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conditioned RTL with XLEN parameter (#1579)
This commit is contained in:
Fatima Saleem
GitHub
parent
1faaec09bc
commit
a99f115d41
3 changed files with 103 additions and 66 deletions
75
core/alu.sv
75
core/alu.sv
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@ -76,16 +76,21 @@ module alu
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operand_a_bitmanip = fu_data_i.operand_a;
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if (ariane_pkg::BITMANIP) begin
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if (riscv::IS_XLEN64) begin
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unique case (fu_data_i.operation)
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SH1ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 1;
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SH2ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 2;
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SH3ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 3;
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CTZW: operand_a_bitmanip = operand_a_rev32;
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ADDUW, CPOPW, CLZW: operand_a_bitmanip = fu_data_i.operand_a[31:0];
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default: ;
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endcase
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end
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unique case (fu_data_i.operation)
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SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1;
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SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2;
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SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3;
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SH1ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 1;
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SH2ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 2;
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SH3ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 3;
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CTZ: operand_a_bitmanip = operand_a_rev;
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CTZW: operand_a_bitmanip = operand_a_rev32;
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ADDUW, CPOPW, CLZW: operand_a_bitmanip = fu_data_i.operand_a[31:0];
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default: ;
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endcase
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end
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@ -209,21 +214,23 @@ module alu
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.cnt_o(lz_tz_count),
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.empty_o(lz_tz_empty)
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);
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//32b
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lzc #(
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.WIDTH(32),
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.MODE (1)
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) i_clz_32b (
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.in_i(operand_a_bitmanip[31:0]),
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.cnt_o(lz_tz_wcount),
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.empty_o(lz_tz_wempty)
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);
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if (riscv::IS_XLEN64) begin
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//32b
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lzc #(
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.WIDTH(32),
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.MODE (1)
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) i_clz_32b (
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.in_i(operand_a_bitmanip[31:0]),
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.cnt_o(lz_tz_wcount),
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.empty_o(lz_tz_wempty)
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);
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end
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end
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if (ariane_pkg::BITMANIP) begin : gen_orcbw_rev8w_results
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assign orcbw = {{8{|fu_data_i.operand_a[31:24]}}, {8{|fu_data_i.operand_a[23:16]}}, {8{|fu_data_i.operand_a[15:8]}}, {8{|fu_data_i.operand_a[7:0]}}};
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assign rev8w = {{fu_data_i.operand_a[7:0]}, {fu_data_i.operand_a[15:8]}, {fu_data_i.operand_a[23:16]}, {fu_data_i.operand_a[31:24]}};
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if (riscv::XLEN == 64) begin : gen_64b
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if (riscv::IS_XLEN64) begin : gen_64b
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assign orcbw_result = {{8{|fu_data_i.operand_a[63:56]}}, {8{|fu_data_i.operand_a[55:48]}}, {8{|fu_data_i.operand_a[47:40]}}, {8{|fu_data_i.operand_a[39:32]}}, orcbw};
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assign rev8w_result = {rev8w , {fu_data_i.operand_a[39:32]}, {fu_data_i.operand_a[47:40]}, {fu_data_i.operand_a[55:48]}, {fu_data_i.operand_a[63:56]}};
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end else begin : gen_32b
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@ -237,25 +244,28 @@ module alu
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// -----------
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always_comb begin
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result_o = '0;
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if (riscv::IS_XLEN64) begin
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unique case (fu_data_i.operation)
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// Add word: Ignore the upper bits and sign extend to 64 bit
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ADDW, SUBW: result_o = {{riscv::XLEN - 32{adder_result[31]}}, adder_result[31:0]};
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SH1ADDUW, SH2ADDUW, SH3ADDUW: result_o = adder_result;
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// Shifts 32 bit
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SLLW, SRLW, SRAW: result_o = {{riscv::XLEN - 32{shift_result32[31]}}, shift_result32[31:0]};
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default: ;
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endcase
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end
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unique case (fu_data_i.operation)
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// Standard Operations
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ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[riscv::XLEN:1];
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ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[riscv::XLEN:1];
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XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[riscv::XLEN:1];
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// Adder Operations
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ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD, SH1ADDUW, SH2ADDUW, SH3ADDUW:
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ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD:
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result_o = adder_result;
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// Add word: Ignore the upper bits and sign extend to 64 bit
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ADDW, SUBW: result_o = {{riscv::XLEN - 32{adder_result[31]}}, adder_result[31:0]};
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// Shift Operations
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SLL, SRL, SRA: result_o = (riscv::XLEN == 64) ? shift_result : shift_result32;
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// Shifts 32 bit
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SLLW, SRLW, SRAW: result_o = {{riscv::XLEN - 32{shift_result32[31]}}, shift_result32[31:0]};
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SLL, SRL, SRA: result_o = (riscv::IS_XLEN64) ? shift_result : shift_result32;
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// Comparison Operations
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SLTS, SLTU: result_o = {{riscv::XLEN - 1{1'b0}}, less};
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default: ; // default case to suppress unique warning
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endcase
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@ -265,6 +275,14 @@ module alu
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// rolw, roriw, rorw
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rolw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
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rorw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
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if (riscv::IS_XLEN64) begin
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unique case (fu_data_i.operation)
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CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount}; // change
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ROLW: result_o = {{riscv::XLEN - 32{rolw[31]}}, rolw};
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RORW, RORIW: result_o = {{riscv::XLEN - 32{rorw[31]}}, rorw};
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default: ;
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endcase
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end
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unique case (fu_data_i.operation)
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// Left Shift 32 bit unsigned
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SLLIUW:
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@ -285,7 +303,6 @@ module alu
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CLZ, CTZ:
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result_o = (lz_tz_empty) ? ({{riscv::XLEN - $clog2(riscv::XLEN) {1'b0}}, lz_tz_count} + 1) :
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{{riscv::XLEN - $clog2(riscv::XLEN) {1'b0}}, lz_tz_count};
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CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount};
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// Count population
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CPOP, CPOPW: result_o = {{(riscv::XLEN - ($clog2(riscv::XLEN) + 1)) {1'b0}}, cpop};
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@ -297,11 +314,11 @@ module alu
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// Bitwise Rotation
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ROL:
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result_o = (riscv::XLEN == 64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[4:0])));
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ROLW: result_o = {{riscv::XLEN - 32{rolw[31]}}, rolw};
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result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[4:0])));
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ROR, RORI:
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result_o = (riscv::XLEN == 64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));
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RORW, RORIW: result_o = {{riscv::XLEN - 32{rorw[31]}}, rorw};
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result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));
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ORCB:
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result_o = orcbw_result;
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REV8:
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@ -100,7 +100,7 @@ module compressed_decoder #(
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// c.ld -> ld rd', imm(rs1')
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// RV32
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// c.flw -> flw fprd', imm(rs1')
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if (riscv::XLEN == 64) begin
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if (riscv::IS_XLEN64) begin
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// CLD: | funct3 | imm[5:3] | rs1' | imm[7:6] | rd' | C0 |
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instr_o = {
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4'b0,
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@ -136,7 +136,7 @@ module compressed_decoder #(
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if (CVA6Cfg.RVZCB) begin
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unique case (instr_i[12:10])
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3'b000: begin
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// c.lbu -> lbu rd', uimm(rs1')
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// c.lbu -> lbu rd', uimm(rs1')
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instr_o = {
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10'b0,
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instr_i[5],
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@ -152,7 +152,7 @@ module compressed_decoder #(
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3'b001: begin
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if (instr_i[6]) begin
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// c.lh -> lh rd', uimm(rs1')
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// c.lh -> lh rd', uimm(rs1')
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instr_o = {
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10'b0,
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instr_i[5],
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@ -181,7 +181,7 @@ module compressed_decoder #(
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end
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3'b010: begin
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// c.sb -> sb rs2', uimm(rs1')
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// c.sb -> sb rs2', uimm(rs1')
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instr_o = {
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7'b0,
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2'b01,
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@ -263,7 +263,7 @@ module compressed_decoder #(
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// c.sd -> sd rs2', imm(rs1')
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// RV32
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// c.fsw -> fsw fprs2', imm(rs1')
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if (riscv::XLEN == 64) begin
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if (riscv::IS_XLEN64) begin
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instr_o = {
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4'b0,
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instr_i[6:5],
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@ -320,7 +320,7 @@ module compressed_decoder #(
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riscv::OpcodeC1Addiw: begin // or riscv::OpcodeC1Jal for RV32IC
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if (riscv::XLEN == 64) begin
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if (riscv::IS_XLEN64) begin
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// c.addiw -> addiw rd, rd, nzimm for RV64IC
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if (instr_i[11:7] != 5'h0) begin // only valid if the destination is not r0
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instr_o = {
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@ -493,34 +493,43 @@ module compressed_decoder #(
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end
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3'b100: begin
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// c.subw -> subw rd', rd', rs2'
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instr_o = {
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2'b01,
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5'b0,
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2'b01,
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instr_i[4:2],
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2'b01,
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instr_i[9:7],
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3'b000,
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2'b01,
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instr_i[9:7],
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riscv::OpcodeOp32
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};
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if (riscv::IS_XLEN64) begin
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// c.subw -> subw rd', rd', rs2'
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instr_o = {
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2'b01,
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5'b0,
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2'b01,
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instr_i[4:2],
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2'b01,
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instr_i[9:7],
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3'b000,
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2'b01,
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instr_i[9:7],
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riscv::OpcodeOp32
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};
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end else begin
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illegal_instr_o = 1'b1;
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end
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end
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3'b101: begin
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// c.addw -> addw rd', rd', rs2'
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instr_o = {
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2'b00,
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5'b0,
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2'b01,
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instr_i[4:2],
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2'b01,
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instr_i[9:7],
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3'b000,
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2'b01,
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instr_i[9:7],
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riscv::OpcodeOp32
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};
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if (riscv::IS_XLEN64) begin
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// c.addw -> addw rd', rd', rs2'
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instr_o = {
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2'b00,
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5'b0,
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2'b01,
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instr_i[4:2],
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2'b01,
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instr_i[9:7],
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3'b000,
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2'b01,
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instr_i[9:7],
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riscv::OpcodeOp32
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};
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end else begin
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illegal_instr_o = 1'b1;
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end
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end
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3'b110: begin
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@ -581,7 +590,7 @@ module compressed_decoder #(
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3'b010: begin
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if (ariane_pkg::BITMANIP) begin
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// c.zext.h -> zext.h rd', rd'
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if (riscv::XLEN == 64) begin
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if (riscv::IS_XLEN64) begin
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instr_o = {
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7'h4,
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5'h0,
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@ -626,7 +635,7 @@ module compressed_decoder #(
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3'b100: begin
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if (ariane_pkg::BITMANIP) begin
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// c.zext.w -> add.uw
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if (riscv::XLEN == 64) begin
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if (riscv::IS_XLEN64) begin
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instr_o = {
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7'h4,
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5'h0,
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@ -759,7 +768,7 @@ module compressed_decoder #(
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// c.ldsp -> ld rd, imm(x2)
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// RV32
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// c.flwsp -> flw fprd, imm(x2)
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if (riscv::XLEN == 64) begin
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if (riscv::IS_XLEN64) begin
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instr_o = {
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3'b0,
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instr_i[4:2],
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@ -847,7 +856,7 @@ module compressed_decoder #(
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// c.sdsp -> sd rs2, imm(x2)
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// RV32
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// c.fswsp -> fsw fprs2, imm(x2)
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if (riscv::XLEN == 64) begin
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if (riscv::IS_XLEN64) begin
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instr_o = {
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3'b0,
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instr_i[9:7],
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@ -50,6 +50,7 @@ module decoder
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logic illegal_instr_bm;
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logic illegal_instr_zic;
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logic illegal_instr_non_bm;
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logic illegal_instr_non_zexth;
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// this instruction is an environment call (ecall), it is handled like an exception
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logic ecall;
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// this instruction is a software break-point
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@ -107,6 +108,7 @@ module decoder
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illegal_instr_non_bm = 1'b0;
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illegal_instr_bm = 1'b0;
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illegal_instr_zic = 1'b0;
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illegal_instr_non_zexth = 1'b0;
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instruction_o.pc = pc_i;
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instruction_o.trans_id = '0;
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instruction_o.fu = NONE;
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@ -629,6 +631,15 @@ module decoder
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instruction_o.rs1[4:0] = instr.rtype.rs1;
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instruction_o.rs2[4:0] = instr.rtype.rs2;
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instruction_o.rd[4:0] = instr.rtype.rd;
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if (ariane_pkg::BITMANIP) begin
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unique case ({
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instr.rtype.funct7, instr.rtype.funct3
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})
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// Zero Extend Op
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{7'b000_0100, 3'b100}: instruction_o.op = ariane_pkg::ZEXTH; // zext
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default: illegal_instr_non_zexth = 1'b1;
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endcase
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end
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if (riscv::IS_XLEN64) begin
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unique case ({
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instr.rtype.funct7, instr.rtype.funct3
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@ -667,7 +678,7 @@ module decoder
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end else begin
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illegal_instr = illegal_instr_non_bm;
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end
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end else illegal_instr = 1'b1;
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end else illegal_instr = ~illegal_instr_non_zexth;
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end
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// --------------------------------
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// Reg-Immediate Operations
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