[gen_from_riscv_config] improve readme file and requirements file to support spike (#2380)

config/gen_from_riscv_config/README.md

@@ -34,11 +34,14 @@ pip3 install -r requirements.txt
 
 ```bash
 #Generate Restructred-text documentation for Control and Status Registers (CSR)
-python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -c <../riscv-config/Config_Name/generated/custom_gen>.yaml-m <updaters/Config_Name/csr_updater>.yaml -t < Config_Name>
+python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -c <../riscv-config/Config_Name/generated/custom_gen>.yaml -m <updaters/Config_Name/csr_updater>.yaml -t < Config_Name>
 
 #Generate Restructred-text documentation for ISA extensions
 python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -i <templates/isa_template>.yaml -m <updaters/Config_Name/isa_updater>.yaml -t < Config_Name>
 
+#Generate  the Yaml spike configuration file 
+python3 <scripts/riscv_config_gen>.py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -c <../riscv-config/Config_Name/generated/custom_gen>.yaml  -i <templates/spike>.mako -m <updaters/Config_Name/spike_updater>.yaml -t < Config_Name>
+
 ```
 
 ##  Usage with cv32a65x 
@@ -50,6 +53,9 @@ python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_ge
 #Generate  the Restructred-text documentation for ISA extensions
 python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/cv32a65x/isa_updater.yaml -t cv32a65x
 
+#Generate  the Yaml spike configuration file  
+python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -c ../riscv-config/cv32a65x/generated/custom_gen.yaml -i templates/spike.mako -m updaters/cv32a65x/spike_updater.yaml -t cv32a65x
+
 ```
  
 You could find your output files in this directory : 
@@ -59,12 +65,18 @@ if the output is ISA Documentation:
                 
 if the output is CSR Documentation :
                 `<Config_Name>/csr/`
+                
+if the output is Spike yaml :
+                `<Config_Name>/spike/`
+
                
                 
                 
-for more details about How to write CSR or ISA Updater,see [UPDATERS](##Updaters) section
+for more details about How to write CSR or ISA Updater,see [Updaters](#updaters) section
 
-for more details about How to write ISA template ,see [Annexes2](##Annexes2) section
+for more details about How to write ISA template ,see [Annexes2](#annexes2) section
+
+for more details about How to write spike template , see [mako](https://www.makotemplates.org/) section
 
 
 
@@ -130,7 +142,7 @@ Example : ISA_Updater.yaml
      
 -If  you want to modify any parameter for registers in RISC CONFIG YAML  :
       
- Format : 
+- Format :  
  
                 Register name :
                        sub_feature : 
@@ -146,7 +158,7 @@ Example : ISA_Updater.yaml
                     
 -If you want to exclude any registers base on condition :
        
- Format : 
+- Format :  
                 
                 exclude :
                         
@@ -155,7 +167,7 @@ Example : ISA_Updater.yaml
                         sub_key : sub_value (if exist if not dont include it )
                         
                         cond: value
- Exemple : 
+- Exemple : 
                
                 exclude : 
                 
@@ -168,12 +180,12 @@ Example : ISA_Updater.yaml
        
     Example : (PMPADDR , MHPMCOUNTER, ...)
              
-Format :
+- Format :
            
                   Register Name :
             
                         range : number
-Exemple : 
+- Exemple : 
            
                     pmpaddr :
                     
@@ -184,6 +196,54 @@ CSR/ISA Updater read RISC-CONFIG.yaml and update the registers so if you want to
 
 
 
+### SPIKE Updater
+
+     
+-If  you want to modify any parameter Spike yaml:
+       
+- Format : 
+ 
+                <parameter name> : <parameter value> 
+
+- Example :
+ 
+ 
+                bootrom: false
+         
+-If you want to to modify any parameter in core config in Spike yaml :
+       
+- Format : 
+                
+                cores:
+                        
+                       <parameter name> : <parameter value> 
+- Exemple : 
+- Exemple : 
+               
+                cores: 
+                   isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei
+                   boot_addr: 0x80000000
+                   marchid: 0x3
+                   misa_we: false
+                   misa_we_enable: true
+                   pmpaddr0: 0x0
+                   pmpcfg0: 0x0
+                   pmpregions: 0x40
+                   usable_pmpregions : 0x8
+                   priv: M
+                   status_fs_field_we: false
+                   status_fs_field_we_enable: false
+                   status_vs_field_we: false
+                   status_vs_field_we_enable: false
+                   misa_we: false
+                   mstatus_write_mask: 0x00000088
+                   mstatus_override_mask: 0x00001800
+                   mtval_write_mask: 0x00000000
+                   unified_traps: true
+
+                 
+Spike Updater read spike.yaml and update the parameters  so if you want to add parameter in spike.yaml  you need to respect it architecture.
+
 
 ## Annexes
 

config/gen_from_riscv_config/requirements.txt

@@ -3,4 +3,5 @@ pyyaml
 mdutils
 restructuredtext-lint
 rstcloth
-regex
+regex
+Mako

config/gen_from_riscv_config/scripts/libs/spike_updater.py

@@ -0,0 +1,74 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Oukalrazqou Abdessamii
+
+
+""" Module is used to update Spike based on yaml file called  spike updater """
+import re
+import yaml
+from yaml import BaseLoader
+
+
+def spike_recursive_update(original_dict, spike_update):
+    """
+    Gets the data of the RISC-V Config Yaml file and
+    update the value of sub key in RISC-V Config Yaml file
+    (ex: priv , pmpaddr)
+    :param original_dict : parsed data of  Spike Yaml file
+           spike_update : parsed data of   Spike updaters
+    :return: data of Spike Yaml file updated
+    """
+    for key, value in spike_update.items():
+        if key in original_dict:
+            if isinstance(value, dict) and isinstance(original_dict[key], dict):
+                if key == "cores":
+                    original_dict[key] = value
+                else:
+                    csr_recursive_update(original_dict[key], value)
+            else:
+                original_dict[key] = value
+
+
+def is_hex_string(s):
+    return bool(re.match(r"'?(0x[0-9a-fA-F]+)'?", s))
+
+
+def custom_convert(data):
+    if isinstance(data, dict):
+        return {k: custom_convert(v) for k, v in data.items()}
+    elif isinstance(data, list):
+        return [custom_convert(item) for item in data]
+    elif isinstance(data, str):
+        if data.lower() == "true":
+            return True
+        elif data.lower() == "false":
+            return False
+        elif data.isdigit():
+            return int(data)
+        elif is_hex_string(data.strip()):
+            return int(data, 16)
+    return data
+
+
+def spike_formatter(original_dict, modifile):
+    # Read original dictionary from YAML  Source file
+    updated_values = {}
+    if modifile is not None:
+        with open(modifile, "r", encoding="utf-8") as file:
+            updated_values = yaml.load(file, Loader=BaseLoader)
+    # Update original_dict with values from updated_values recursively
+    spike_recursive_update(original_dict["spike_param_tree"], updated_values)
+    original_dict = custom_convert(original_dict)
+    return original_dict

config/gen_from_riscv_config/templates/spike.mako

@@ -0,0 +1,53 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Oukalrazqou Abdessamii
+
+<%!
+def format_hex(value):
+    return f"0x{value:X}"
+
+def format_bool(value):
+    return "true" if value else "false"
+%>
+spike_param_tree:
+  bootrom: ${format_bool(spike.bootrom)}
+  bootrom_base: ${format_hex(spike.bootrom_base)}
+  bootrom_size: ${format_hex(spike.bootrom_size)}
+  dram: ${format_bool(spike.dram)}
+  dram_base: ${format_hex(spike.dram_base)}
+  dram_size: ${format_hex(spike.dram_size)}
+  generic_core_config: ${format_bool(spike.generic_core_config)}
+  max_steps: ${spike.max_steps}
+  max_steps_enabled: ${format_bool(spike.max_steps_enabled)}
+  isa: ${spike.isa}
+  priv: ${spike.priv}
+  core_configs:
+% for core in spike.core_configs:
+    - isa: ${core.isa}
+      marchid: ${format_hex(core.marchid)}
+      misa_we: ${format_bool(core.misa_we)}
+      misa_we_enable: ${format_bool(core.misa_we_enable)}
+      misaligned: ${format_bool(core.misaligned)}
+      mmu_mode: ${core.mmu_mode}
+      mvendorid: ${format_hex(core.mvendorid)}
+      pmpaddr0: ${format_hex(core.pmpaddr0)}
+      pmpcfg0: ${format_hex(core.pmpcfg0)}
+      pmpregions: ${format_hex(core.pmpregions)}
+      priv: ${core.priv}
+      status_fs_field_we: ${format_bool(core.status_fs_field_we)}
+      status_fs_field_we_enable: ${format_bool(core.status_fs_field_we_enable)}
+      status_vs_field_we: ${format_bool(core.status_vs_field_we)}
+      status_vs_field_we_enable: ${format_bool(core.status_vs_field_we_enable)}
+% endfor

config/gen_from_riscv_config/updaters/cv32a65x/spike_updater.yaml

@@ -0,0 +1,31 @@
+#   Copyright (c) 2024 OpenHW Group
+#   Copyright (c) 2024 Thales
+#   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#   Author: Abdessamii Oukalrazqou
+
+
+
+
+
+cores:
+    - isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei
+      boot_addr: 0x80000000
+      marchid: 0x3
+      misa_we: false
+      misa_we_enable: true
+      pmpaddr0: 0x0
+      pmpcfg0: 0x0
+      pmpregions: 0x40
+      usable_pmpregions : 0x8
+      priv: M
+      status_fs_field_we: false
+      status_fs_field_we_enable: false
+      status_vs_field_we: false
+      status_vs_field_we_enable: false
+      priv: M
+      misa_we: false
+      mstatus_write_mask: 0x00000088
+      mstatus_override_mask: 0x00001800
+      mtval_write_mask: 0x00000000
+      unified_traps: true
+