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Update riscv-config infra to better match expressivity needs of CV32A65X. (#2193)

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Zbigniew Chamski 2024-06-04 18:12:14 +02:00 • committed by GitHub
parent 721fa0c175
commit aa76752f18
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GPG key ID: B5690EEEBB952194
6 changed files with 137 additions and 4 deletions
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7
config/riscv-config/Makefile
View file

@ -42,5 +42,8 @@ $(RVCONFIG_OUTPUTS): $(RVCONFIG_INPUTS) Makefile
-cspec $(SPEC_DIR)/custom_spec.yaml \
-pspec $(SPEC_DIR)/platform_spec.yaml
clean:
$(RM) $(OUTPUT_FILES) $(RVCONFIG_OUTPUTS)
clean: distclean
$(RM) $(OUTPUT_FILES)
distclean:
$(RM) run.log $(RVCONFIG_OUTPUTS)

18
vendor/patches/riscv/riscv-config/0001-enable-implied-B-ext.patch vendored Normal file
View file

@ -0,0 +1,18 @@
diff --git a/vendor/riscv/riscv-config/riscv_config/isa_validator.py b/vendor/riscv/riscv-config/riscv_config/isa_validator.py
index 94f7412ae..9655258b3 100644
--- a/vendor/riscv/riscv-config/riscv_config/isa_validator.py
+++ b/vendor/riscv/riscv-config/riscv_config/isa_validator.py
@@ -60,7 +60,12 @@ def get_extension_list(isa):
elif a1 == a2 and a3 > a4:
err = True
err_list.append( f"Within the Z{a1.lower()} category extension {zext_list[i]} must occur after {zext_list[i+1]}")
-
+ if 'B' not in extension_list and (set(['Zba', 'Zbb', 'Zbs']) & set(extension_list) == set(['Zba', 'Zbb', 'Zbs'])):
+ # Insert 'B' at correct location: after any of its predecessors in canonical ordering.
+ # At least 'I' or 'E' must be present by definition.
+ B_preds = canonical_ordering[:canonical_ordering.find('B')]
+ lastpred_B_idx = max([pos for pos, char in enumerate(standard_isa) if char in list(B_preds)])
+ extension_list.insert(lastpred_B_idx + 1, 'B')
if 'I' not in extension_list and 'E' not in extension_list:
err_list.append( 'Either of I or E base extensions need to be present in the ISA string')
err = True

54
vendor/patches/riscv/riscv-config/0002-add-mstatus-UBE-bit.patch vendored Normal file
View file

@ -0,0 +1,54 @@
diff --git a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
index 981ee6247..a972efb14 100644
--- a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
+++ b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
@@ -636,6 +636,24 @@ hart_schema:
- 0:1
default: {implemented: false}
check_with: s_check
+ ube:
+ type: dict
+ schema:
+ description: { type: string, default: control the endianness of memory accesses other than instruction fetches for user mode}
+ shadow: {type: string, default: , nullable: True}
+ shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']}
+ msb: {type: integer, default: 6, allowed: [6]}
+ lsb: {type: integer, default: 6, allowed: [6]}
+ implemented: {type: boolean, default: true}
+ type:
+ type: dict
+ oneof:
+ - schema: { warl: *ref_warl }
+ - schema: {ro_constant: {type: integer, max: 0 , min : 0}}
+ - schema: { wlrl: *ref_wlrl }
+ default: {ro_constant: 0}
+ default: {implemented: false}
+ check_with: u_check
mpie:
type: dict
schema:
@@ -1049,6 +1067,24 @@ hart_schema:
- 0:1
default: {implemented: false}
check_with: s_check
+ ube:
+ type: dict
+ schema:
+ description: { type: string, default: control the endianness of memory accesses other than instruction fetches for user mode}
+ shadow: {type: string, default: , nullable: True}
+ shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']}
+ msb: {type: integer, default: 6, allowed: [6]}
+ lsb: {type: integer, default: 6, allowed: [6]}
+ implemented: {type: boolean, default: true}
+ type:
+ type: dict
+ oneof:
+ - schema: { warl: *ref_warl }
+ - schema: {ro_constant: {type: integer, max: 0 , min : 0}}
+ - schema: { wlrl: *ref_wlrl }
+ default: {ro_constant: 0}
+ default: {implemented: false}
+ check_with: u_check
mpie:
type: dict
schema:

15
vendor/patches/riscv/riscv-config/0003-add-mtval-roconst0-schema.patch vendored Normal file
View file

@ -0,0 +1,15 @@
diff --git a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
index a972efb14..a7536375f 100644
--- a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
+++ b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
@@ -3594,7 +3594,9 @@ hart_schema:
lsb: {type: integer, default: 0, allowed: [0]}
type:
type: dict
- schema: { warl: *ref_warl }
+ oneof:
+ - schema: { ro_constant: {type: integer, default: 0x0, allowed: [0x0]}}
+ - schema: { warl: *ref_warl }
default:
warl:
dependency_fields: []

7
vendor/riscv/riscv-config/riscv_config/isa_validator.py vendored
View file

@ -60,7 +60,12 @@ def get_extension_list(isa):
elif a1 == a2 and a3 > a4:
err = True
err_list.append( f"Within the Z{a1.lower()} category extension {zext_list[i]} must occur after {zext_list[i+1]}")
if 'B' not in extension_list and (set(['Zba', 'Zbb', 'Zbs']) & set(extension_list) == set(['Zba', 'Zbb', 'Zbs'])):
# Insert 'B' at correct location: after any of its predecessors in canonical ordering.
# At least 'I' or 'E' must be present by definition.
B_preds = canonical_ordering[:canonical_ordering.find('B')]
lastpred_B_idx = max([pos for pos, char in enumerate(standard_isa) if char in list(B_preds)])
extension_list.insert(lastpred_B_idx + 1, 'B')
if 'I' not in extension_list and 'E' not in extension_list:
err_list.append( 'Either of I or E base extensions need to be present in the ISA string')
err = True

40
vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml vendored
View file

@ -636,6 +636,24 @@ hart_schema:
- 0:1
default: {implemented: false}
check_with: s_check
ube:
type: dict
schema:
description: { type: string, default: control the endianness of memory accesses other than instruction fetches for user mode}
shadow: {type: string, default: , nullable: True}
shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']}
msb: {type: integer, default: 6, allowed: [6]}
lsb: {type: integer, default: 6, allowed: [6]}
implemented: {type: boolean, default: true}
type:
type: dict
oneof:
- schema: { warl: *ref_warl }
- schema: {ro_constant: {type: integer, max: 0 , min : 0}}
- schema: { wlrl: *ref_wlrl }
default: {ro_constant: 0}
default: {implemented: false}
check_with: u_check
mpie:
type: dict
schema:
@ -1049,6 +1067,24 @@ hart_schema:
- 0:1
default: {implemented: false}
check_with: s_check
ube:
type: dict
schema:
description: { type: string, default: control the endianness of memory accesses other than instruction fetches for user mode}
shadow: {type: string, default: , nullable: True}
shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']}
msb: {type: integer, default: 6, allowed: [6]}
lsb: {type: integer, default: 6, allowed: [6]}
implemented: {type: boolean, default: true}
type:
type: dict
oneof:
- schema: { warl: *ref_warl }
- schema: {ro_constant: {type: integer, max: 0 , min : 0}}
- schema: { wlrl: *ref_wlrl }
default: {ro_constant: 0}
default: {implemented: false}
check_with: u_check
mpie:
type: dict
schema:
@ -3558,7 +3594,9 @@ hart_schema:
lsb: {type: integer, default: 0, allowed: [0]}
type:
type: dict
schema: { warl: *ref_warl }
oneof:
- schema: { ro_constant: {type: integer, default: 0x0, allowed: [0x0]}}
- schema: { warl: *ref_warl }
default:
warl:
dependency_fields: []