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cva6_icache: Fix formatting (#2770)

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Run verible verilog format to fix upstream formatting.

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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Nils Wistoff 2025-02-14 07:24:31 +11:00 • committed by GitHub
parent 7b759a8b71
commit abf21ee221
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1 changed files with 2 additions and 2 deletions
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core/cache_subsystem/cva6_icache.sv
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@ -424,8 +424,8 @@ module cva6_icache
logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] hit_idx;
for (genvar i = 0; i < CVA6Cfg.ICACHE_SET_ASSOC; i++) begin : gen_tag_cmpsel
assign cl_hit[i] = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i];
assign cl_sel[i] = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH];
assign cl_hit[i] = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i];
assign cl_sel[i] = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH];
assign cl_user[i] = CVA6Cfg.FETCH_USER_EN ? cl_ruser[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH] : '0;
end