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move functions into modules (#1926)

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Côme 2024-03-13 17:46:33 +01:00 • committed by GitHub
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43 changed files with 449 additions and 494 deletions
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8
core/acc_dispatcher.sv
View file

@ -27,8 +27,8 @@ module acc_dispatcher
logic req_valid;
logic resp_ready;
riscv::instruction_t insn;
riscv::xlen_t rs1;
riscv::xlen_t rs2;
logic [riscv::XLEN-1:0] rs1;
logic [riscv::XLEN-1:0] rs2;
fpnew_pkg::roundmode_e frm;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
logic store_pending;
@ -40,7 +40,7 @@ module acc_dispatcher
parameter type acc_resp_t = struct packed {
logic req_ready;
logic resp_valid;
riscv::xlen_t result;
logic [riscv::XLEN-1:0] result;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
logic error;
// Metadata
@ -76,7 +76,7 @@ module acc_dispatcher
input fu_data_t fu_data_i,
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
output logic [TRANS_ID_BITS-1:0] acc_trans_id_o,
output xlen_t acc_result_o,
output logic [riscv::XLEN-1:0] acc_result_o,
output logic acc_valid_o,
output exception_t acc_exception_o,
// Interface with the execute stage

42
core/alu.sv
View file

@ -31,24 +31,24 @@ module alu
// FU data needed to execute instruction - ISSUE_STAGE
input fu_data_t fu_data_i,
// ALU result - ISSUE_STAGE
output riscv::xlen_t result_o,
output logic [riscv::XLEN-1:0] result_o,
// ALU branch compare result - branch_unit
output logic alu_branch_res_o
);
riscv::xlen_t operand_a_rev;
logic [ 31:0] operand_a_rev32;
logic [ riscv::XLEN:0] operand_b_neg;
logic [riscv::XLEN+1:0] adder_result_ext_o;
logic less; // handles both signed and unsigned forms
logic [ 31:0] rolw; // Rotate Left Word
logic [ 31:0] rorw; // Rotate Right Word
logic [riscv::XLEN-1:0] operand_a_rev;
logic [ 31:0] operand_a_rev32;
logic [ riscv::XLEN:0] operand_b_neg;
logic [riscv::XLEN+1:0] adder_result_ext_o;
logic less; // handles both signed and unsigned forms
logic [ 31:0] rolw; // Rotate Left Word
logic [ 31:0] rorw; // Rotate Right Word
logic [31:0] orcbw, rev8w;
logic [ $clog2(riscv::XLEN) : 0] cpop; // Count Population
logic [$clog2(riscv::XLEN)-1 : 0] lz_tz_count; // Count Leading Zeros
logic [ 4:0] lz_tz_wcount; // Count Leading Zeros Word
logic lz_tz_empty, lz_tz_wempty;
riscv::xlen_t orcbw_result, rev8w_result;
logic [riscv::XLEN-1:0] orcbw_result, rev8w_result;
// bit reverse operand_a for left shifts and bit counting
generate
@ -65,7 +65,7 @@ module alu
logic adder_op_b_negate;
logic adder_z_flag;
logic [riscv::XLEN:0] adder_in_a, adder_in_b;
riscv::xlen_t adder_result;
logic [riscv::XLEN-1:0] adder_result;
logic [riscv::XLEN-1:0] operand_a_bitmanip, bit_indx;
always_comb begin
@ -132,21 +132,21 @@ module alu
// ---------
// TODO: this can probably optimized significantly
logic shift_left; // should we shift left
logic shift_arithmetic;
logic shift_left; // should we shift left
logic shift_arithmetic;
riscv::xlen_t shift_amt; // amount of shift, to the right
riscv::xlen_t shift_op_a; // input of the shifter
logic [ 31:0] shift_op_a32; // input to the 32 bit shift operation
logic [riscv::XLEN-1:0] shift_amt; // amount of shift, to the right
logic [riscv::XLEN-1:0] shift_op_a; // input of the shifter
logic [ 31:0] shift_op_a32; // input to the 32 bit shift operation
riscv::xlen_t shift_result;
logic [ 31:0] shift_result32;
logic [riscv::XLEN-1:0] shift_result;
logic [ 31:0] shift_result32;
logic [riscv::XLEN:0] shift_right_result;
logic [ 32:0] shift_right_result32;
logic [ riscv::XLEN:0] shift_right_result;
logic [ 32:0] shift_right_result32;
riscv::xlen_t shift_left_result;
logic [ 31:0] shift_left_result32;
logic [riscv::XLEN-1:0] shift_left_result;
logic [ 31:0] shift_left_result32;
assign shift_amt = fu_data_i.operand_b;

4
core/amo_buffer.sv
View file

@ -25,7 +25,7 @@ module amo_buffer #(
output logic ready_o, // AMO unit is ready
input ariane_pkg::amo_t amo_op_i, // AMO Operation
input logic [riscv::PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue
input riscv::xlen_t data_i, // data which is placed in the queue
input logic [riscv::XLEN-1:0] data_i, // data which is placed in the queue
input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write)
// D$
output ariane_pkg::amo_req_t amo_req_o, // request to cache subsytem
@ -40,7 +40,7 @@ module amo_buffer #(
typedef struct packed {
ariane_pkg::amo_t op;
logic [riscv::PLEN-1:0] paddr;
riscv::xlen_t data;
logic [riscv::XLEN-1:0] data;
logic [1:0] size;
} amo_op_t;

8
core/cache_subsystem/cva6_hpdcache_subsystem.sv
View file

@ -137,7 +137,7 @@ module cva6_hpdcache_subsystem
logic icache_miss_resp_valid;
icache_rtrn_t icache_miss_resp;
localparam int ICACHE_RDTXID = 1 << (ariane_pkg::MEM_TID_WIDTH - 1);
localparam int ICACHE_RDTXID = 1 << (CVA6Cfg.MEM_TID_WIDTH - 1);
cva6_icache #(
.CVA6Cfg(CVA6Cfg),
@ -182,7 +182,7 @@ module cva6_hpdcache_subsystem
localparam int HPDCACHE_NREQUESTERS = NumPorts + 2;
typedef logic [riscv::PLEN-1:0] hpdcache_mem_addr_t;
typedef logic [ariane_pkg::MEM_TID_WIDTH-1:0] hpdcache_mem_id_t;
typedef logic [CVA6Cfg.MEM_TID_WIDTH-1:0] hpdcache_mem_id_t;
typedef logic [CVA6Cfg.AxiDataWidth-1:0] hpdcache_mem_data_t;
typedef logic [CVA6Cfg.AxiDataWidth/8-1:0] hpdcache_mem_be_t;
`HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t);
@ -426,7 +426,7 @@ module cva6_hpdcache_subsystem
hpdcache #(
.NREQUESTERS (HPDCACHE_NREQUESTERS),
.HPDcacheMemAddrWidth(riscv::PLEN),
.HPDcacheMemIdWidth (ariane_pkg::MEM_TID_WIDTH),
.HPDcacheMemIdWidth (CVA6Cfg.MEM_TID_WIDTH),
.HPDcacheMemDataWidth(CVA6Cfg.AxiDataWidth)
) i_hpdcache (
.clk_i,
@ -520,7 +520,7 @@ module cva6_hpdcache_subsystem
// AXI arbiter instantiation
// {{{
cva6_hpdcache_subsystem_axi_arbiter #(
.HPDcacheMemIdWidth (ariane_pkg::MEM_TID_WIDTH),
.HPDcacheMemIdWidth (CVA6Cfg.MEM_TID_WIDTH),
.HPDcacheMemDataWidth (CVA6Cfg.AxiDataWidth),
.hpdcache_mem_req_t (hpdcache_mem_req_t),
.hpdcache_mem_req_w_t (hpdcache_mem_req_w_t),

10
core/cache_subsystem/cva6_icache.sv
View file

@ -37,7 +37,7 @@ module cva6_icache
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
/// ID to be used for read transactions
parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0
parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdTxId = 0
) (
input logic clk_i,
input logic rst_ni,
@ -62,6 +62,10 @@ module cva6_icache
output icache_req_t mem_data_o
);
localparam ICACHE_OFFSET_WIDTH = $clog2(ariane_pkg::ICACHE_LINE_WIDTH / 8);
localparam ICACHE_NUM_WORDS = 2 ** (ariane_pkg::ICACHE_INDEX_WIDTH - ICACHE_OFFSET_WIDTH);
localparam ICACHE_CL_IDX_WIDTH = $clog2(ICACHE_NUM_WORDS); // excluding byte offset
// functions
function automatic logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] icache_way_bin2oh(
input logic [L1I_WAY_WIDTH-1:0] in);
@ -551,8 +555,8 @@ module cva6_icache
else $fatal(1, "[l1 icache] cl_hit signal must be hot1");
// this is only used for verification!
logic vld_mirror[wt_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
logic [ariane_pkg::ICACHE_TAG_WIDTH-1:0] tag_mirror[wt_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
logic vld_mirror[ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
logic [ariane_pkg::ICACHE_TAG_WIDTH-1:0] tag_mirror[ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] tag_write_duplicate_test;
always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror

20
core/cache_subsystem/miss_handler.sv
View file

@ -71,6 +71,26 @@ module miss_handler
// Three MSHR ports + AMO port
parameter NR_BYPASS_PORTS = NR_PORTS + 1;
// convert one hot to bin for -> needed for cache replacement
function automatic logic [std_cache_pkg::DCACHE_SET_ASSOC_WIDTH-1:0] one_hot_to_bin(
input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] in);
for (int unsigned i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin
if (in[i]) return i;
end
endfunction
// get the first bit set, returns one hot value
function automatic logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] get_victim_cl(
input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] valid_dirty);
// one-hot return vector
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] oh = '0;
for (int unsigned i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin
if (valid_dirty[i]) begin
oh[i] = 1'b1;
return oh;
end
end
endfunction
// FSM states
enum logic [3:0] {
IDLE, // 0

12
core/cache_subsystem/wt_axi_adapter.sv
View file

@ -97,9 +97,9 @@ module wt_axi_adapter
// AMO generates r beat
logic amo_gen_r_d, amo_gen_r_q;
logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q;
logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q;
logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid;
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q;
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q;
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid;
logic dcache_rd_pop, dcache_wr_pop;
logic icache_rd_full, icache_rd_empty;
logic dcache_rd_full, dcache_rd_empty;
@ -352,7 +352,7 @@ module wt_axi_adapter
logic icache_rtrn_vld_d, icache_rtrn_vld_q, dcache_rtrn_vld_d, dcache_rtrn_vld_q;
fifo_v3 #(
.DATA_WIDTH(wt_cache_pkg::CACHE_ID_WIDTH),
.DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH),
.DEPTH (MetaFifoDepth)
) i_rd_icache_id (
.clk_i (clk_i),
@ -369,7 +369,7 @@ module wt_axi_adapter
);
fifo_v3 #(
.DATA_WIDTH(wt_cache_pkg::CACHE_ID_WIDTH),
.DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH),
.DEPTH (MetaFifoDepth)
) i_rd_dcache_id (
.clk_i (clk_i),
@ -386,7 +386,7 @@ module wt_axi_adapter
);
fifo_v3 #(
.DATA_WIDTH(wt_cache_pkg::CACHE_ID_WIDTH),
.DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH),
.DEPTH (MetaFifoDepth)
) i_wr_dcache_id (
.clk_i (clk_i),

6
core/cache_subsystem/wt_cache_subsystem.sv
View file

@ -88,10 +88,10 @@ module wt_cache_subsystem
logic [2:0] size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
logic [L1D_WAY_WIDTH-1:0] way; // way to replace
logic [riscv::PLEN-1:0] paddr; // physical address
riscv::xlen_t data; // word width of processor (no block stores at the moment)
logic [riscv::XLEN-1:0] data; // word width of processor (no block stores at the moment)
logic [ariane_pkg::DATA_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment)
logic nc; // noncacheable
logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
ariane_pkg::amo_t amo_op; // amo opcode
};
@ -100,7 +100,7 @@ module wt_cache_subsystem
logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // full cache line width
logic [ariane_pkg::DCACHE_USER_LINE_WIDTH-1:0] user; // user bits
dcache_inval_t inv; // invalidation vector
logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
};
logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld;

94
core/cache_subsystem/wt_dcache.sv
View file

@ -25,7 +25,7 @@ module wt_dcache
parameter int unsigned NumPorts = 4, // number of miss ports
// ID to be used for read and AMO transactions.
// note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1
parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdAmoTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
@ -57,7 +57,7 @@ module wt_dcache
localparam type wbuffer_t = struct packed {
logic [ariane_pkg::DCACHE_TAG_WIDTH+(ariane_pkg::DCACHE_INDEX_WIDTH-riscv::XLEN_ALIGN_BYTES)-1:0] wtag;
riscv::xlen_t data;
logic [riscv::XLEN-1:0] data;
logic [ariane_pkg::DCACHE_USER_WIDTH-1:0] user;
logic [(riscv::XLEN/8)-1:0] dirty; // byte is dirty
logic [(riscv::XLEN/8)-1:0] valid; // byte is valid
@ -67,60 +67,60 @@ module wt_dcache
};
// miss unit <-> read controllers
logic cache_en;
logic cache_en;
// miss unit <-> memory
logic wr_cl_vld;
logic wr_cl_nc;
logic [ DCACHE_SET_ASSOC-1:0] wr_cl_we;
logic [ DCACHE_TAG_WIDTH-1:0] wr_cl_tag;
logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx;
logic [ DCACHE_OFFSET_WIDTH-1:0] wr_cl_off;
logic [ DCACHE_LINE_WIDTH-1:0] wr_cl_data;
logic [DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user;
logic [ DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be;
logic [ DCACHE_SET_ASSOC-1:0] wr_vld_bits;
logic [ DCACHE_SET_ASSOC-1:0] wr_req;
logic wr_ack;
logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_idx;
logic [ DCACHE_OFFSET_WIDTH-1:0] wr_off;
riscv::xlen_t wr_data;
logic [ (riscv::XLEN/8)-1:0] wr_data_be;
logic [ DCACHE_USER_WIDTH-1:0] wr_user;
logic wr_cl_vld;
logic wr_cl_nc;
logic [ DCACHE_SET_ASSOC-1:0] wr_cl_we;
logic [ DCACHE_TAG_WIDTH-1:0] wr_cl_tag;
logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx;
logic [ DCACHE_OFFSET_WIDTH-1:0] wr_cl_off;
logic [ DCACHE_LINE_WIDTH-1:0] wr_cl_data;
logic [DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user;
logic [ DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be;
logic [ DCACHE_SET_ASSOC-1:0] wr_vld_bits;
logic [ DCACHE_SET_ASSOC-1:0] wr_req;
logic wr_ack;
logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_idx;
logic [ DCACHE_OFFSET_WIDTH-1:0] wr_off;
logic [ riscv::XLEN-1:0] wr_data;
logic [ (riscv::XLEN/8)-1:0] wr_data_be;
logic [ DCACHE_USER_WIDTH-1:0] wr_user;
// miss unit <-> controllers/wbuffer
logic [ NumPorts-1:0] miss_req;
logic [ NumPorts-1:0] miss_ack;
logic [ NumPorts-1:0] miss_nc;
logic [ NumPorts-1:0] miss_we;
logic [ NumPorts-1:0][ riscv::XLEN-1:0] miss_wdata;
logic [ NumPorts-1:0][ DCACHE_USER_WIDTH-1:0] miss_wuser;
logic [ NumPorts-1:0][ riscv::PLEN-1:0] miss_paddr;
logic [ NumPorts-1:0][ 2:0] miss_size;
logic [ NumPorts-1:0][ CACHE_ID_WIDTH-1:0] miss_id;
logic [ NumPorts-1:0] miss_replay;
logic [ NumPorts-1:0] miss_rtrn_vld;
logic [ CACHE_ID_WIDTH-1:0] miss_rtrn_id;
logic [ NumPorts-1:0] miss_req;
logic [ NumPorts-1:0] miss_ack;
logic [ NumPorts-1:0] miss_nc;
logic [ NumPorts-1:0] miss_we;
logic [ NumPorts-1:0][ riscv::XLEN-1:0] miss_wdata;
logic [ NumPorts-1:0][ DCACHE_USER_WIDTH-1:0] miss_wuser;
logic [ NumPorts-1:0][ riscv::PLEN-1:0] miss_paddr;
logic [ NumPorts-1:0][ 2:0] miss_size;
logic [ NumPorts-1:0][CVA6Cfg.MEM_TID_WIDTH-1:0] miss_id;
logic [ NumPorts-1:0] miss_replay;
logic [ NumPorts-1:0] miss_rtrn_vld;
logic [ CVA6Cfg.MEM_TID_WIDTH-1:0] miss_rtrn_id;
// memory <-> read controllers/miss unit
logic [ NumPorts-1:0] rd_prio;
logic [ NumPorts-1:0] rd_tag_only;
logic [ NumPorts-1:0] rd_req;
logic [ NumPorts-1:0] rd_ack;
logic [ NumPorts-1:0][ DCACHE_TAG_WIDTH-1:0] rd_tag;
logic [ NumPorts-1:0][DCACHE_CL_IDX_WIDTH-1:0] rd_idx;
logic [ NumPorts-1:0][DCACHE_OFFSET_WIDTH-1:0] rd_off;
riscv::xlen_t rd_data;
logic [ DCACHE_USER_WIDTH-1:0] rd_user;
logic [ DCACHE_SET_ASSOC-1:0] rd_vld_bits;
logic [ DCACHE_SET_ASSOC-1:0] rd_hit_oh;
logic [ NumPorts-1:0] rd_prio;
logic [ NumPorts-1:0] rd_tag_only;
logic [ NumPorts-1:0] rd_req;
logic [ NumPorts-1:0] rd_ack;
logic [ NumPorts-1:0][ DCACHE_TAG_WIDTH-1:0] rd_tag;
logic [ NumPorts-1:0][ DCACHE_CL_IDX_WIDTH-1:0] rd_idx;
logic [ NumPorts-1:0][ DCACHE_OFFSET_WIDTH-1:0] rd_off;
logic [ riscv::XLEN-1:0] rd_data;
logic [ DCACHE_USER_WIDTH-1:0] rd_user;
logic [ DCACHE_SET_ASSOC-1:0] rd_vld_bits;
logic [ DCACHE_SET_ASSOC-1:0] rd_hit_oh;
// miss unit <-> wbuffer
logic [ CVA6Cfg.DCACHE_MAX_TX-1:0][ riscv::PLEN-1:0] tx_paddr;
logic [ CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld;
logic [ CVA6Cfg.DCACHE_MAX_TX-1:0][ riscv::PLEN-1:0] tx_paddr;
logic [ CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld;
// wbuffer <-> memory
wbuffer_t [ DCACHE_WBUF_DEPTH-1:0] wbuffer_data;
wbuffer_t [ DCACHE_WBUF_DEPTH-1:0] wbuffer_data;
///////////////////////////////////////////////////////
@ -240,7 +240,7 @@ module wt_dcache
assign miss_paddr[k] = {{riscv::PLEN} {1'b0}};
assign miss_nc[k] = 1'b0;
assign miss_size[k] = 3'b0;
assign miss_id[k] = {{CACHE_ID_WIDTH} {1'b0}};
assign miss_id[k] = {{CVA6Cfg.MEM_TID_WIDTH} {1'b0}};
assign rd_tag[k] = {{DCACHE_TAG_WIDTH} {1'b0}};
assign rd_idx[k] = {{DCACHE_CL_IDX_WIDTH} {1'b0}};
assign rd_off[k] = {{DCACHE_OFFSET_WIDTH} {1'b0}};

8
core/cache_subsystem/wt_dcache_ctrl.sv
View file

@ -20,7 +20,7 @@ module wt_dcache_ctrl
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1
parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
@ -32,13 +32,13 @@ module wt_dcache_ctrl
output logic miss_req_o,
input logic miss_ack_i,
output logic miss_we_o, // unused (set to 0)
output riscv::xlen_t miss_wdata_o, // unused (set to 0)
output logic [riscv::XLEN-1:0] miss_wdata_o, // unused (set to 0)
output logic [DCACHE_USER_WIDTH-1:0] miss_wuser_o, // unused (set to 0)
output logic [DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, // valid bits at the missed index
output logic [riscv::PLEN-1:0] miss_paddr_o,
output logic miss_nc_o, // request to I/O space
output logic [2:0] miss_size_o, // 00: 1byte, 01: 2byte, 10: 4byte, 11: 8byte, 111: cacheline
output logic [CACHE_ID_WIDTH-1:0] miss_id_o, // set to constant ID
output logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_id_o, // set to constant ID
input logic miss_replay_i, // request collided with pending miss - have to replay the request
input logic miss_rtrn_vld_i, // signals that the miss has been served, asserted in the same cycle as when the data returns from memory
// used to detect readout mux collisions
@ -50,7 +50,7 @@ module wt_dcache_ctrl
output logic rd_req_o, // read the word at offset off_i[:3] in all ways
output logic rd_tag_only_o, // set to zero here
input logic rd_ack_i,
input riscv::xlen_t rd_data_i,
input logic [riscv::XLEN-1:0] rd_data_i,
input logic [DCACHE_USER_WIDTH-1:0] rd_user_i,
input logic [DCACHE_SET_ASSOC-1:0] rd_vld_bits_i,
input logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh_i

9
core/cache_subsystem/wt_dcache_mem.sv
View file

@ -47,7 +47,7 @@ module wt_dcache_mem
output logic [NumPorts-1:0] rd_ack_o,
output logic [DCACHE_SET_ASSOC-1:0] rd_vld_bits_o,
output logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh_o,
output riscv::xlen_t rd_data_o,
output logic [riscv::XLEN-1:0] rd_data_o,
output logic [DCACHE_USER_WIDTH-1:0] rd_user_o,
// only available on port 0, uses address signals of port 0
@ -67,7 +67,7 @@ module wt_dcache_mem
output logic wr_ack_o,
input logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx_i,
input logic [DCACHE_OFFSET_WIDTH-1:0] wr_off_i,
input riscv::xlen_t wr_data_i,
input logic [riscv::XLEN-1:0] wr_data_i,
input logic [DCACHE_USER_WIDTH-1:0] wr_user_i,
input logic [(riscv::XLEN/8)-1:0] wr_data_be_i,
@ -75,6 +75,9 @@ module wt_dcache_mem
input wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_data_i
);
localparam DCACHE_NUM_BANKS = ariane_pkg::DCACHE_LINE_WIDTH / riscv::XLEN;
localparam DCACHE_NUM_BANKS_WIDTH = $clog2(DCACHE_NUM_BANKS);
// functions
function automatic logic [DCACHE_NUM_BANKS-1:0] dcache_cl_bin2oh(
input logic [DCACHE_NUM_BANKS_WIDTH-1:0] in);
@ -117,7 +120,7 @@ module wt_dcache_mem
logic [DCACHE_WBUF_DEPTH-1:0] wbuffer_hit_oh;
logic [ (riscv::XLEN/8)-1:0] wbuffer_be;
riscv::xlen_t wbuffer_rdata, rdata;
logic [riscv::XLEN-1:0] wbuffer_rdata, rdata;
logic [DCACHE_USER_WIDTH-1:0] wbuffer_ruser, ruser;
logic [riscv::PLEN-1:0] wbuffer_cmp_addr;

12
core/cache_subsystem/wt_dcache_missunit.sv
View file

@ -21,7 +21,7 @@ module wt_dcache_missunit
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_t = logic,
parameter type dcache_rtrn_t = logic,
parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs
parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs
parameter int unsigned NumPorts = 4 // number of miss ports
) (
input logic clk_i, // Clock
@ -47,12 +47,12 @@ module wt_dcache_missunit
input logic [NumPorts-1:0][riscv::PLEN-1:0] miss_paddr_i,
input logic [NumPorts-1:0][DCACHE_SET_ASSOC-1:0] miss_vld_bits_i,
input logic [NumPorts-1:0][2:0] miss_size_i,
input logic [NumPorts-1:0][CACHE_ID_WIDTH-1:0] miss_id_i, // used as transaction ID
input logic [NumPorts-1:0][CVA6Cfg.MEM_TID_WIDTH-1:0] miss_id_i, // used as transaction ID
// signals that the request collided with a pending read
output logic [NumPorts-1:0] miss_replay_o,
// signals response from memory
output logic [NumPorts-1:0] miss_rtrn_vld_o,
output logic [CACHE_ID_WIDTH-1:0] miss_rtrn_id_o, // only used for writes, set to zero fro reads
output logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_rtrn_id_o, // only used for writes, set to zero fro reads
// from writebuffer
input logic [CVA6Cfg.DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_i, // used to check for address collisions with read operations
input logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_i, // used to check for address collisions with read operations
@ -121,7 +121,7 @@ module wt_dcache_missunit
logic [riscv::PLEN-1:0] paddr;
logic [2:0] size;
logic [DCACHE_SET_ASSOC-1:0] vld_bits;
logic [CACHE_ID_WIDTH-1:0] id;
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] id;
logic nc;
logic [$clog2(DCACHE_SET_ASSOC)-1:0] repl_way;
logic [$clog2(NumPorts)-1:0] miss_port_idx;
@ -140,8 +140,8 @@ module wt_dcache_missunit
logic amo_sel, miss_is_write;
logic amo_req_d, amo_req_q;
logic [63:0] amo_rtrn_mux;
riscv::xlen_t amo_data, amo_data_a, amo_data_b;
riscv::xlen_t amo_user; //DCACHE USER ? DATA_USER_WIDTH
logic [riscv::XLEN-1:0] amo_data, amo_data_a, amo_data_b;
logic [riscv::XLEN-1:0] amo_user; //DCACHE USER ? DATA_USER_WIDTH
logic [riscv::PLEN-1:0] tmp_paddr;
logic [$clog2(NumPorts)-1:0] miss_port_idx;
logic [DCACHE_CL_IDX_WIDTH-1:0] cnt_d, cnt_q;

63
core/cache_subsystem/wt_dcache_wbuffer.sv
View file

@ -72,15 +72,15 @@ module wt_dcache_wbuffer
output logic [riscv::PLEN-1:0] miss_paddr_o,
output logic miss_req_o,
output logic miss_we_o, // always 1 here
output riscv::xlen_t miss_wdata_o,
output logic [riscv::XLEN-1:0] miss_wdata_o,
output logic [DCACHE_USER_WIDTH-1:0] miss_wuser_o,
output logic [DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, // unused here (set to 0)
output logic miss_nc_o, // request to I/O space
output logic [2:0] miss_size_o, //
output logic [CACHE_ID_WIDTH-1:0] miss_id_o, // ID of this transaction (wbuffer uses all IDs from 0 to DCACHE_MAX_TX-1)
output logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_id_o, // ID of this transaction (wbuffer uses all IDs from 0 to DCACHE_MAX_TX-1)
// write responses from memory
input logic miss_rtrn_vld_i,
input logic [CACHE_ID_WIDTH-1:0] miss_rtrn_id_i, // transaction ID to clear
input logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_rtrn_id_i, // transaction ID to clear
// cache read interface
output logic [DCACHE_TAG_WIDTH-1:0] rd_tag_o, // tag in - comes one cycle later
output logic [DCACHE_CL_IDX_WIDTH-1:0] rd_idx_o,
@ -88,7 +88,7 @@ module wt_dcache_wbuffer
output logic rd_req_o, // read the word at offset off_i[:3] in all ways
output logic rd_tag_only_o, // set to 1 here as we do not have to read the data arrays
input logic rd_ack_i,
input riscv::xlen_t rd_data_i, // unused
input logic [riscv::XLEN-1:0] rd_data_i, // unused
input logic [DCACHE_SET_ASSOC-1:0] rd_vld_bits_i, // unused
input logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh_i,
// cacheline writes
@ -99,7 +99,7 @@ module wt_dcache_wbuffer
input logic wr_ack_i,
output logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx_o,
output logic [DCACHE_OFFSET_WIDTH-1:0] wr_off_o,
output riscv::xlen_t wr_data_o,
output logic [riscv::XLEN-1:0] wr_data_o,
output logic [(riscv::XLEN/8)-1:0] wr_data_be_o,
output logic [DCACHE_USER_WIDTH-1:0] wr_user_o,
// to forwarding logic and miss unit
@ -108,6 +108,57 @@ module wt_dcache_wbuffer
output logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_o
);
function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable8(
input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
logic [(riscv::XLEN/8)-1:0] be;
be = '0;
unique case (size)
2'b00: be[offset] = '1; // byte
2'b01: be[offset+:2] = '1; // hword
2'b10: be[offset+:4] = '1; // word
default: be = '1; // dword
endcase // size
return be;
endfunction : to_byte_enable8
function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable4(
input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
logic [3:0] be;
be = '0;
unique case (size)
2'b00: be[offset] = '1; // byte
2'b01: be[offset+:2] = '1; // hword
default: be = '1; // word
endcase // size
return be;
endfunction : to_byte_enable4
// openpiton requires the data to be replicated in case of smaller sizes than dwords
function automatic logic [riscv::XLEN-1:0] repData64(
input logic [riscv::XLEN-1:0] data, input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset,
input logic [1:0] size);
logic [riscv::XLEN-1:0] out;
unique case (size)
2'b00: for (int k = 0; k < 8; k++) out[k*8+:8] = data[offset*8+:8]; // byte
2'b01: for (int k = 0; k < 4; k++) out[k*16+:16] = data[offset*8+:16]; // hword
2'b10: for (int k = 0; k < 2; k++) out[k*32+:32] = data[offset*8+:32]; // word
default: out = data; // dword
endcase // size
return out;
endfunction : repData64
function automatic logic [riscv::XLEN-1:0] repData32(
input logic [riscv::XLEN-1:0] data, input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset,
input logic [1:0] size);
logic [riscv::XLEN-1:0] out;
unique case (size)
2'b00: for (int k = 0; k < 4; k++) out[k*8+:8] = data[offset*8+:8]; // byte
2'b01: for (int k = 0; k < 2; k++) out[k*16+:16] = data[offset*8+:16]; // hword
default: out = data; // word
endcase // size
return out;
endfunction : repData32
typedef struct packed {
logic vld;
logic [(riscv::XLEN/8)-1:0] be;
@ -125,7 +176,7 @@ module wt_dcache_wbuffer
logic [$clog2(DCACHE_WBUF_DEPTH)-1:0]
next_ptr, dirty_ptr, hit_ptr, wr_ptr, check_ptr_d, check_ptr_q, check_ptr_q1, rtrn_ptr;
logic [CACHE_ID_WIDTH-1:0] tx_id, rtrn_id;
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tx_id, rtrn_id;
logic [riscv::XLEN_ALIGN_BYTES-1:0] bdirty_off;
logic [(riscv::XLEN/8)-1:0] tx_be;

6
core/cache_subsystem/wt_l15_adapter.sv
View file

@ -89,7 +89,7 @@ module wt_l15_adapter
wt_cache_pkg::l15_reqtypes_t l15_rqtype; // see below for encoding
logic l15_nc; // non-cacheable bit
logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
logic [wt_cache_pkg::L15_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1
logic l15_prefetch; // unused in openpiton
logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment
logic l15_blockstore; // unused in openpiton
@ -110,7 +110,7 @@ module wt_l15_adapter
logic [1:0] l15_error; // unused in openpiton
logic l15_noncacheable; // non-cacheable bit
logic l15_atomic; // asserted in load return and store ack packets of atomic tx
logic [wt_cache_pkg::L15_TID_WIDTH-1:0] l15_threadid; // used as transaction ID
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_threadid; // used as transaction ID
logic l15_prefetch; // unused in openpiton
logic l15_f4b; // 4byte instruction fill from I/O space (nc).
logic [63:0] l15_data_0; // used for both caches
@ -151,7 +151,7 @@ module wt_l15_adapter
// l15_req_t l15_req_o.l15_rqtype; // see below for encoding
// logic l15_req_o.l15_nc; // non-cacheable bit
// logic [2:0] l15_req_o.l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
// logic [L15_TID_WIDTH-1:0] l15_req_o.l15_threadid; // currently 0 or 1
// logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_req_o.l15_threadid; // currently 0 or 1
// logic l15_req_o.l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment
// logic [L15_WAY_WIDTH-1:0] l15_req_o.l15_l1rplway; // way to replace
// logic [39:0] l15_req_o.l15_address; // physical address

4
core/commit_stage.sv
View file

@ -55,9 +55,9 @@ module commit_stage
// Decoded CSR operation - CSR_REGFILE
output fu_op csr_op_o,
// Data to write to CSR - CSR_REGFILE
output riscv::xlen_t csr_wdata_o,
output logic [riscv::XLEN-1:0] csr_wdata_o,
// Data to read from CSR - CSR_REGFILE
input riscv::xlen_t csr_rdata_i,
input logic [riscv::XLEN-1:0] csr_rdata_i,
// Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE
input exception_t csr_exception_i,
// Write the fflags CSR - CSR_REGFILE

2
core/csr_buffer.sv
View file

@ -33,7 +33,7 @@ module csr_buffer
// CSR instruction is valid - ISSUE_STAGE
input logic csr_valid_i,
// CSR buffer result - ISSUE_STAGE
output riscv::xlen_t csr_result_o,
output logic [riscv::XLEN-1:0] csr_result_o,
// commit the pending CSR OP - TO_BE_COMPLETED
input logic csr_commit_i,
// CSR address to write - COMMIT_STAGE

56
core/csr_regfile.sv
View file

@ -153,7 +153,7 @@ module csr_regfile
// internal signal to keep track of access exceptions
logic read_access_exception, update_access_exception, privilege_violation;
logic csr_we, csr_read;
riscv::xlen_t csr_wdata, csr_rdata;
logic [riscv::XLEN-1:0] csr_wdata, csr_rdata;
riscv::priv_lvl_t trap_to_priv_lvl;
// register for enabling load store address translation, this is critical, hence the register
logic en_ld_st_translation_d, en_ld_st_translation_q;
@ -164,7 +164,7 @@ module csr_regfile
// CSR write causes us to mark the FPU state as dirty
logic dirty_fp_state_csr;
riscv::mstatus_rv_t mstatus_q, mstatus_d;
riscv::xlen_t mstatus_extended;
logic [riscv::XLEN-1:0] mstatus_extended;
satp_t satp_q, satp_d;
riscv::dcsr_t dcsr_q, dcsr_d;
riscv::csr_t csr_addr;
@ -174,30 +174,30 @@ module csr_regfile
logic debug_mode_q, debug_mode_d;
logic mtvec_rst_load_q; // used to determine whether we came out of reset
riscv::xlen_t dpc_q, dpc_d;
riscv::xlen_t dscratch0_q, dscratch0_d;
riscv::xlen_t dscratch1_q, dscratch1_d;
riscv::xlen_t mtvec_q, mtvec_d;
riscv::xlen_t medeleg_q, medeleg_d;
riscv::xlen_t mideleg_q, mideleg_d;
riscv::xlen_t mip_q, mip_d;
riscv::xlen_t mie_q, mie_d;
riscv::xlen_t mcounteren_q, mcounteren_d;
riscv::xlen_t mscratch_q, mscratch_d;
riscv::xlen_t mepc_q, mepc_d;
riscv::xlen_t mcause_q, mcause_d;
riscv::xlen_t mtval_q, mtval_d;
logic [riscv::XLEN-1:0] dpc_q, dpc_d;
logic [riscv::XLEN-1:0] dscratch0_q, dscratch0_d;
logic [riscv::XLEN-1:0] dscratch1_q, dscratch1_d;
logic [riscv::XLEN-1:0] mtvec_q, mtvec_d;
logic [riscv::XLEN-1:0] medeleg_q, medeleg_d;
logic [riscv::XLEN-1:0] mideleg_q, mideleg_d;
logic [riscv::XLEN-1:0] mip_q, mip_d;
logic [riscv::XLEN-1:0] mie_q, mie_d;
logic [riscv::XLEN-1:0] mcounteren_q, mcounteren_d;
logic [riscv::XLEN-1:0] mscratch_q, mscratch_d;
logic [riscv::XLEN-1:0] mepc_q, mepc_d;
logic [riscv::XLEN-1:0] mcause_q, mcause_d;
logic [riscv::XLEN-1:0] mtval_q, mtval_d;
logic fiom_d, fiom_q;
riscv::xlen_t stvec_q, stvec_d;
riscv::xlen_t scounteren_q, scounteren_d;
riscv::xlen_t sscratch_q, sscratch_d;
riscv::xlen_t sepc_q, sepc_d;
riscv::xlen_t scause_q, scause_d;
riscv::xlen_t stval_q, stval_d;
riscv::xlen_t dcache_q, dcache_d;
riscv::xlen_t icache_q, icache_d;
riscv::xlen_t acc_cons_q, acc_cons_d;
logic [riscv::XLEN-1:0] stvec_q, stvec_d;
logic [riscv::XLEN-1:0] scounteren_q, scounteren_d;
logic [riscv::XLEN-1:0] sscratch_q, sscratch_d;
logic [riscv::XLEN-1:0] sepc_q, sepc_d;
logic [riscv::XLEN-1:0] scause_q, scause_d;
logic [riscv::XLEN-1:0] stval_q, stval_d;
logic [riscv::XLEN-1:0] dcache_q, dcache_d;
logic [riscv::XLEN-1:0] icache_q, icache_d;
logic [riscv::XLEN-1:0] acc_cons_q, acc_cons_d;
logic wfi_d, wfi_q;
@ -209,7 +209,7 @@ module csr_regfile
logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q;
logic [3:0] index;
localparam riscv::xlen_t IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
localparam logic [riscv::XLEN-1:0] IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
| (riscv::XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
| (riscv::XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
| (riscv::XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension
@ -366,8 +366,8 @@ module csr_regfile
if (CVA6Cfg.RVU && riscv::XLEN == 32) csr_rdata = '0;
else read_access_exception = 1'b1;
end
riscv::CSR_MVENDORID: csr_rdata = OPENHWGROUP_MVENDORID;
riscv::CSR_MARCHID: csr_rdata = ARIANE_MARCHID;
riscv::CSR_MVENDORID: csr_rdata = {{riscv::XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID};
riscv::CSR_MARCHID: csr_rdata = {{riscv::XLEN - 32{1'b0}}, ARIANE_MARCHID};
riscv::CSR_MIMPID: csr_rdata = '0; // not implemented
riscv::CSR_MHARTID: csr_rdata = hart_id_i;
riscv::CSR_MCONFIGPTR: csr_rdata = '0; // not implemented
@ -604,7 +604,7 @@ module csr_regfile
// ---------------------------
// CSR Write and update logic
// ---------------------------
riscv::xlen_t mask;
logic [riscv::XLEN-1:0] mask;
always_comb begin : csr_update
automatic satp_t satp;
automatic logic [63:0] instret;

30
core/cva6.sv
View file

@ -93,10 +93,10 @@ module cva6
logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1
logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2
logic [REG_ADDR_SIZE-1:0] rd; // register destination address
riscv::xlen_t result; // for unfinished instructions this field also holds the immediate,
// for unfinished floating-point that are partly encoded in rs2, this field also holds rs2
// for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB)
// this field holds the address of the third operand from the floating-point register file
logic [riscv::XLEN-1:0] result; // for unfinished instructions this field also holds the immediate,
// for unfinished floating-point that are partly encoded in rs2, this field also holds rs2
// for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB)
// this field holds the address of the third operand from the floating-point register file
logic valid; // is the result valid
logic use_imm; // should we use the immediate as operand b?
logic use_zimm; // use zimm as operand a
@ -158,7 +158,7 @@ module cva6
logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] way; // way to replace
logic [riscv::PLEN-1:0] paddr; // physical address
logic nc; // noncacheable
logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
},
localparam type icache_rtrn_t = struct packed {
wt_cache_pkg::icache_in_t rtype; // see definitions above
@ -170,7 +170,7 @@ module cva6
logic [ariane_pkg::ICACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate
logic [wt_cache_pkg::L1I_WAY_WIDTH-1:0] way; // way to invalidate
} inv; // invalidation vector
logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
},
// D$ data requests
@ -345,7 +345,7 @@ module cva6
logic flu_ready_ex_id;
logic [TRANS_ID_BITS-1:0] flu_trans_id_ex_id;
logic flu_valid_ex_id;
riscv::xlen_t flu_result_ex_id;
logic [riscv::XLEN-1:0] flu_result_ex_id;
exception_t flu_exception_ex_id;
// ALU
logic alu_valid_id_ex;
@ -359,11 +359,11 @@ module cva6
logic lsu_ready_ex_id;
logic [TRANS_ID_BITS-1:0] load_trans_id_ex_id;
riscv::xlen_t load_result_ex_id;
logic [riscv::XLEN-1:0] load_result_ex_id;
logic load_valid_ex_id;
exception_t load_exception_ex_id;
riscv::xlen_t store_result_ex_id;
logic [riscv::XLEN-1:0] store_result_ex_id;
logic [TRANS_ID_BITS-1:0] store_trans_id_ex_id;
logic store_valid_ex_id;
exception_t store_exception_ex_id;
@ -375,7 +375,7 @@ module cva6
logic [1:0] fpu_fmt_id_ex;
logic [2:0] fpu_rm_id_ex;
logic [TRANS_ID_BITS-1:0] fpu_trans_id_ex_id;
riscv::xlen_t fpu_result_ex_id;
logic [riscv::XLEN-1:0] fpu_result_ex_id;
logic fpu_valid_ex_id;
exception_t fpu_exception_ex_id;
// Accelerator
@ -383,7 +383,7 @@ module cva6
scoreboard_entry_t issue_instr_id_acc;
logic issue_instr_hs_id_acc;
logic [TRANS_ID_BITS-1:0] acc_trans_id_ex_id;
riscv::xlen_t acc_result_ex_id;
logic [riscv::XLEN-1:0] acc_result_ex_id;
logic acc_valid_ex_id;
exception_t acc_exception_ex_id;
logic halt_acc_ctrl;
@ -394,7 +394,7 @@ module cva6
logic csr_valid_id_ex;
// CVXIF
logic [TRANS_ID_BITS-1:0] x_trans_id_ex_id;
riscv::xlen_t x_result_ex_id;
logic [riscv::XLEN-1:0] x_result_ex_id;
logic x_valid_ex_id;
exception_t x_exception_ex_id;
logic x_we_ex_id;
@ -451,8 +451,8 @@ module cva6
logic [ASID_WIDTH-1:0] asid_csr_ex;
logic [11:0] csr_addr_ex_csr;
fu_op csr_op_commit_csr;
riscv::xlen_t csr_wdata_commit_csr;
riscv::xlen_t csr_rdata_csr_commit;
logic [riscv::XLEN-1:0] csr_wdata_commit_csr;
logic [riscv::XLEN-1:0] csr_rdata_csr_commit;
exception_t csr_exception_csr_commit;
logic tvm_csr_id;
logic tw_csr_id;
@ -471,7 +471,7 @@ module cva6
// Performance Counters <-> *
// ----------------------------
logic [11:0] addr_csr_perf;
riscv::xlen_t data_csr_perf, data_perf_csr;
logic [riscv::XLEN-1:0] data_csr_perf, data_perf_csr;
logic we_csr_perf;
logic icache_flush_ctrl_cache;

18
core/cva6_rvfi.sv
View file

@ -39,7 +39,7 @@ module cva6_rvfi
localparam bit RVD = (riscv::IS_XLEN64 ? 1 : 0) & CVA6Cfg.FpuEn;
localparam bit FpPresent = RVF | RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8;
localparam riscv::xlen_t IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
localparam logic [riscv::XLEN-1:0] IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
| (riscv::XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
| (riscv::XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
| (riscv::XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension
@ -53,7 +53,7 @@ module cva6_rvfi
| (riscv::XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present
| ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN - 2); // MXL
localparam riscv::xlen_t hart_id_i = '0;
localparam logic [riscv::XLEN-1:0] hart_id_i = '0;
logic flush;
logic issue_instr_ack;
logic fetch_entry_valid;
@ -67,18 +67,18 @@ module cva6_rvfi
logic decoded_instr_valid;
logic decoded_instr_ack;
riscv::xlen_t rs1_forwarding;
riscv::xlen_t rs2_forwarding;
logic [riscv::XLEN-1:0] rs1_forwarding;
logic [riscv::XLEN-1:0] rs2_forwarding;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_pc;
fu_op [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_instr_op;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs1;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs2;
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rd;
riscv::xlen_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_result;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] commit_instr_result;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_valid;
riscv::xlen_t ex_commit_cause;
logic [riscv::XLEN-1:0] ex_commit_cause;
logic ex_commit_valid;
riscv::priv_lvl_t priv_lvl;
@ -193,12 +193,12 @@ module cva6_rvfi
// this is the FIFO struct of the issue queue
typedef struct packed {
riscv::xlen_t rs1_rdata;
riscv::xlen_t rs2_rdata;
logic [riscv::XLEN-1:0] rs1_rdata;
logic [riscv::XLEN-1:0] rs2_rdata;
logic [riscv::VLEN-1:0] lsu_addr;
logic [(riscv::XLEN/8)-1:0] lsu_rmask;
logic [(riscv::XLEN/8)-1:0] lsu_wmask;
riscv::xlen_t lsu_wdata;
logic [riscv::XLEN-1:0] lsu_wdata;
logic [31:0] instr;
} sb_mem_t;
sb_mem_t [NR_SB_ENTRIES-1:0] mem_q, mem_n;

4
core/cva6_rvfi_probes.sv
View file

@ -35,8 +35,8 @@ module cva6_rvfi_probes
input logic decoded_instr_valid_i,
input logic decoded_instr_ack_i,
input riscv::xlen_t rs1_forwarding_i,
input riscv::xlen_t rs2_forwarding_i,
input logic [riscv::XLEN-1:0] rs1_forwarding_i,
input logic [riscv::XLEN-1:0] rs2_forwarding_i,
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
input exception_t ex_commit_i,

2
core/cvxif_fu.sv
View file

@ -36,7 +36,7 @@ module cvxif_fu
// CVXIF exception - ISSUE_STAGE
output exception_t x_exception_o,
// CVXIF FU result - ISSUE_STAGE
output riscv::xlen_t x_result_o,
output logic [ riscv::XLEN-1:0] x_result_o,
// CVXIF result valid - ISSUE_STAGE
output logic x_valid_o,
// CVXIF write enable - ISSUE_STAGE

32
core/decoder.sv
View file

@ -92,22 +92,30 @@ module decoder
// --------------------
// Immediate select
// --------------------
enum logic [3:0] {NOIMM, IIMM, SIMM, SBIMM, UIMM, JIMM, RS3} imm_select;
enum logic [3:0] {
NOIMM,
IIMM,
SIMM,
SBIMM,
UIMM,
JIMM,
RS3
} imm_select;
riscv::xlen_t imm_i_type;
riscv::xlen_t imm_s_type;
riscv::xlen_t imm_sb_type;
riscv::xlen_t imm_u_type;
riscv::xlen_t imm_uj_type;
riscv::xlen_t imm_bi_type;
logic [riscv::XLEN-1:0] imm_i_type;
logic [riscv::XLEN-1:0] imm_s_type;
logic [riscv::XLEN-1:0] imm_sb_type;
logic [riscv::XLEN-1:0] imm_u_type;
logic [riscv::XLEN-1:0] imm_uj_type;
logic [riscv::XLEN-1:0] imm_bi_type;
// ---------------------------------------
// Accelerator instructions' first-pass decoder
// ---------------------------------------
logic is_accel;
scoreboard_entry_t acc_instruction;
logic acc_illegal_instr;
logic acc_is_control_flow_instr;
logic is_accel;
scoreboard_entry_t acc_instruction;
logic acc_illegal_instr;
logic acc_is_control_flow_instr;
if (CVA6Cfg.EnableAccelerator) begin : gen_accel_decoder
// This module is responsible for a light-weight decoding of accelerator instructions,
@ -1335,7 +1343,7 @@ module decoder
// ---------------------
// Exception handling
// ---------------------
riscv::xlen_t interrupt_cause;
logic [riscv::XLEN-1:0] interrupt_cause;
// this instruction has already executed if the exception is valid
assign instruction_o.valid = instruction_o.ex.valid;

12
core/ex_stage.sv
View file

@ -50,7 +50,7 @@ module ex_stage
// Report whether isntruction is compressed - ISSUE_STAGE
input logic is_compressed_instr_i,
// Fixed Latency Unit result - ISSUE_STAGE
output riscv::xlen_t flu_result_o,
output logic [riscv::XLEN-1:0] flu_result_o,
// ID of the scoreboard entry at which a=to write back - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] flu_trans_id_o,
// Fixed Latency Unit exception - ISSUE_STAGE
@ -84,7 +84,7 @@ module ex_stage
// Load result is valid - ISSUE_STAGE
output logic load_valid_o,
// Load result valid - ISSUE_STAGE
output riscv::xlen_t load_result_o,
output logic [riscv::XLEN-1:0] load_result_o,
// Load instruction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] load_trans_id_o,
// Exception generated by load instruction - ISSUE_STAGE
@ -92,7 +92,7 @@ module ex_stage
// Store result is valid - ISSUe_STAGE
output logic store_valid_o,
// Store result - ISSUE_STAGE
output riscv::xlen_t store_result_o,
output logic [riscv::XLEN-1:0] store_result_o,
// Store instruction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] store_trans_id_o,
// Exception generated by store instruction - ISSUE_STAGE
@ -124,7 +124,7 @@ module ex_stage
// FPU transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] fpu_trans_id_o,
// FPU result - ISSUE_STAGE
output riscv::xlen_t fpu_result_o,
output logic [riscv::XLEN-1:0] fpu_result_o,
// FPU valid - ISSUE_STAGE
output logic fpu_valid_o,
// FPU exception - ISSUE_STAGE
@ -140,7 +140,7 @@ module ex_stage
// CVXIF exception - ISSUE_STAGE
output exception_t x_exception_o,
// CVXIF result - ISSUE_STAGE
output riscv::xlen_t x_result_o,
output logic [riscv::XLEN-1:0] x_result_o,
// CVXIF result valid - ISSUE_STAGE
output logic x_valid_o,
// CVXIF write enable - ISSUE_STAGE
@ -228,7 +228,7 @@ module ex_stage
// from ALU to branch unit
logic alu_branch_res; // branch comparison result
riscv::xlen_t alu_result, csr_result, mult_result;
logic [riscv::XLEN-1:0] alu_result, csr_result, mult_result;
logic [riscv::VLEN-1:0] branch_result;
logic csr_ready, mult_ready;
logic [TRANS_ID_BITS-1:0] mult_trans_id;

28
core/frontend/instr_scan.sv
View file

@ -47,6 +47,28 @@ module instr_scan #(
// Instruction compressed immediat - FRONTEND
output logic [riscv::VLEN-1:0] rvc_imm_o
);
function automatic logic [riscv::VLEN-1:0] uj_imm(logic [31:0] instruction_i);
return {
{44 + riscv::VLEN - 64{instruction_i[31]}},
instruction_i[19:12],
instruction_i[20],
instruction_i[30:21],
1'b0
};
endfunction
function automatic logic [riscv::VLEN-1:0] sb_imm(logic [31:0] instruction_i);
return {
{51 + riscv::VLEN - 64{instruction_i[31]}},
instruction_i[31],
instruction_i[7],
instruction_i[30:25],
instruction_i[11:8],
1'b0
};
endfunction
logic is_rvc;
assign is_rvc = (instr_i[1:0] != 2'b11);
@ -62,11 +84,7 @@ module instr_scan #(
// Opocde is JAL[R] and destination register is either x1 or x5
assign rvi_call_o = (rvi_jalr_o | rvi_jump_o) & ((instr_i[11:7] == 5'd1) | instr_i[11:7] == 5'd5);
// differentiates between JAL and BRANCH opcode, JALR comes from BHT
assign rvi_imm_o = is_xret ? '0 : (instr_i[3]) ? ariane_pkg::uj_imm(
instr_i
) : ariane_pkg::sb_imm(
instr_i
);
assign rvi_imm_o = is_xret ? '0 : (instr_i[3]) ? uj_imm(instr_i) : sb_imm(instr_i);
assign rvi_branch_o = (instr_i[6:0] == riscv::OpcodeBranch);
assign rvi_jalr_o = (instr_i[6:0] == riscv::OpcodeJalr);
assign rvi_jump_o = logic'(instr_i[6:0] == riscv::OpcodeJal) | is_xret;

58
core/include/ariane_pkg.sv
View file

@ -65,8 +65,8 @@ package ariane_pkg;
localparam int unsigned LAT_NONCOMP = 'd1;
localparam int unsigned LAT_CONV = 'd2;
localparam riscv::xlen_t OPENHWGROUP_MVENDORID = {{riscv::XLEN - 32{1'b0}}, 32'h0602};
localparam riscv::xlen_t ARIANE_MARCHID = {{riscv::XLEN - 32{1'b0}}, 32'd3};
localparam logic [31:0] OPENHWGROUP_MVENDORID = 32'h0602;
localparam logic [31:0] ARIANE_MARCHID = 32'd3;
// 32 registers
localparam REG_ADDR_SIZE = 5;
@ -274,8 +274,6 @@ package ariane_pkg;
localparam int unsigned DCACHE_LINE_WIDTH = cva6_config_pkg::CVA6ConfigDcacheLineWidth; // in bit
localparam int unsigned DCACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : cva6_config_pkg::CVA6ConfigDcacheLineWidth; // in bit
localparam int unsigned DCACHE_USER_WIDTH = DATA_USER_WIDTH;
localparam int unsigned MEM_TID_WIDTH = cva6_config_pkg::CVA6ConfigMemTidWidth;
`endif
localparam int unsigned DCACHE_TID_WIDTH = cva6_config_pkg::CVA6ConfigDcacheIdWidth;
@ -651,62 +649,14 @@ package ariane_pkg;
// ----------------------
// Arithmetic Functions
// ----------------------
function automatic riscv::xlen_t sext32(logic [31:0] operand);
function automatic logic [riscv::XLEN-1:0] sext32(config_pkg::cva6_cfg_t Cfg,
logic [31:0] operand);
return {{riscv::XLEN - 32{operand[31]}}, operand[31:0]};
endfunction
// ----------------------
// Immediate functions
// ----------------------
function automatic logic [riscv::VLEN-1:0] uj_imm(logic [31:0] instruction_i);
return {
{44 + riscv::VLEN - 64{instruction_i[31]}},
instruction_i[19:12],
instruction_i[20],
instruction_i[30:21],
1'b0
};
endfunction
function automatic logic [riscv::VLEN-1:0] i_imm(logic [31:0] instruction_i);
return {{52 + riscv::VLEN - 64{instruction_i[31]}}, instruction_i[31:20]};
endfunction
function automatic logic [riscv::VLEN-1:0] sb_imm(logic [31:0] instruction_i);
return {
{51 + riscv::VLEN - 64{instruction_i[31]}},
instruction_i[31],
instruction_i[7],
instruction_i[30:25],
instruction_i[11:8],
1'b0
};
endfunction
// ----------------------
// LSU Functions
// ----------------------
// align data to address e.g.: shift data to be naturally 64
function automatic riscv::xlen_t data_align(logic [2:0] addr, logic [63:0] data);
// Set addr[2] to 1'b0 when 32bits
logic [ 2:0] addr_tmp = {(addr[2] && riscv::IS_XLEN64), addr[1:0]};
logic [63:0] data_tmp = {64{1'b0}};
case (addr_tmp)
3'b000: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-1:0]};
3'b001:
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-9:0], data[riscv::XLEN-1:riscv::XLEN-8]};
3'b010:
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-17:0], data[riscv::XLEN-1:riscv::XLEN-16]};
3'b011:
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-25:0], data[riscv::XLEN-1:riscv::XLEN-24]};
3'b100: data_tmp = {data[31:0], data[63:32]};
3'b101: data_tmp = {data[23:0], data[63:24]};
3'b110: data_tmp = {data[15:0], data[63:16]};
3'b111: data_tmp = {data[7:0], data[63:8]};
endcase
return data_tmp[riscv::XLEN-1:0];
endfunction
// generate byte enable mask
function automatic logic [7:0] be_gen(logic [2:0] addr, logic [1:0] size);
case (size)

3
core/include/riscv_pkg.sv
View file

@ -21,7 +21,6 @@ package riscv;
// Import cva6 config from cva6_config_pkg
// ----------------------
localparam XLEN = cva6_config_pkg::CVA6ConfigXlen;
localparam FPU_EN = cva6_config_pkg::CVA6ConfigFpuEn;
// ----------------------
// Data and Address length
@ -50,8 +49,6 @@ package riscv;
localparam VPN2 = (VLEN - 31 < 8) ? VLEN - 31 : 8;
localparam XLEN_ALIGN_BYTES = $clog2(XLEN / 8);
typedef logic [XLEN-1:0] xlen_t;
// --------------------
// Privilege Spec
// --------------------

64
core/include/rvfi_types.svh
View file

@ -29,10 +29,10 @@
}
`define RVFI_CSR_ELMT_T(Cfg) struct packed { \
riscv::xlen_t rdata; \
riscv::xlen_t rmask; \
riscv::xlen_t wdata; \
riscv::xlen_t wmask; \
logic [riscv::XLEN-1:0] rdata; \
logic [riscv::XLEN-1:0] rmask; \
logic [riscv::XLEN-1:0] wdata; \
logic [riscv::XLEN-1:0] wmask; \
}
`define RVFI_CSR_T(Cfg, rvfi_csr_elmt_t) struct packed { \
@ -103,16 +103,16 @@
logic fetch_entry_valid; \
logic [31:0] instruction; \
logic is_compressed; \
riscv::xlen_t rs1_forwarding; \
riscv::xlen_t rs2_forwarding; \
logic [riscv::XLEN-1:0] rs1_forwarding; \
logic [riscv::XLEN-1:0] rs2_forwarding; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_pc; \
ariane_pkg::fu_op [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] commit_instr_op; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs1; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs2; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rd; \
riscv::xlen_t [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_instr_result; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::XLEN-1:0] commit_instr_result; \
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_valid; \
riscv::xlen_t ex_commit_cause; \
logic [riscv::XLEN-1:0] ex_commit_cause; \
logic ex_commit_valid; \
riscv::priv_lvl_t priv_lvl; \
logic [riscv::VLEN-1:0] lsu_ctrl_vaddr; \
@ -129,34 +129,34 @@
`define RVFI_PROBES_CSR_T(Cfg) struct packed { \
riscv::fcsr_t fcsr_q; \
riscv::dcsr_t dcsr_q; \
riscv::xlen_t dpc_q; \
riscv::xlen_t dscratch0_q; \
riscv::xlen_t dscratch1_q; \
riscv::xlen_t mie_q; \
riscv::xlen_t mip_q; \
riscv::xlen_t stvec_q; \
riscv::xlen_t scounteren_q; \
riscv::xlen_t sscratch_q; \
riscv::xlen_t sepc_q; \
riscv::xlen_t scause_q; \
riscv::xlen_t stval_q; \
riscv::xlen_t satp_q; \
riscv::xlen_t mstatus_extended; \
riscv::xlen_t medeleg_q; \
riscv::xlen_t mideleg_q; \
riscv::xlen_t mtvec_q; \
riscv::xlen_t mcounteren_q; \
riscv::xlen_t mscratch_q; \
riscv::xlen_t mepc_q; \
riscv::xlen_t mcause_q; \
riscv::xlen_t mtval_q; \
logic [riscv::XLEN-1:0] dpc_q; \
logic [riscv::XLEN-1:0] dscratch0_q; \
logic [riscv::XLEN-1:0] dscratch1_q; \
logic [riscv::XLEN-1:0] mie_q; \
logic [riscv::XLEN-1:0] mip_q; \
logic [riscv::XLEN-1:0] stvec_q; \
logic [riscv::XLEN-1:0] scounteren_q; \
logic [riscv::XLEN-1:0] sscratch_q; \
logic [riscv::XLEN-1:0] sepc_q; \
logic [riscv::XLEN-1:0] scause_q; \
logic [riscv::XLEN-1:0] stval_q; \
logic [riscv::XLEN-1:0] satp_q; \
logic [riscv::XLEN-1:0] mstatus_extended; \
logic [riscv::XLEN-1:0] medeleg_q; \
logic [riscv::XLEN-1:0] mideleg_q; \
logic [riscv::XLEN-1:0] mtvec_q; \
logic [riscv::XLEN-1:0] mcounteren_q; \
logic [riscv::XLEN-1:0] mscratch_q; \
logic [riscv::XLEN-1:0] mepc_q; \
logic [riscv::XLEN-1:0] mcause_q; \
logic [riscv::XLEN-1:0] mtval_q; \
logic fiom_q; \
logic [ariane_pkg::MHPMCounterNum+3-1:0] mcountinhibit_q; \
logic [63:0] cycle_q; \
logic [63:0] instret_q; \
riscv::xlen_t dcache_q; \
riscv::xlen_t icache_q; \
riscv::xlen_t acc_cons_q; \
logic [riscv::XLEN-1:0] dcache_q; \
logic [riscv::XLEN-1:0] icache_q; \
logic [riscv::XLEN-1:0] acc_cons_q; \
riscv::pmpcfg_t [15:0] pmpcfg_q; \
logic [15:0][riscv::PLEN-3:0] pmpaddr_q; \
}

19
core/include/std_cache_pkg.sv
View file

@ -61,24 +61,5 @@ package std_cache_pkg;
logic [63:0] rdata;
} bypass_rsp_t;
// convert one hot to bin for -> needed for cache replacement
function automatic logic [DCACHE_SET_ASSOC_WIDTH-1:0] one_hot_to_bin(
input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] in);
for (int unsigned i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin
if (in[i]) return i;
end
endfunction
// get the first bit set, returns one hot value
function automatic logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] get_victim_cl(
input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] valid_dirty);
// one-hot return vector
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] oh = '0;
for (int unsigned i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin
if (valid_dirty[i]) begin
oh[i] = 1'b1;
return oh;
end
end
endfunction
endpackage : std_cache_pkg

60
core/include/wt_cache_pkg.sv
View file

@ -40,7 +40,6 @@ package wt_cache_pkg;
localparam L15_SET_ASSOC = ariane_pkg::DCACHE_SET_ASSOC;// align with dcache for compatibility with the standard Ariane setup
localparam L15_TLB_CSM_WIDTH = 33;
`endif
localparam L15_TID_WIDTH = ariane_pkg::MEM_TID_WIDTH;
localparam L15_WAY_WIDTH = $clog2(L15_SET_ASSOC);
localparam L1I_WAY_WIDTH = $clog2(ariane_pkg::ICACHE_SET_ASSOC);
localparam L1D_WAY_WIDTH = $clog2(ariane_pkg::DCACHE_SET_ASSOC);
@ -51,20 +50,12 @@ package wt_cache_pkg;
// Calculated parameter
localparam ICACHE_OFFSET_WIDTH = $clog2(ariane_pkg::ICACHE_LINE_WIDTH / 8);
localparam ICACHE_NUM_WORDS = 2 ** (ariane_pkg::ICACHE_INDEX_WIDTH - ICACHE_OFFSET_WIDTH);
localparam ICACHE_CL_IDX_WIDTH = $clog2(ICACHE_NUM_WORDS); // excluding byte offset
localparam DCACHE_OFFSET_WIDTH = $clog2(ariane_pkg::DCACHE_LINE_WIDTH / 8);
localparam DCACHE_NUM_WORDS = 2 ** (ariane_pkg::DCACHE_INDEX_WIDTH - DCACHE_OFFSET_WIDTH);
localparam DCACHE_CL_IDX_WIDTH = $clog2(DCACHE_NUM_WORDS); // excluding byte offset
localparam DCACHE_NUM_BANKS = ariane_pkg::DCACHE_LINE_WIDTH / riscv::XLEN;
localparam DCACHE_NUM_BANKS_WIDTH = $clog2(DCACHE_NUM_BANKS);
// write buffer parameterization
localparam DCACHE_WBUF_DEPTH = ariane_pkg::WT_DCACHE_WBUF_DEPTH;
localparam CACHE_ID_WIDTH = L15_TID_WIDTH;
// TX status registers are indexed with the transaction ID
// they basically store which bytes from which buffer entry are part
@ -147,57 +138,6 @@ package wt_cache_pkg;
return cnt;
endfunction : popcnt64
function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable8(
input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
logic [(riscv::XLEN/8)-1:0] be;
be = '0;
unique case (size)
2'b00: be[offset] = '1; // byte
2'b01: be[offset+:2] = '1; // hword
2'b10: be[offset+:4] = '1; // word
default: be = '1; // dword
endcase // size
return be;
endfunction : to_byte_enable8
function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable4(
input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
logic [3:0] be;
be = '0;
unique case (size)
2'b00: be[offset] = '1; // byte
2'b01: be[offset+:2] = '1; // hword
default: be = '1; // word
endcase // size
return be;
endfunction : to_byte_enable4
// openpiton requires the data to be replicated in case of smaller sizes than dwords
function automatic riscv::xlen_t repData64(input riscv::xlen_t data,
input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset,
input logic [1:0] size);
riscv::xlen_t out;
unique case (size)
2'b00: for (int k = 0; k < 8; k++) out[k*8+:8] = data[offset*8+:8]; // byte
2'b01: for (int k = 0; k < 4; k++) out[k*16+:16] = data[offset*8+:16]; // hword
2'b10: for (int k = 0; k < 2; k++) out[k*32+:32] = data[offset*8+:32]; // word
default: out = data; // dword
endcase // size
return out;
endfunction : repData64
function automatic riscv::xlen_t repData32(input riscv::xlen_t data,
input logic [riscv::XLEN_ALIGN_BYTES-1:0] offset,
input logic [1:0] size);
riscv::xlen_t out;
unique case (size)
2'b00: for (int k = 0; k < 4; k++) out[k*8+:8] = data[offset*8+:8]; // byte
2'b01: for (int k = 0; k < 2; k++) out[k*16+:16] = data[offset*8+:16]; // hword
default: out = data; // word
endcase // size
return out;
endfunction : repData32
// note: this is openpiton specific. cannot transmit unaligned words.
// hence we default to individual bytes in that case, and they have to be transmitted
// one after the other

13
core/issue_read_operands.sv
View file

@ -42,13 +42,13 @@ module issue_read_operands
// rs1 operand address - scoreboard
output logic [REG_ADDR_SIZE-1:0] rs1_o,
// rs1 operand - scoreboard
input riscv::xlen_t rs1_i,
input logic [riscv::XLEN-1:0] rs1_i,
// rs1 operand is valid - scoreboard
input logic rs1_valid_i,
// rs2 operand address - scoreboard
output logic [REG_ADDR_SIZE-1:0] rs2_o,
// rs2 operand - scoreboard
input riscv::xlen_t rs2_i,
input logic [riscv::XLEN-1:0] rs2_i,
// rs2 operand is valid - scoreboard
input logic rs2_valid_i,
// rs3 operand address - scoreboard
@ -65,9 +65,9 @@ module issue_read_operands
// TO_BE_COMPLETED - TO_BE_COMPLETED
output fu_data_t fu_data_o,
// Unregistered version of fu_data_o.operanda - TO_BE_COMPLETED
output riscv::xlen_t rs1_forwarding_o,
output logic [riscv::XLEN-1:0] rs1_forwarding_o,
// Unregistered version of fu_data_o.operandb - TO_BE_COMPLETED
output riscv::xlen_t rs2_forwarding_o,
output logic [riscv::XLEN-1:0] rs2_forwarding_o,
// Instruction pc - TO_BE_COMPLETED
output logic [riscv::VLEN-1:0] pc_o,
// Is compressed instruction - TO_BE_COMPLETED
@ -116,13 +116,14 @@ module issue_read_operands
);
logic stall;
logic fu_busy; // functional unit is busy
riscv::xlen_t operand_a_regfile, operand_b_regfile; // operands coming from regfile
logic [riscv::XLEN-1:0] operand_a_regfile, operand_b_regfile; // operands coming from regfile
rs3_len_t
operand_c_regfile,
operand_c_fpr,
operand_c_gpr; // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3
// output flipflop (ID <-> EX)
riscv::xlen_t operand_a_n, operand_a_q, operand_b_n, operand_b_q, imm_n, imm_q, imm_forward_rs3;
logic [riscv::XLEN-1:0]
operand_a_n, operand_a_q, operand_b_n, operand_b_q, imm_n, imm_q, imm_forward_rs3;
logic alu_valid_q;
logic mult_valid_q;

8
core/issue_stage.sv
View file

@ -132,11 +132,11 @@ module issue_stage
fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_fpr_sb_iro;
logic [ REG_ADDR_SIZE-1:0] rs1_iro_sb;
riscv::xlen_t rs1_sb_iro;
logic [ riscv::XLEN-1:0] rs1_sb_iro;
logic rs1_valid_sb_iro;
logic [ REG_ADDR_SIZE-1:0] rs2_iro_sb;
riscv::xlen_t rs2_sb_iro;
logic [ riscv::XLEN-1:0] rs2_sb_iro;
logic rs2_valid_iro_sb;
logic [ REG_ADDR_SIZE-1:0] rs3_iro_sb;
@ -148,8 +148,8 @@ module issue_stage
logic issue_instr_valid_sb_iro;
logic issue_ack_iro_sb;
riscv::xlen_t rs1_forwarding_xlen;
riscv::xlen_t rs2_forwarding_xlen;
logic [ riscv::XLEN-1:0] rs1_forwarding_xlen;
logic [ riscv::XLEN-1:0] rs2_forwarding_xlen;
assign rs1_forwarding_o = rs1_forwarding_xlen[riscv::VLEN-1:0];
assign rs2_forwarding_o = rs2_forwarding_xlen[riscv::VLEN-1:0];

48
core/load_store_unit.sv
View file

@ -50,7 +50,7 @@ module load_store_unit
// Load transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] load_trans_id_o,
// Load result - ISSUE_STAGE
output riscv::xlen_t load_result_o,
output logic [riscv::XLEN-1:0] load_result_o,
// Load result is valid - ISSUE_STAGE
output logic load_valid_o,
// Load exception - ISSUE_STAGE
@ -59,7 +59,7 @@ module load_store_unit
// Store transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] store_trans_id_o,
// Store result - ISSUE_STAGE
output riscv::xlen_t store_result_o,
output logic [riscv::XLEN-1:0] store_result_o,
// Store result is valid - ISSUE_STAGE
output logic store_valid_o,
// Store exception - ISSUE_STAGE
@ -129,25 +129,25 @@ module load_store_unit
);
// data is misaligned
logic data_misaligned;
logic data_misaligned;
// --------------------------------------
// 1st register stage - (stall registers)
// --------------------------------------
// those are the signals which are always correct
// e.g.: they keep the value in the stall case
lsu_ctrl_t lsu_ctrl;
lsu_ctrl_t lsu_ctrl;
logic pop_st;
logic pop_ld;
logic pop_st;
logic pop_ld;
// ------------------------------
// Address Generation Unit (AGU)
// ------------------------------
// virtual address as calculated by the AGU in the first cycle
logic [ riscv::VLEN-1:0] vaddr_i;
riscv::xlen_t vaddr_xlen;
logic overflow;
logic [(riscv::XLEN/8)-1:0] be_i;
logic [ riscv::VLEN-1:0] vaddr_i;
logic [ riscv::XLEN-1:0] vaddr_xlen;
logic overflow;
logic [(riscv::XLEN/8)-1:0] be_i;
assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a));
assign vaddr_i = vaddr_xlen[riscv::VLEN-1:0];
@ -164,23 +164,23 @@ module load_store_unit
logic translation_valid;
logic [riscv::VLEN-1:0] mmu_vaddr;
logic [riscv::PLEN-1:0] mmu_paddr, mmu_vaddr_plen, fetch_vaddr_plen;
exception_t mmu_exception;
logic dtlb_hit;
logic [ riscv::PPNW-1:0] dtlb_ppn;
exception_t mmu_exception;
logic dtlb_hit;
logic [ riscv::PPNW-1:0] dtlb_ppn;
logic ld_valid;
logic [TRANS_ID_BITS-1:0] ld_trans_id;
riscv::xlen_t ld_result;
logic st_valid;
logic [TRANS_ID_BITS-1:0] st_trans_id;
riscv::xlen_t st_result;
logic ld_valid;
logic [TRANS_ID_BITS-1:0] ld_trans_id;
logic [ riscv::XLEN-1:0] ld_result;
logic st_valid;
logic [TRANS_ID_BITS-1:0] st_trans_id;
logic [ riscv::XLEN-1:0] st_result;
logic [ 11:0] page_offset;
logic page_offset_matches;
logic [ 11:0] page_offset;
logic page_offset_matches;
exception_t misaligned_exception;
exception_t ld_ex;
exception_t st_ex;
exception_t misaligned_exception;
exception_t ld_ex;
exception_t st_ex;
// -------------------
// MMU e.g.: TLBs/PTW

4
core/load_unit.sv
View file

@ -44,7 +44,7 @@ module load_unit
// Load transaction ID - TO_BE_COMPLETED
output logic [TRANS_ID_BITS-1:0] trans_id_o,
// Load result - TO_BE_COMPLETED
output riscv::xlen_t result_o,
output logic [riscv::XLEN-1:0] result_o,
// Load exception - TO_BE_COMPLETED
output exception_t ex_o,
// Request address translation - TO_BE_COMPLETED
@ -453,7 +453,7 @@ module load_unit
// ---------------
// Sign Extend
// ---------------
riscv::xlen_t shifted_data;
logic [riscv::XLEN-1:0] shifted_data;
// realign as needed
assign shifted_data = req_port_i.data_rdata >> {ldbuf_rdata.address_offset, 3'b000};

2
core/mmu_sv32/cva6_ptw_sv32.sv
View file

@ -79,7 +79,7 @@ module cva6_ptw_sv32
// input registers
logic data_rvalid_q;
riscv::xlen_t data_rdata_q;
logic [riscv::XLEN-1:0] data_rdata_q;
riscv::pte_sv32_t pte;
assign pte = riscv::pte_sv32_t'(data_rdata_q);

36
core/mult.sv
View file

@ -7,31 +7,31 @@ module mult
parameter type fu_data_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
input logic rst_ni,
// Flush - CONTROLLER
input logic flush_i,
input logic flush_i,
// FU data needed to execute instruction - ISSUE_STAGE
input fu_data_t fu_data_i,
input fu_data_t fu_data_i,
// Mult instruction is valid - ISSUE_STAGE
input logic mult_valid_i,
input logic mult_valid_i,
// Mult result - ISSUE_STAGE
output riscv::xlen_t result_o,
output logic [ riscv::XLEN-1:0] result_o,
// Mult result is valid - ISSUE_STAGE
output logic mult_valid_o,
output logic mult_valid_o,
// Mutl is ready - ISSUE_STAGE
output logic mult_ready_o,
output logic mult_ready_o,
// Mult transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
);
logic mul_valid;
logic div_valid;
logic div_ready_i; // receiver of division result is able to accept the result
logic [TRANS_ID_BITS-1:0] mul_trans_id;
logic [TRANS_ID_BITS-1:0] div_trans_id;
riscv::xlen_t mul_result;
riscv::xlen_t div_result;
logic [riscv::XLEN-1:0] mul_result;
logic [riscv::XLEN-1:0] div_result;
logic div_valid_op;
logic mul_valid_op;
@ -74,13 +74,13 @@ module mult
// ---------------------
// Division
// ---------------------
riscv::xlen_t
logic [riscv::XLEN-1:0]
operand_b,
operand_a; // input operands after input MUX (input silencing, word operations or full inputs)
riscv::xlen_t result; // result before result mux
logic [riscv::XLEN-1:0] result; // result before result mux
logic div_signed; // signed or unsigned division
logic rem; // is it a reminder (or not a reminder e.g.: a division)
logic div_signed; // signed or unsigned division
logic rem; // is it a reminder (or not a reminder e.g.: a division)
logic word_op_d, word_op_q; // save whether the operation was signed or not
// is this a signed op?
@ -102,8 +102,8 @@ module mult
if (riscv::IS_XLEN64 && (fu_data_i.operation == DIVW || fu_data_i.operation == DIVUW || fu_data_i.operation == REMW || fu_data_i.operation == REMUW)) begin
// yes so check if we should sign extend this is only done for a signed operation
if (div_signed) begin
operand_a = sext32(fu_data_i.operand_a[31:0]);
operand_b = sext32(fu_data_i.operand_b[31:0]);
operand_a = sext32(CVA6Cfg, fu_data_i.operand_a[31:0]);
operand_b = sext32(CVA6Cfg, fu_data_i.operand_b[31:0]);
end else begin
operand_a = fu_data_i.operand_a[31:0];
operand_b = fu_data_i.operand_b[31:0];
@ -144,7 +144,7 @@ module mult
// Result multiplexer
// if it was a signed word operation the bit will be set and the result will be sign extended accordingly
assign div_result = (riscv::IS_XLEN64 && word_op_q) ? sext32(result) : result;
assign div_result = (riscv::IS_XLEN64 && word_op_q) ? sext32(CVA6Cfg, result) : result;
// ---------------------
// Registers

24
core/multiplier.sv
View file

@ -21,27 +21,27 @@ module multiplier
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
input logic rst_ni,
// Multiplier transaction ID - Mult
input logic [TRANS_ID_BITS-1:0] trans_id_i,
input logic [TRANS_ID_BITS-1:0] trans_id_i,
// Multiplier instruction is valid - Mult
input logic mult_valid_i,
input logic mult_valid_i,
// Multiplier operation - Mult
input fu_op operation_i,
input fu_op operation_i,
// A operand - Mult
input riscv::xlen_t operand_a_i,
input logic [ riscv::XLEN-1:0] operand_a_i,
// B operand - Mult
input riscv::xlen_t operand_b_i,
input logic [ riscv::XLEN-1:0] operand_b_i,
// Multiplier result - Mult
output riscv::xlen_t result_o,
output logic [ riscv::XLEN-1:0] result_o,
// Mutliplier result is valid - Mult
output logic mult_valid_o,
output logic mult_valid_o,
// Multiplier FU is ready - Mult
output logic mult_ready_o,
output logic mult_ready_o,
// Multiplier transaction ID - Mult
output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
);
// Carry-less multiplication
logic [riscv::XLEN-1:0]
@ -132,7 +132,7 @@ module multiplier
CLMULR: result_o = clmulr_q;
// MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register
default: begin
if (operator_q == MULW && riscv::IS_XLEN64) result_o = sext32(mult_result_q[31:0]);
if (operator_q == MULW && riscv::IS_XLEN64) result_o = sext32(CVA6Cfg, mult_result_q[31:0]);
else result_o = mult_result_q[riscv::XLEN-1:0]; // including MUL
end
endcase

4
core/perf_counters.sv
View file

@ -31,8 +31,8 @@ module perf_counters
// SRAM like interface
input logic [11:0] addr_i, // read/write address (up to 6 counters possible)
input logic we_i, // write enable
input riscv::xlen_t data_i, // data to write
output riscv::xlen_t data_o, // data to read
input logic [riscv::XLEN-1:0] data_i, // data to write
output logic [riscv::XLEN-1:0] data_o, // data to read
// from commit stage
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // the instruction we want to commit
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // acknowledge that we are indeed committing

14
core/scoreboard.sv
View file

@ -37,18 +37,18 @@ module scoreboard #(
output ariane_pkg::fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_fpr_o,
// rs1 operand address - issue_read_operands
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs1_i,
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs1_i,
// rs1 operand - issue_read_operands
output riscv::xlen_t rs1_o,
output logic [ riscv::XLEN-1:0] rs1_o,
// rs1 operand is valid - issue_read_operands
output logic rs1_valid_o,
output logic rs1_valid_o,
// rs2 operand address - issue_read_operands
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs2_i,
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs2_i,
// rs2 operand - issue_read_operands
output riscv::xlen_t rs2_o,
output logic [ riscv::XLEN-1:0] rs2_o,
// rs2 operand is valid - issue_read_operands
output logic rs2_valid_o,
output logic rs2_valid_o,
// rs3 operand address - issue_read_operands
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs3_i,
@ -412,7 +412,7 @@ module scoreboard #(
.idx_o ()
);
riscv::xlen_t rs3;
logic [riscv::XLEN-1:0] rs3;
rr_arb_tree #(
.NumIn(ariane_pkg::NR_SB_ENTRIES + CVA6Cfg.NrWbPorts),

4
core/store_buffer.sv
View file

@ -42,7 +42,7 @@ module store_buffer
input logic [riscv::PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue
output [riscv::PLEN-1:0] rvfi_mem_paddr_o,
input riscv::xlen_t data_i, // data which is placed in the queue
input logic [riscv::XLEN-1:0] data_i, // data which is placed in the queue
input logic [(riscv::XLEN/8)-1:0] be_i, // byte enable in
input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write)
@ -56,7 +56,7 @@ module store_buffer
// 2. Commit queue which is non-speculative, e.g.: the store will definitely happen.
struct packed {
logic [riscv::PLEN-1:0] address;
riscv::xlen_t data;
logic [riscv::XLEN-1:0] data;
logic [(riscv::XLEN/8)-1:0] be;
logic [1:0] data_size;
logic valid; // this entry is valid, we need this for checking if the address offset matches

26
core/store_unit.sv
View file

@ -51,7 +51,7 @@ module store_unit
// Transaction ID - ISSUE_STAGE
output logic [TRANS_ID_BITS-1:0] trans_id_o,
// Store result - ISSUE_STAGE
output riscv::xlen_t result_o,
output logic [riscv::XLEN-1:0] result_o,
// Store exception output - TO_BE_COMPLETED
output exception_t ex_o,
// Address translation request - TO_BE_COMPLETED
@ -79,6 +79,28 @@ module store_unit
// Data cache response - CACHES
output dcache_req_i_t req_port_o
);
// align data to address e.g.: shift data to be naturally 64
function automatic [riscv::XLEN-1:0] data_align(logic [2:0] addr, logic [63:0] data);
// Set addr[2] to 1'b0 when 32bits
logic [ 2:0] addr_tmp = {(addr[2] && riscv::IS_XLEN64), addr[1:0]};
logic [63:0] data_tmp = {64{1'b0}};
case (addr_tmp)
3'b000: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-1:0]};
3'b001:
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-9:0], data[riscv::XLEN-1:riscv::XLEN-8]};
3'b010:
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-17:0], data[riscv::XLEN-1:riscv::XLEN-16]};
3'b011:
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-25:0], data[riscv::XLEN-1:riscv::XLEN-24]};
3'b100: data_tmp = {data[31:0], data[63:32]};
3'b101: data_tmp = {data[23:0], data[63:24]};
3'b110: data_tmp = {data[15:0], data[63:16]};
3'b111: data_tmp = {data[7:0], data[63:8]};
endcase
return data_tmp[riscv::XLEN-1:0];
endfunction
// it doesn't matter what we are writing back as stores don't return anything
assign result_o = lsu_ctrl_i.data;
@ -97,7 +119,7 @@ module store_unit
logic instr_is_amo;
assign instr_is_amo = is_amo(lsu_ctrl_i.operation);
// keep the data and the byte enable for the second cycle (after address translation)
riscv::xlen_t st_data_n, st_data_q;
logic [riscv::XLEN-1:0] st_data_n, st_data_q;
logic [(riscv::XLEN/8)-1:0] st_be_n, st_be_q;
logic [1:0] st_data_size_n, st_data_size_q;
amo_t amo_op_d, amo_op_q;

62
corev_apu/fpga/src/ariane_xilinx.sv
View file

@ -155,57 +155,17 @@ module ariane_xilinx (
);
// CVA6 Xilinx configuration
localparam config_pkg::cva6_user_cfg_t CVA6UserCfg = '{
NrCommitPorts: cva6_config_pkg::CVA6ConfigNrCommitPorts,
AxiAddrWidth: cva6_config_pkg::CVA6ConfigAxiAddrWidth,
AxiDataWidth: cva6_config_pkg::CVA6ConfigAxiDataWidth,
AxiIdWidth: cva6_config_pkg::CVA6ConfigAxiIdWidth,
AxiUserWidth: cva6_config_pkg::CVA6ConfigDataUserWidth,
MemTidWidth: cva6_config_pkg::CVA6ConfigMemTidWidth,
NrLoadBufEntries: cva6_config_pkg::CVA6ConfigNrLoadBufEntries,
RASDepth: cva6_config_pkg::CVA6ConfigRASDepth,
BTBEntries: cva6_config_pkg::CVA6ConfigBTBEntries,
BHTEntries: cva6_config_pkg::CVA6ConfigBHTEntries,
FpuEn: bit'(cva6_config_pkg::CVA6ConfigFpuEn),
XF16: bit'(cva6_config_pkg::CVA6ConfigF16En),
XF16ALT: bit'(cva6_config_pkg::CVA6ConfigF16AltEn),
XF8: bit'(cva6_config_pkg::CVA6ConfigF8En),
RVA: bit'(cva6_config_pkg::CVA6ConfigAExtEn),
RVB: bit'(cva6_config_pkg::CVA6ConfigAExtEn),
RVV: bit'(cva6_config_pkg::CVA6ConfigVExtEn),
RVC: bit'(cva6_config_pkg::CVA6ConfigCExtEn),
RVZCB: bit'(cva6_config_pkg::CVA6ConfigZcbExtEn),
RVZCMP: bit'(cva6_config_pkg::CVA6ConfigZcmpExtEn),
XFVec: bit'(cva6_config_pkg::CVA6ConfigFVecEn),
CvxifEn: bit'(cva6_config_pkg::CVA6ConfigCvxifEn),
ZiCondExtEn: bit'(0),
RVS: bit'(1),
RVU: bit'(1),
HaltAddress: dm::HaltAddress,
ExceptionAddress: dm::ExceptionAddress,
DmBaseAddress: ariane_soc::DebugBase,
TvalEn: bit'(cva6_config_pkg::CVA6ConfigTvalEn),
NrPMPEntries: unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries),
PMPCfgRstVal: {16{64'h0}},
PMPAddrRstVal: {16{64'h0}},
PMPEntryReadOnly: 16'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(1),
NonIdempotentAddrBase: 1024'({64'b0}),
NonIdempotentLength: 1024'({ariane_soc::DRAMBase}),
NrExecuteRegionRules: unsigned'(3),
ExecuteRegionAddrBase: 1024'({ariane_soc::DRAMBase, ariane_soc::ROMBase, ariane_soc::DebugBase}),
ExecuteRegionLength: 1024'({ariane_soc::DRAMLength, ariane_soc::ROMLength, ariane_soc::DebugLength}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({ariane_soc::DRAMBase}),
CachedRegionLength: 1024'({ariane_soc::DRAMLength}),
MaxOutstandingStores: unsigned'(7),
DebugEn: bit'(1),
AxiBurstWriteEn: bit'(0)
};
localparam config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config(CVA6UserCfg);
function automatic config_pkg::cva6_cfg_t build_fpga_config(config_pkg::cva6_user_cfg_t CVA6UserCfg);
config_pkg::cva6_user_cfg_t cfg = CVA6UserCfg;
cfg.ZiCondExtEn = bit'(0);
cfg.NrNonIdempotentRules = unsigned'(1);
cfg.NonIdempotentAddrBase = 1024'({64'b0});
cfg.NonIdempotentLength = 1024'({ariane_soc::DRAMBase});
return build_config_pkg::build_config(cfg);
endfunction
// CVA6 Xilinx configuration
localparam config_pkg::cva6_cfg_t CVA6Cfg = build_fpga_config(cva6_config_pkg::cva6_cfg);
localparam type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg);
localparam type rvfi_probes_csr_t = `RVFI_PROBES_CSR_T(CVA6Cfg);

2
corev_apu/tb/common/tb_readport.sv
View file

@ -47,7 +47,7 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #(
// expresp interface
output logic [63:0] exp_paddr_o,
input logic [1:0] exp_size_i,
input riscv::xlen_t exp_rdata_i,
input logic [riscv::XLEN-1:0] exp_rdata_i,
input logic [63:0] exp_paddr_i,
input logic [63:0] act_paddr_i,

2
corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv
View file

@ -115,7 +115,7 @@ module tb import ariane_pkg::*; import wt_cache_pkg::*; import tb_pkg::*; #()();
} reservation_t;
logic [63:0] act_paddr[1:0];
riscv::xlen_t exp_rdata[1:0];
logic [riscv::XLEN-1:0] exp_rdata[1:0];
logic [63:0] exp_paddr[1:0];
logic [63:0] amo_act_mem;
logic [63:0] amo_shadow;