Moved wire assign to interface

include/mem_if.svh

@@ -25,6 +25,16 @@ interface mem_if
         wire [DATA_WIDTH-1:0]   data_rdata;        // Read data
         wire                    data_we;           // Write enable
         wire [DATA_WIDTH/8-1:0] data_be;           // Byte enable
+
+        // super hack in assigning the wire a value
+        // we need to keep all interface signals as wire as
+        // the simulator does not now if this interface will be used
+        // as an active or passive device
+        // only helpful thread so far:
+        // https://verificationacademy.com/forums/uvm/getting-multiply-driven-warnings-vsim-passive-agent
+        logic data_gnt_driver = 'z;
+        assign data_gnt = data_gnt_driver;
+
         // Memory interface configured as master
         clocking mck @(posedge clk);
             // default input #1ns output #1ns;

tb/agents/mem_if/mem_if_driver.svh

@@ -49,12 +49,12 @@ class mem_if_driver extends uvm_driver #(mem_if_seq_item);
                 slave_gnt: begin
                     forever begin
                         slave_data_gnt = 1'b0;
-                        fu.data_gnt = slave_data_gnt;
+                        fu.data_gnt_driver = slave_data_gnt;
                         wait (fu.data_req);
                         // randomize grant delay
                         repeat ($urandom_range(0,4)) @(fu.mck);
                         slave_data_gnt = 1'b1;
-                        fu.data_gnt = slave_data_gnt;
+                        fu.data_gnt_driver = slave_data_gnt;
                         wait (~fu.data_req);
                     end
                 end

tb/mem_arbiter_tb.sv

@@ -67,7 +67,7 @@ module mem_arbiter_tb;
     program testbench (mem_if master[3], mem_if slave);
         initial begin
             // register the ALU interface
-            uvm_config_db #(virtual fu_if)::set(null, "uvm_test_top", "mem_if", slave);
+            uvm_config_db #(virtual mem_if)::set(null, "uvm_test_top", "mem_if", slave);
             // print the topology
             uvm_top.enable_print_topology = 1;
             // Start UVM test