mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-22 21:27:10 -04:00
fix regress tests and makefiles
Co-authored-by: Côme Allart <come.allart@thalesgroup.com>
This commit is contained in:
Jean-Roch Coulon
Côme Allart
parent
1386369b50
commit
b13530ccbc
24 changed files with 141 additions and 153 deletions
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@ -14,8 +14,8 @@ if [ -z "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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if [ -z "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness,spike
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@ -25,7 +25,7 @@ if [ -z "$DV_TARGET" ]; then
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DV_TARGET=cv64a6_imafdc_sv39
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fi
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cd cva6/sim/
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cd verif/sim/
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BDIR=../tests/riscv-tests/benchmarks/
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CVA6_FLAGS="--target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml cva6.yaml --linker ../tests/custom/common/test.ld"
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@ -61,8 +61,8 @@ python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/spmv/spmv_main.c --gcc_opts "
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python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/towers/towers_main.c --gcc_opts "$GCC_OPTS -I$BDIR/towers/"
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python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/vvadd/vvadd.c --gcc_opts "$GCC_OPTS -I$BDIR/vvadd/ $BDIR/vvadd/vvadd_main.c"
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make -C ../../core-v-cores/cva6 clean
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make clean_all
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make clean
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make -C verif/sim clean_all
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cd -
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@ -19,19 +19,19 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-riscv-compliance.sh
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source ./cva6/regress/install-riscv-tests.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-riscv-compliance.sh
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source verif/regress/install-riscv-tests.sh
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness
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fi
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cd cva6/sim/
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cd verif/sim/
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make -C ../../core-v-cores/cva6 clean
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make clean_all
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make clean
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make -C verif/sim clean_all
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src0=../tests/custom/coremark/core_main.c
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srcA=(
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@ -14,19 +14,19 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-riscv-compliance.sh
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source ./cva6/regress/install-riscv-tests.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-riscv-compliance.sh
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source verif/regress/install-riscv-tests.sh
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness
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fi
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cd cva6/sim/
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cd verif/sim
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make -C ../../core-v-cores/cva6 clean
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make clean_all
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make clean
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make -C verif/sim clean_all
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src0=../tests/riscv-tests/benchmarks/dhrystone/dhrystone_main.c
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srcA=(
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@ -13,9 +13,9 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-spike.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-spike.sh
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv32a60x
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@ -31,7 +31,7 @@ fi
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export cov=1 #enable the Code Coverage
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cd cva6/sim/
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cd verif/sim/
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dd=$(date '+%Y-%m-%d')
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key_word="Mismatch[1]:"
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#Read from the iss_regr.log to detect the failed tests
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@ -13,9 +13,9 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-spike.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-spike.sh
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv32a60x
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@ -32,7 +32,7 @@ fi
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export cov=1 #enable the Code Coverage
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export cvxif=1 #enable cvxif extension for Spike
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cd cva6/sim/
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cd verif/sim/
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dd=$(date '+%Y-%m-%d')
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key_word="Mismatch[1]:"
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#Read from the iss_regr.log to detect the failed tests
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@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-riscv-arch-test.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-riscv-arch-test.sh
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv64a6_imafdc_sv39
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@ -26,6 +26,6 @@ if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness,spike
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fi
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cd cva6/sim
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cd verif/sim
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python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
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cd -
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@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-riscv-compliance.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-riscv-compliance.sh
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv64a6_imafdc_sv39
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@ -26,6 +26,6 @@ if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness,spike
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fi
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cd cva6/sim
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cd verif/sim
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python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS
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cd -
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@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-riscv-arch-test.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-riscv-arch-test.sh
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv32a60x
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@ -26,7 +26,7 @@ if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness,spike
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fi
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cd cva6/sim
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cd verif/sim
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python3 cva6.py --testlist=../tests/testlist_riscv-csr-access-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../sim/link.ld
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cd -
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@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-riscv-tests.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-riscv-tests.sh
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if ! [ -n "$DV_TARGET" ]; then
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DV_TARGET=cv64a6_imafdc_sv39
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@ -31,7 +31,7 @@ if ! [ -n "$DV_TESTLISTS" ]; then
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../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
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fi
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cd cva6/sim
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cd verif/sim
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for TESTLIST in $DV_TESTLISTS
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do
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python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS
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@ -14,17 +14,17 @@ if ! [ -n "$RISCV" ]; then
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fi
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# install the required tools
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source ./cva6/regress/install-cva6.sh
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source ./cva6/regress/install-riscv-dv.sh
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source ./cva6/regress/install-riscv-tests.sh
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source verif/regress/install-cva6.sh
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source verif/regress/install-riscv-dv.sh
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source verif/regress/install-riscv-tests.sh
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if ! [ -n "$DV_SIMULATORS" ]; then
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DV_SIMULATORS=veri-testharness,spike
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fi
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cd cva6/sim/
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cd verif/sim/
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python3 cva6.py --testlist=../tests/testlist_hwconfig.yaml --iss_yaml cva6.yaml --target hwconfig --hwconfig_opts="$DV_HWCONFIG_OPTS" --iss=$DV_SIMULATORS
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make -C ../../core-v-cores/cva6 clean
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make -C ../.. clean
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make clean_all
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cd -
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@ -40,7 +40,7 @@ export CPLUS_INCLUDE_PATH="$RISCV/include"
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# Set VERILATOR_INSTALL_DIR to 'NO' to skip installation and checks
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# of Verilator (useful for CI jobs not depending on Verilator in any way).
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if [ "$VERILATOR_INSTALL_DIR" != "NO" ]; then
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source cva6/regress/install-verilator.sh
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source verif/regress/install-verilator.sh
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# Complain if the installation directory of Verilator still is not set
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# after running the installer.
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@ -75,19 +75,8 @@ echo $CVA6_BRANCH
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echo $CVA6_HASH
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echo $CVA6_PATCH
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if ! [ -d core-v-cores/cva6 ]; then
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git clone --recursive $CVA6_REPO -b $CVA6_BRANCH core-v-cores/cva6
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pushd core-v-cores/cva6
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git checkout $CVA6_HASH
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echo -n "Using CVA6 commit "; git describe --always HEAD
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if [[ -n "$CVA6_PATCH" && -f "$CVA6_PATCH" ]]; then
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git apply "$CVA6_PATCH"
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fi
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popd
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fi
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# install Spike
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if [ -z "$SPIKE_ROOT" ]; then
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export SPIKE_ROOT=$TOP/spike/
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fi
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source cva6/regress/install-spike.sh
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source verif/regress/install-spike.sh
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@ -8,7 +8,7 @@
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# Original Author: Jean-Roch COULON - Thales
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# riscv-arch-tests uses definition of RVMODEL_HALT provided by Spike.
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. cva6/regress/install-spike.sh
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. verif/regress/install-spike.sh
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if [ ! -d $SPIKE_SRC_DIR/arch_test_target ]; then
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echo "*** Variable SPIKE_SRC_DIR must point to a source-based installation of Spike."
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return 1
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@ -24,10 +24,10 @@ echo "Branch:" $ARCH_TEST_BRANCH
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echo "Hash: " $ARCH_TEST_HASH
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mkdir -p cva6/tests
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if ! [ -d cva6/tests/riscv-arch-test ]; then
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git clone $ARCH_TEST_REPO -b $ARCH_TEST_BRANCH cva6/tests/riscv-arch-test
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cd cva6/tests/riscv-arch-test; git checkout $ARCH_TEST_HASH;
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mkdir -p verif/tests
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if ! [ -d verif/tests/riscv-arch-test ]; then
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git clone $ARCH_TEST_REPO -b $ARCH_TEST_BRANCH verif/tests/riscv-arch-test
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cd verif/tests/riscv-arch-test; git checkout $ARCH_TEST_HASH;
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# Copy Spike definitions to the corresponding riscv-target subdirectory.
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cp -rpa $SPIKE_SRC_DIR/arch_test_target riscv-target
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cd -
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@ -11,17 +11,17 @@ if ! [ -n "$COMPLIANCE_REPO" ]; then
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COMPLIANCE_REPO="https://github.com/riscv-non-isa/riscv-arch-test.git"
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COMPLIANCE_BRANCH="main"
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COMPLIANCE_HASH="220e78542da4510e40eac31e31fdd4e77cdae437"
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COMPLIANCE_PATCH="../../../cva6/regress/riscv-compliance.patch"
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COMPLIANCE_PATCH="../../../verif/regress/riscv-compliance.patch"
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fi
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echo "Repo: " $COMPLIANCE_REPO
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echo "Branch:" $COMPLIANCE_BRANCH
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echo "Hash: " $COMPLIANCE_HASH
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echo "Patch: " $COMPLIANCE_PATCH
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mkdir -p cva6/tests
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if ! [ -d cva6/tests/riscv-compliance ]; then
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git clone $COMPLIANCE_REPO -b $COMPLIANCE_BRANCH cva6/tests/riscv-compliance
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cd cva6/tests/riscv-compliance; git checkout $COMPLIANCE_HASH;
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mkdir -p verif/tests
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if ! [ -d verif/tests/riscv-compliance ]; then
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git clone $COMPLIANCE_REPO -b $COMPLIANCE_BRANCH verif/tests/riscv-compliance
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cd verif/tests/riscv-compliance; git checkout $COMPLIANCE_HASH;
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if [[ -n "$COMPLIANCE_PATCH" && -f "$COMPLIANCE_PATCH" ]]; then
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echo "Applying patch $COMPLIANCE_PATCH in $PWD..."
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git apply "$COMPLIANCE_PATCH"
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@ -16,9 +16,9 @@ if [ -z "$RISCV_OBJCOPY" ]; then
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export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv-none-elf-objcopy"
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fi
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export SPIKE_PATH=$SPIKE_ROOT/bin
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export RTL_PATH=$ROOT_PROJECT/core-v-cores/cva6
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export TB_PATH=$ROOT_PROJECT/cva6/tb/core
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export TESTS_PATH=$ROOT_PROJECT/cva6/tests
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export RTL_PATH=$ROOT_PROJECT/
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export TB_PATH=$ROOT_PROJECT/verif/tb/core
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export TESTS_PATH=$ROOT_PROJECT/verif/tests
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if [ -z "$DV_REPO" ]; then
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export DV_REPO="https://github.com/google/riscv-dv.git"
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@ -31,15 +31,15 @@ echo "Branch:" $DV_BRANCH
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echo "Hash: " $DV_HASH
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echo "Patch: " $DV_PATCH
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mkdir -p cva6/sim
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if ! [ -d cva6/sim/dv ]; then
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git clone $DV_REPO -b $DV_BRANCH cva6/sim/dv
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cd cva6/sim/dv; git checkout $DV_HASH;
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mkdir -p verif/sim
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if ! [ -d verif/sim/dv ]; then
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git clone $DV_REPO -b $DV_BRANCH verif/sim/dv
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cd verif/sim/dv; git checkout $DV_HASH;
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if [[ -n "$DV_PATCH" && -f "$DV_PATCH" ]]; then
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git apply "$DV_PATCH"
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fi
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cd -
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# install riscv-dv dependencies
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cd cva6/sim/dv; pip3 install -r requirements.txt; cd -
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cd verif/sim/dv; pip3 install -r requirements.txt; cd -
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fi
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@ -16,11 +16,11 @@ echo "Repo: " $TESTS_REPO
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echo "Branch:" $TESTS_BRANCH
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echo "Hash: " $TESTS_HASH
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mkdir -p cva6/tests
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if ! [ -d cva6/tests/riscv-tests ]; then
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git clone $TESTS_REPO -b $TESTS_BRANCH cva6/tests/riscv-tests
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cd cva6/tests/riscv-tests; git checkout $TESTS_HASH;
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mkdir -p verif/tests
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if ! [ -d verif/tests/riscv-tests ]; then
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git clone $TESTS_REPO -b $TESTS_BRANCH verif/tests/riscv-tests
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cd verif/tests/riscv-tests; git checkout $TESTS_HASH;
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git submodule update --init --recursive
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git apply --directory=env ../../../cva6/regress/riscv-tests-env.patch
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git apply --directory=env ../../../verif/regress/riscv-tests-env.patch
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cd -
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fi
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ VERILATOR_REPO="https://github.com/verilator/verilator.git"
|
|||
VERILATOR_BRANCH="master"
|
||||
# Use the release tag instead of a full SHA1 hash.
|
||||
VERILATOR_HASH="v5.008"
|
||||
VERILATOR_PATCH="$TOP/../cva6/regress/verilator-v5.patch"
|
||||
VERILATOR_PATCH="$TOP/../verif/regress/verilator-v5.patch"
|
||||
|
||||
# Unset historical variable VERILATOR_ROOT as it collides with the build process.
|
||||
if [ -n "$VERILATOR_ROOT" ]; then
|
||||
|
|
|
|||
|
|
@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
|
|||
fi
|
||||
|
||||
# install the required tools
|
||||
source ./cva6/regress/install-cva6.sh
|
||||
source ./cva6/regress/install-riscv-dv.sh
|
||||
source ./cva6/regress/install-riscv-compliance.sh
|
||||
source verif/regress/install-cva6.sh
|
||||
source verif/regress/install-riscv-dv.sh
|
||||
source verif/regress/install-riscv-compliance.sh
|
||||
|
||||
if ! [ -n "$DV_SIMULATORS" ]; then
|
||||
echo "Error DV_SIMULATORS variable undefined"
|
||||
|
|
@ -25,9 +25,9 @@ if ! [ -n "$DV_TARGET" ]; then
|
|||
echo "Error DV_TARGET variable undefined"
|
||||
fi
|
||||
|
||||
cd cva6/sim/
|
||||
cd verif/sim/
|
||||
python3 cva6.py --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --test rv32ui-addi
|
||||
make -C ../../core-v-cores/cva6 clean
|
||||
make clean_all
|
||||
make clean
|
||||
make -C verif/sim clean_all
|
||||
|
||||
cd -
|
||||
|
|
|
|||
|
|
@ -14,21 +14,21 @@ if ! [ -n "$RISCV" ]; then
|
|||
fi
|
||||
|
||||
# install the required tools
|
||||
source ./cva6/regress/install-cva6.sh
|
||||
source ./cva6/regress/install-riscv-dv.sh
|
||||
source ./cva6/regress/install-riscv-compliance.sh
|
||||
source ./cva6/regress/install-riscv-tests.sh
|
||||
source verif/regress/install-cva6.sh
|
||||
source verif/regress/install-riscv-dv.sh
|
||||
source verif/regress/install-riscv-compliance.sh
|
||||
source verif/regress/install-riscv-tests.sh
|
||||
|
||||
if ! [ -n "$DV_SIMULATORS" ]; then
|
||||
DV_SIMULATORS=veri-testharness,spike
|
||||
fi
|
||||
|
||||
cd cva6/sim/
|
||||
cd verif/sim/
|
||||
python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg-commits-rv64 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
|
||||
make -C ../../core-v-cores/cva6 clean
|
||||
make clean_all
|
||||
make clean
|
||||
make -C verif/sim clean_all
|
||||
python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg-commits-rv32 --iss_yaml cva6.yaml --target cv32a6_imafc_sv32 --iss=$DV_SIMULATORS $DV_OPTS
|
||||
make -C ../../core-v-cores/cva6 clean
|
||||
make clean_all
|
||||
make clean
|
||||
make -C verif/sim clean_all
|
||||
|
||||
cd -
|
||||
|
|
|
|||
|
|
@ -21,14 +21,14 @@ if ! [ -n "$BBL_ROOT" ]; then
|
|||
fi
|
||||
|
||||
# install the required tools
|
||||
source ./cva6/regress/install-cva6.sh
|
||||
source ./cva6/regress/install-riscv-dv.sh
|
||||
source verif/regress/install-cva6.sh
|
||||
source verif/regress/install-riscv-dv.sh
|
||||
|
||||
if ! [ -n "$DV_SIMULATORS" ]; then
|
||||
DV_SIMULATORS=veri-testharness
|
||||
fi
|
||||
|
||||
cd cva6/sim
|
||||
cd verif/sim
|
||||
cp $BBL_ROOT/bbl bbl.o
|
||||
python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --elf_tests bbl.o\
|
||||
--issrun_opts="+time_out=40000000 +debug_disable=1" --isspostrun_opts="ffffffe0005e5cd4"
|
||||
|
|
|
|||
|
|
@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
|
|||
fi
|
||||
|
||||
# install the required tools
|
||||
source ./cva6/regress/install-cva6.sh
|
||||
source ./cva6/regress/install-riscv-dv.sh
|
||||
source ./cva6/regress/install-riscv-isa-sim.sh
|
||||
source verif/regress/install-cva6.sh
|
||||
source verif/regress/install-riscv-dv.sh
|
||||
source verif/regress/install-riscv-isa-sim.sh
|
||||
|
||||
if ! [ -n "$DV_TARGET" ]; then
|
||||
DV_TARGET=cv32a60x
|
||||
|
|
@ -26,7 +26,7 @@ if ! [ -n "$DV_SIMULATORS" ]; then
|
|||
DV_SIMULATORS=vcs-uvm,spike
|
||||
fi
|
||||
|
||||
cd cva6/sim/
|
||||
cd verif/sim/
|
||||
cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
|
||||
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
|
||||
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
|
||||
|
|
|
|||
|
|
@ -14,18 +14,18 @@ if ! [ -n "$RISCV" ]; then
|
|||
fi
|
||||
|
||||
# install the required tools
|
||||
source ./cva6/regress/install-cva6.sh
|
||||
source ./cva6/regress/install-riscv-dv.sh
|
||||
source ./cva6/regress/install-riscv-compliance.sh
|
||||
source ./cva6/regress/install-riscv-tests.sh
|
||||
source ./cva6/regress/install-riscv-arch-test.sh
|
||||
source ./verif/regress/install-cva6.sh
|
||||
source ./verif/regress/install-riscv-dv.sh
|
||||
source ./verif/regress/install-riscv-compliance.sh
|
||||
source ./verif/regress/install-riscv-tests.sh
|
||||
source ./verif/regress/install-riscv-arch-test.sh
|
||||
|
||||
|
||||
if ! [ -n "$DV_SIMULATORS" ]; then
|
||||
DV_SIMULATORS=vcs-testharness,spike
|
||||
fi
|
||||
|
||||
cd cva6/sim/
|
||||
cd verif/sim/
|
||||
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
|
||||
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
|
||||
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
|
||||
|
|
@ -33,14 +33,14 @@ python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.
|
|||
python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
|
||||
python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\
|
||||
--gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld"
|
||||
make -C ../../core-v-cores/cva6 clean
|
||||
make -C ../.. clean
|
||||
make clean_all
|
||||
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
|
||||
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
|
||||
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
|
||||
python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../tests/custom/common/test.ld\
|
||||
--gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common"
|
||||
make -C ../../core-v-cores/cva6 clean
|
||||
make -C ../.. clean
|
||||
make clean_all
|
||||
|
||||
cd -
|
||||
|
|
|
|||
|
|
@ -12,9 +12,8 @@ root-dir := $(dir $(mkfile_path))
|
|||
|
||||
ifndef CVA6_REPO_DIR
|
||||
$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...)
|
||||
export CVA6_REPO_DIR = $(abspath $(root-dir)../../core-v-cores/cva6/)
|
||||
export CVA6_REPO_DIR = $(abspath $(root-dir)../..)
|
||||
export CVA6_TB_DIR = $(root-dir)/../tb/core
|
||||
export CORE_V_VERIF = $(root-dir)/../..
|
||||
endif
|
||||
ifndef TARGET_CFG
|
||||
export TARGET_CFG = $(target)
|
||||
|
|
@ -144,65 +143,65 @@ questa-testharness:
|
|||
# UVM specific commands, variables
|
||||
###############################################################################
|
||||
ALL_VCS_FLAGS = $(if $(VERDI), -kdb -debug_access+all -lca,) -sverilog -full64 -timescale=1ns/1ns
|
||||
VCS_WORK_DIR = $(CORE_V_VERIF)/cva6/sim/vcs_results/default/vcs.d
|
||||
VCS_WORK_DIR = $(CVA6_REPO_DIR)/verif/sim/vcs_results/default/vcs.d
|
||||
SIMV = $(VCS_WORK_DIR)/simv
|
||||
|
||||
export CVA6_UVMT_DIR = $(CORE_V_VERIF)/cva6/tb/uvmt
|
||||
export CVA6_UVMT_PATH = $(CORE_V_VERIF)/cva6/tb/uvmt
|
||||
export CVA6_UVME_PATH = $(CORE_V_VERIF)/cva6/env/uvme
|
||||
export CVA6_UVMT_DIR = $(CVA6_REPO_DIR)/verif/tb/uvmt
|
||||
export CVA6_UVMT_PATH = $(CVA6_REPO_DIR)/verif/tb/uvmt
|
||||
export CVA6_UVME_PATH = $(CVA6_REPO_DIR)/verif/env/uvme
|
||||
export CV_CORE_LC = cva6
|
||||
export CV_CORE_UC = CVA6
|
||||
export DV_UVMT_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/tb/uvmt
|
||||
export DV_UVME_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/env/uvme
|
||||
export DV_UVML_HRTBT_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_hrtbt
|
||||
export DV_UVMA_CORE_CNTRL_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_core_cntrl
|
||||
export DV_UVMA_RVFI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_rvfi
|
||||
export DV_UVMA_ISACOV_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_isacov
|
||||
export DV_UVMA_CLKNRST_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_clknrst
|
||||
export DV_UVMA_CVXIF_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_cvxif
|
||||
export DV_UVMA_AXI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_axi
|
||||
export DV_UVMA_INTERRUPT_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_interrupt
|
||||
export DV_UVMA_DEBUG_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_debug
|
||||
export DV_UVMA_OBI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_obi
|
||||
export DV_UVML_TRN_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_trn
|
||||
export DV_UVML_MEM_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_mem
|
||||
export DV_UVML_LOGS_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_logs
|
||||
export DV_UVML_SB_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_sb
|
||||
export CV_CORE_PKG = $(CORE_V_VERIF)/core-v-cores/$(CV_CORE_LC)
|
||||
export DV_UVMT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/tb/uvmt
|
||||
export DV_UVME_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/env/uvme
|
||||
export DV_UVML_HRTBT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_hrtbt
|
||||
export DV_UVMA_CORE_CNTRL_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl
|
||||
export DV_UVMA_RVFI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi
|
||||
export DV_UVMA_ISACOV_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_isacov
|
||||
export DV_UVMA_CLKNRST_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_clknrst
|
||||
export DV_UVMA_CVXIF_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_cvxif
|
||||
export DV_UVMA_AXI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_axi
|
||||
export DV_UVMA_INTERRUPT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_interrupt
|
||||
export DV_UVMA_DEBUG_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_debug
|
||||
export DV_UVMA_OBI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_obi
|
||||
export DV_UVML_TRN_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_trn
|
||||
export DV_UVML_MEM_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_mem
|
||||
export DV_UVML_LOGS_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_logs
|
||||
export DV_UVML_SB_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_sb
|
||||
export CV_CORE_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/core-v-cores/$(CV_CORE_LC)
|
||||
export DESIGN_RTL_DIR = $(CV_CORE_PKG)/rtl
|
||||
|
||||
DPI_DASM_PKG = $(CORE_V_VERIF)/lib/dpi_dasm
|
||||
DPI_DASM_SPIKE_PKG = $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/dpi_dasm_spike
|
||||
DPI_DASM_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/dpi_dasm
|
||||
DPI_DASM_SPIKE_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/vendor_lib/dpi_dasm_spike
|
||||
export DPI_DASM_ROOT = $(DPI_DASM_PKG)
|
||||
export DPI_DASM_SPIKE_ROOT = $(DPI_DASM_SPIKE_PKG)
|
||||
export TBSRC_HOME = $(CORE_V_VERIF)/cva6/tb
|
||||
export DV_OVPM_HOME = $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/imperas
|
||||
export TBSRC_HOME = $(CVA6_REPO_DIR)/verif/tb
|
||||
export DV_OVPM_HOME = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/vendor_lib/imperas
|
||||
export DV_OVPM_MODEL = $(DV_OVPM_HOME)/riscv_$(CV_CORE_UC)_OVPsim
|
||||
export DV_OVPM_DESIGN = $(DV_OVPM_HOME)/design
|
||||
|
||||
ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \
|
||||
$(VCS_HOME)/etc/uvm/src/uvm_pkg.sv +UVM_VERBOSITY=UVM_MEDIUM -ntb_opts uvm-1.2 -timescale=1ns/1ps \
|
||||
-assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \
|
||||
+incdir+$(CORE_V_VERIF)/$(CV_CORE_LC)/env/uvme +incdir+$(CORE_V_VERIF)/$(CV_CORE_LC)/tb/uvmt \
|
||||
+incdir+$(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/env/uvme +incdir+$(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/tb/uvmt \
|
||||
$(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon))
|
||||
|
||||
ALL_SIMV_UVM_FLAGS = -licwait 20 $(issrun_opts) \
|
||||
-sv_lib $(CORE_V_VERIF)/lib/dpi_dasm/lib/Linux64/libdpi_dasm +signature=I-ADD-01.signature_output \
|
||||
-sv_lib $(CVA6_REPO_DIR)/verif/core-v-verif/lib/dpi_dasm/lib/Linux64/libdpi_dasm +signature=I-ADD-01.signature_output \
|
||||
+UVM_TESTNAME=uvmt_cva6_firmware_test_c
|
||||
|
||||
ifneq ($(DEBUG),) # If RTL DEBUG support requested
|
||||
ifneq ($(VERDI),) # If VERDI interactive mode requested, use GUI and do not run simulation
|
||||
ALL_SIMV_UVM_FLAGS += \
|
||||
-gui -do $(CORE_V_VERIF)/cva6/sim/init_uvm.do
|
||||
-gui -do $(CVA6_REPO_DIR)/verif/sim/init_uvm.do
|
||||
else # else: *not* VERDI, use CLI mode and appropriate batch dump controls
|
||||
ifneq ($(TRACE_FAST),) # TRACE_FAST: Generate waveform trace in VPD format
|
||||
ALL_SIMV_UVM_FLAGS += \
|
||||
-ucli -do $(CORE_V_VERIF)/cva6/sim/init_run_uvm_vpd.do
|
||||
-ucli -do $(CVA6_REPO_DIR)/verif/sim/init_run_uvm_vpd.do
|
||||
SIMV_TRACE_EXTN = vpd
|
||||
endif
|
||||
ifneq ($(TRACE_COMPACT),) # TRACE_COMPACT: Generate waveform trace in FSDB format
|
||||
ALL_SIMV_UVM_FLAGS += \
|
||||
-ucli -do $(CORE_V_VERIF)/cva6/sim/init_run_uvm_fsdb.do
|
||||
-ucli -do $(CVA6_REPO_DIR)/verif/sim/init_run_uvm_fsdb.do
|
||||
SIMV_TRACE_EXTN = fsdb
|
||||
endif
|
||||
endif
|
||||
|
|
@ -234,9 +233,9 @@ vcs_uvm_run:
|
|||
+tohost_addr=$(shell $$RISCV/bin/riscv-none-elf-nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
|
||||
-sv_lib $(dpi-library)/ariane_dpi \
|
||||
$(cov-run-opt) $(issrun_opts) && \
|
||||
mv $(VCS_WORK_DIR)/trace_rvfi_hart_00.dasm $(CORE_V_VERIF)/cva6/sim/ && \
|
||||
mv $(VCS_WORK_DIR)/trace_rvfi_hart_00.dasm $(CVA6_REPO_DIR)/verif/sim/ && \
|
||||
{ [ -z "`ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)`" ] || \
|
||||
for i in `ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)` ; do mv $$i $(CORE_V_VERIF)/cva6/sim/`basename $$i` ; done || \
|
||||
for i in `ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)` ; do mv $$i $(CVA6_REPO_DIR)/verif/sim/`basename $$i` ; done || \
|
||||
true ; }
|
||||
|
||||
vcs-uvm:
|
||||
|
|
@ -252,7 +251,7 @@ generate_cov_dash:
|
|||
|
||||
vcs_clean_all:
|
||||
@echo "[VCS] Cleanup (entire vcs_work dir)"
|
||||
rm -rf $(CORE_V_VERIF)/cva6/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart
|
||||
rm -rf $(CVA6_REPO_DIR)/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart
|
||||
|
||||
###############################################################################
|
||||
# Common targets and rules
|
||||
|
|
|
|||
|
|
@ -936,7 +936,7 @@ def load_config(args, cwd):
|
|||
args.isa = "rv64imc"
|
||||
elif args.target == "hwconfig":
|
||||
current_path = os.getcwd()
|
||||
os.chdir(os.getcwd()+"/../../core-v-cores/cva6")
|
||||
os.chdir(os.getcwd()+"/../../")
|
||||
[args.isa,args.mabi, args.target, args.hwconfig_opts] = generate_config(args.hwconfig_opts.split())
|
||||
os.chdir(current_path)
|
||||
else:
|
||||
|
|
@ -1219,7 +1219,7 @@ def main():
|
|||
sys.exit(130)
|
||||
|
||||
if __name__ == "__main__":
|
||||
sys.path.append(os.getcwd()+"/../../core-v-cores/cva6/util")
|
||||
sys.path.append(os.getcwd()+"/../../util")
|
||||
from config_pkg_generator import *
|
||||
main()
|
||||
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ root-dir := $(dir $(mkfile_path))
|
|||
|
||||
ifndef CVA6_REPO_DIR
|
||||
$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...)
|
||||
export CVA6_REPO_DIR = $(abspath $(root-dir)../../../core-v-cores/cva6/)
|
||||
export CVA6_REPO_DIR = $(abspath $(root-dir)../../../)
|
||||
export CVA6_TB_DIR = $(root-dir)
|
||||
endif
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue