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fix regress tests and makefiles

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Co-authored-by: Côme Allart <come.allart@thalesgroup.com>
This commit is contained in:
Jean-Roch Coulon 2023-08-23 23:15:21 +02:00 • committed by Côme Allart
parent 1386369b50
commit b13530ccbc
24 changed files with 141 additions and 153 deletions
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10
verif/regress/benchmark.sh
View file

@ -14,8 +14,8 @@ if [ -z "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
if [ -z "$DV_SIMULATORS" ]; then if [ -z "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness,spike DV_SIMULATORS=veri-testharness,spike
@ -25,7 +25,7 @@ if [ -z "$DV_TARGET" ]; then
DV_TARGET=cv64a6_imafdc_sv39 DV_TARGET=cv64a6_imafdc_sv39
fi fi
cd cva6/sim/ cd verif/sim/
BDIR=../tests/riscv-tests/benchmarks/ BDIR=../tests/riscv-tests/benchmarks/
CVA6_FLAGS="--target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml cva6.yaml --linker ../tests/custom/common/test.ld" CVA6_FLAGS="--target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml cva6.yaml --linker ../tests/custom/common/test.ld"
@ -61,8 +61,8 @@ python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/spmv/spmv_main.c --gcc_opts "
python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/towers/towers_main.c --gcc_opts "$GCC_OPTS -I$BDIR/towers/" python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/towers/towers_main.c --gcc_opts "$GCC_OPTS -I$BDIR/towers/"
python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/vvadd/vvadd.c --gcc_opts "$GCC_OPTS -I$BDIR/vvadd/ $BDIR/vvadd/vvadd_main.c" python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/vvadd/vvadd.c --gcc_opts "$GCC_OPTS -I$BDIR/vvadd/ $BDIR/vvadd/vvadd_main.c"
make -C ../../core-v-cores/cva6 clean make clean
make clean_all make -C verif/sim clean_all
cd - cd -

14
verif/regress/coremark.sh
View file

@ -19,19 +19,19 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-compliance.sh source verif/regress/install-riscv-compliance.sh
source ./cva6/regress/install-riscv-tests.sh source verif/regress/install-riscv-tests.sh
if ! [ -n "$DV_SIMULATORS" ]; then if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness DV_SIMULATORS=veri-testharness
fi fi
cd cva6/sim/ cd verif/sim/
make -C ../../core-v-cores/cva6 clean make clean
make clean_all make -C verif/sim clean_all
src0=../tests/custom/coremark/core_main.c src0=../tests/custom/coremark/core_main.c
srcA=( srcA=(

14
verif/regress/dhrystone.sh
View file

@ -14,19 +14,19 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-compliance.sh source verif/regress/install-riscv-compliance.sh
source ./cva6/regress/install-riscv-tests.sh source verif/regress/install-riscv-tests.sh
if ! [ -n "$DV_SIMULATORS" ]; then if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness DV_SIMULATORS=veri-testharness
fi fi
cd cva6/sim/ cd verif/sim
make -C ../../core-v-cores/cva6 clean make clean
make clean_all make -C verif/sim clean_all
src0=../tests/riscv-tests/benchmarks/dhrystone/dhrystone_main.c src0=../tests/riscv-tests/benchmarks/dhrystone/dhrystone_main.c
srcA=( srcA=(

8
verif/regress/dv-generated-tests.sh
View file

@ -13,9 +13,9 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-spike.sh source verif/regress/install-spike.sh
if ! [ -n "$DV_TARGET" ]; then if ! [ -n "$DV_TARGET" ]; then
DV_TARGET=cv32a60x DV_TARGET=cv32a60x
@ -31,7 +31,7 @@ fi
export cov=1 #enable the Code Coverage export cov=1 #enable the Code Coverage
cd cva6/sim/ cd verif/sim/
dd=$(date '+%Y-%m-%d') dd=$(date '+%Y-%m-%d')
key_word="Mismatch[1]:" key_word="Mismatch[1]:"
#Read from the iss_regr.log to detect the failed tests #Read from the iss_regr.log to detect the failed tests

8
verif/regress/dv-generated-xif-tests.sh
View file

@ -13,9 +13,9 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-spike.sh source verif/regress/install-spike.sh
if ! [ -n "$DV_TARGET" ]; then if ! [ -n "$DV_TARGET" ]; then
DV_TARGET=cv32a60x DV_TARGET=cv32a60x
@ -32,7 +32,7 @@ fi
export cov=1 #enable the Code Coverage export cov=1 #enable the Code Coverage
export cvxif=1 #enable cvxif extension for Spike export cvxif=1 #enable cvxif extension for Spike
cd cva6/sim/ cd verif/sim/
dd=$(date '+%Y-%m-%d') dd=$(date '+%Y-%m-%d')
key_word="Mismatch[1]:" key_word="Mismatch[1]:"
#Read from the iss_regr.log to detect the failed tests #Read from the iss_regr.log to detect the failed tests

8
verif/regress/dv-riscv-arch-test.sh
View file

@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-arch-test.sh source verif/regress/install-riscv-arch-test.sh
if ! [ -n "$DV_TARGET" ]; then if ! [ -n "$DV_TARGET" ]; then
DV_TARGET=cv64a6_imafdc_sv39 DV_TARGET=cv64a6_imafdc_sv39
@ -26,6 +26,6 @@ if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness,spike DV_SIMULATORS=veri-testharness,spike
fi fi
cd cva6/sim cd verif/sim
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
cd - cd -

8
verif/regress/dv-riscv-compliance.sh
View file

@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-compliance.sh source verif/regress/install-riscv-compliance.sh
if ! [ -n "$DV_TARGET" ]; then if ! [ -n "$DV_TARGET" ]; then
DV_TARGET=cv64a6_imafdc_sv39 DV_TARGET=cv64a6_imafdc_sv39
@ -26,6 +26,6 @@ if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness,spike DV_SIMULATORS=veri-testharness,spike
fi fi
cd cva6/sim cd verif/sim
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS
cd - cd -

8
verif/regress/dv-riscv-csr-access-test.sh
View file

@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-arch-test.sh source verif/regress/install-riscv-arch-test.sh
if ! [ -n "$DV_TARGET" ]; then if ! [ -n "$DV_TARGET" ]; then
DV_TARGET=cv32a60x DV_TARGET=cv32a60x
@ -26,7 +26,7 @@ if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness,spike DV_SIMULATORS=veri-testharness,spike
fi fi
cd cva6/sim cd verif/sim
python3 cva6.py --testlist=../tests/testlist_riscv-csr-access-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../sim/link.ld python3 cva6.py --testlist=../tests/testlist_riscv-csr-access-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../sim/link.ld
cd - cd -

8
verif/regress/dv-riscv-tests.sh
View file

@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-tests.sh source verif/regress/install-riscv-tests.sh
if ! [ -n "$DV_TARGET" ]; then if ! [ -n "$DV_TARGET" ]; then
DV_TARGET=cv64a6_imafdc_sv39 DV_TARGET=cv64a6_imafdc_sv39
@ -31,7 +31,7 @@ if ! [ -n "$DV_TESTLISTS" ]; then
../tests/testlist_riscv-tests-$DV_TARGET-v.yaml" ../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
fi fi
cd cva6/sim cd verif/sim
for TESTLIST in $DV_TESTLISTS for TESTLIST in $DV_TESTLISTS
do do
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS

10
verif/regress/hwconfig_tests.sh
View file

@ -14,17 +14,17 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-tests.sh source verif/regress/install-riscv-tests.sh
if ! [ -n "$DV_SIMULATORS" ]; then if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness,spike DV_SIMULATORS=veri-testharness,spike
fi fi
cd cva6/sim/ cd verif/sim/
python3 cva6.py --testlist=../tests/testlist_hwconfig.yaml --iss_yaml cva6.yaml --target hwconfig --hwconfig_opts="$DV_HWCONFIG_OPTS" --iss=$DV_SIMULATORS python3 cva6.py --testlist=../tests/testlist_hwconfig.yaml --iss_yaml cva6.yaml --target hwconfig --hwconfig_opts="$DV_HWCONFIG_OPTS" --iss=$DV_SIMULATORS
make -C ../../core-v-cores/cva6 clean make -C ../.. clean
make clean_all make clean_all
cd - cd -

15
verif/regress/install-cva6.sh
View file

@ -40,7 +40,7 @@ export CPLUS_INCLUDE_PATH="$RISCV/include"
# Set VERILATOR_INSTALL_DIR to 'NO' to skip installation and checks # Set VERILATOR_INSTALL_DIR to 'NO' to skip installation and checks
# of Verilator (useful for CI jobs not depending on Verilator in any way). # of Verilator (useful for CI jobs not depending on Verilator in any way).
if [ "$VERILATOR_INSTALL_DIR" != "NO" ]; then if [ "$VERILATOR_INSTALL_DIR" != "NO" ]; then
source cva6/regress/install-verilator.sh source verif/regress/install-verilator.sh
# Complain if the installation directory of Verilator still is not set # Complain if the installation directory of Verilator still is not set
# after running the installer. # after running the installer.
@ -75,19 +75,8 @@ echo $CVA6_BRANCH
echo $CVA6_HASH echo $CVA6_HASH
echo $CVA6_PATCH echo $CVA6_PATCH
if ! [ -d core-v-cores/cva6 ]; then
git clone --recursive $CVA6_REPO -b $CVA6_BRANCH core-v-cores/cva6
pushd core-v-cores/cva6
git checkout $CVA6_HASH
echo -n "Using CVA6 commit "; git describe --always HEAD
if [[ -n "$CVA6_PATCH" && -f "$CVA6_PATCH" ]]; then
git apply "$CVA6_PATCH"
fi
popd
fi
# install Spike # install Spike
if [ -z "$SPIKE_ROOT" ]; then if [ -z "$SPIKE_ROOT" ]; then
export SPIKE_ROOT=$TOP/spike/ export SPIKE_ROOT=$TOP/spike/
fi fi
source cva6/regress/install-spike.sh source verif/regress/install-spike.sh

10
verif/regress/install-riscv-arch-test.sh
View file

@ -8,7 +8,7 @@
# Original Author: Jean-Roch COULON - Thales # Original Author: Jean-Roch COULON - Thales
# riscv-arch-tests uses definition of RVMODEL_HALT provided by Spike. # riscv-arch-tests uses definition of RVMODEL_HALT provided by Spike.
. cva6/regress/install-spike.sh . verif/regress/install-spike.sh
if [ ! -d $SPIKE_SRC_DIR/arch_test_target ]; then if [ ! -d $SPIKE_SRC_DIR/arch_test_target ]; then
echo "*** Variable SPIKE_SRC_DIR must point to a source-based installation of Spike." echo "*** Variable SPIKE_SRC_DIR must point to a source-based installation of Spike."
return 1 return 1
@ -24,10 +24,10 @@ echo "Branch:" $ARCH_TEST_BRANCH
echo "Hash: " $ARCH_TEST_HASH echo "Hash: " $ARCH_TEST_HASH
mkdir -p cva6/tests mkdir -p verif/tests
if ! [ -d cva6/tests/riscv-arch-test ]; then if ! [ -d verif/tests/riscv-arch-test ]; then
git clone $ARCH_TEST_REPO -b $ARCH_TEST_BRANCH cva6/tests/riscv-arch-test git clone $ARCH_TEST_REPO -b $ARCH_TEST_BRANCH verif/tests/riscv-arch-test
cd cva6/tests/riscv-arch-test; git checkout $ARCH_TEST_HASH; cd verif/tests/riscv-arch-test; git checkout $ARCH_TEST_HASH;
# Copy Spike definitions to the corresponding riscv-target subdirectory. # Copy Spike definitions to the corresponding riscv-target subdirectory.
cp -rpa $SPIKE_SRC_DIR/arch_test_target riscv-target cp -rpa $SPIKE_SRC_DIR/arch_test_target riscv-target
cd - cd -

10
verif/regress/install-riscv-compliance.sh
View file

@ -11,17 +11,17 @@ if ! [ -n "$COMPLIANCE_REPO" ]; then
COMPLIANCE_REPO="https://github.com/riscv-non-isa/riscv-arch-test.git" COMPLIANCE_REPO="https://github.com/riscv-non-isa/riscv-arch-test.git"
COMPLIANCE_BRANCH="main" COMPLIANCE_BRANCH="main"
COMPLIANCE_HASH="220e78542da4510e40eac31e31fdd4e77cdae437" COMPLIANCE_HASH="220e78542da4510e40eac31e31fdd4e77cdae437"
COMPLIANCE_PATCH="../../../cva6/regress/riscv-compliance.patch" COMPLIANCE_PATCH="../../../verif/regress/riscv-compliance.patch"
fi fi
echo "Repo: " $COMPLIANCE_REPO echo "Repo: " $COMPLIANCE_REPO
echo "Branch:" $COMPLIANCE_BRANCH echo "Branch:" $COMPLIANCE_BRANCH
echo "Hash: " $COMPLIANCE_HASH echo "Hash: " $COMPLIANCE_HASH
echo "Patch: " $COMPLIANCE_PATCH echo "Patch: " $COMPLIANCE_PATCH
mkdir -p cva6/tests mkdir -p verif/tests
if ! [ -d cva6/tests/riscv-compliance ]; then if ! [ -d verif/tests/riscv-compliance ]; then
git clone $COMPLIANCE_REPO -b $COMPLIANCE_BRANCH cva6/tests/riscv-compliance git clone $COMPLIANCE_REPO -b $COMPLIANCE_BRANCH verif/tests/riscv-compliance
cd cva6/tests/riscv-compliance; git checkout $COMPLIANCE_HASH; cd verif/tests/riscv-compliance; git checkout $COMPLIANCE_HASH;
if [[ -n "$COMPLIANCE_PATCH" && -f "$COMPLIANCE_PATCH" ]]; then if [[ -n "$COMPLIANCE_PATCH" && -f "$COMPLIANCE_PATCH" ]]; then
echo "Applying patch $COMPLIANCE_PATCH in $PWD..." echo "Applying patch $COMPLIANCE_PATCH in $PWD..."
git apply "$COMPLIANCE_PATCH" git apply "$COMPLIANCE_PATCH"

16
verif/regress/install-riscv-dv.sh
View file

@ -16,9 +16,9 @@ if [ -z "$RISCV_OBJCOPY" ]; then
export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv-none-elf-objcopy" export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv-none-elf-objcopy"
fi fi
export SPIKE_PATH=$SPIKE_ROOT/bin export SPIKE_PATH=$SPIKE_ROOT/bin
export RTL_PATH=$ROOT_PROJECT/core-v-cores/cva6 export RTL_PATH=$ROOT_PROJECT/
export TB_PATH=$ROOT_PROJECT/cva6/tb/core export TB_PATH=$ROOT_PROJECT/verif/tb/core
export TESTS_PATH=$ROOT_PROJECT/cva6/tests export TESTS_PATH=$ROOT_PROJECT/verif/tests
if [ -z "$DV_REPO" ]; then if [ -z "$DV_REPO" ]; then
export DV_REPO="https://github.com/google/riscv-dv.git" export DV_REPO="https://github.com/google/riscv-dv.git"
@ -31,15 +31,15 @@ echo "Branch:" $DV_BRANCH
echo "Hash: " $DV_HASH echo "Hash: " $DV_HASH
echo "Patch: " $DV_PATCH echo "Patch: " $DV_PATCH
mkdir -p cva6/sim mkdir -p verif/sim
if ! [ -d cva6/sim/dv ]; then if ! [ -d verif/sim/dv ]; then
git clone $DV_REPO -b $DV_BRANCH cva6/sim/dv git clone $DV_REPO -b $DV_BRANCH verif/sim/dv
cd cva6/sim/dv; git checkout $DV_HASH; cd verif/sim/dv; git checkout $DV_HASH;
if [[ -n "$DV_PATCH" && -f "$DV_PATCH" ]]; then if [[ -n "$DV_PATCH" && -f "$DV_PATCH" ]]; then
git apply "$DV_PATCH" git apply "$DV_PATCH"
fi fi
cd - cd -
# install riscv-dv dependencies # install riscv-dv dependencies
cd cva6/sim/dv; pip3 install -r requirements.txt; cd - cd verif/sim/dv; pip3 install -r requirements.txt; cd -
fi fi

10
verif/regress/install-riscv-tests.sh
View file

@ -16,11 +16,11 @@ echo "Repo: " $TESTS_REPO
echo "Branch:" $TESTS_BRANCH echo "Branch:" $TESTS_BRANCH
echo "Hash: " $TESTS_HASH echo "Hash: " $TESTS_HASH
mkdir -p cva6/tests mkdir -p verif/tests
if ! [ -d cva6/tests/riscv-tests ]; then if ! [ -d verif/tests/riscv-tests ]; then
git clone $TESTS_REPO -b $TESTS_BRANCH cva6/tests/riscv-tests git clone $TESTS_REPO -b $TESTS_BRANCH verif/tests/riscv-tests
cd cva6/tests/riscv-tests; git checkout $TESTS_HASH; cd verif/tests/riscv-tests; git checkout $TESTS_HASH;
git submodule update --init --recursive git submodule update --init --recursive
git apply --directory=env ../../../cva6/regress/riscv-tests-env.patch git apply --directory=env ../../../verif/regress/riscv-tests-env.patch
cd - cd -
fi fi

2
verif/regress/install-verilator.sh
View file

@ -21,7 +21,7 @@ VERILATOR_REPO="https://github.com/verilator/verilator.git"
VERILATOR_BRANCH="master" VERILATOR_BRANCH="master"
# Use the release tag instead of a full SHA1 hash. # Use the release tag instead of a full SHA1 hash.
VERILATOR_HASH="v5.008" VERILATOR_HASH="v5.008"
VERILATOR_PATCH="$TOP/../cva6/regress/verilator-v5.patch" VERILATOR_PATCH="$TOP/../verif/regress/verilator-v5.patch"
# Unset historical variable VERILATOR_ROOT as it collides with the build process. # Unset historical variable VERILATOR_ROOT as it collides with the build process.
if [ -n "$VERILATOR_ROOT" ]; then if [ -n "$VERILATOR_ROOT" ]; then

12
verif/regress/iss-tests.sh
View file

@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-compliance.sh source verif/regress/install-riscv-compliance.sh
if ! [ -n "$DV_SIMULATORS" ]; then if ! [ -n "$DV_SIMULATORS" ]; then
echo "Error DV_SIMULATORS variable undefined" echo "Error DV_SIMULATORS variable undefined"
@ -25,9 +25,9 @@ if ! [ -n "$DV_TARGET" ]; then
echo "Error DV_TARGET variable undefined" echo "Error DV_TARGET variable undefined"
fi fi
cd cva6/sim/ cd verif/sim/
python3 cva6.py --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --test rv32ui-addi python3 cva6.py --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --test rv32ui-addi
make -C ../../core-v-cores/cva6 clean make clean
make clean_all make -C verif/sim clean_all
cd - cd -

18
verif/regress/issue-tests.sh
View file

@ -14,21 +14,21 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-compliance.sh source verif/regress/install-riscv-compliance.sh
source ./cva6/regress/install-riscv-tests.sh source verif/regress/install-riscv-tests.sh
if ! [ -n "$DV_SIMULATORS" ]; then if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness,spike DV_SIMULATORS=veri-testharness,spike
fi fi
cd cva6/sim/ cd verif/sim/
python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg-commits-rv64 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg-commits-rv64 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
make -C ../../core-v-cores/cva6 clean make clean
make clean_all make -C verif/sim clean_all
python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg-commits-rv32 --iss_yaml cva6.yaml --target cv32a6_imafc_sv32 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg-commits-rv32 --iss_yaml cva6.yaml --target cv32a6_imafc_sv32 --iss=$DV_SIMULATORS $DV_OPTS
make -C ../../core-v-cores/cva6 clean make clean
make clean_all make -C verif/sim clean_all
cd - cd -

6
verif/regress/linux.sh
View file

@ -21,14 +21,14 @@ if ! [ -n "$BBL_ROOT" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
if ! [ -n "$DV_SIMULATORS" ]; then if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness DV_SIMULATORS=veri-testharness
fi fi
cd cva6/sim cd verif/sim
cp $BBL_ROOT/bbl bbl.o cp $BBL_ROOT/bbl bbl.o
python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --elf_tests bbl.o\ python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --elf_tests bbl.o\
--issrun_opts="+time_out=40000000 +debug_disable=1" --isspostrun_opts="ffffffe0005e5cd4" --issrun_opts="+time_out=40000000 +debug_disable=1" --isspostrun_opts="ffffffe0005e5cd4"

8
verif/regress/smoke-gen_tests.sh
View file

@ -14,9 +14,9 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-isa-sim.sh source verif/regress/install-riscv-isa-sim.sh
if ! [ -n "$DV_TARGET" ]; then if ! [ -n "$DV_TARGET" ]; then
DV_TARGET=cv32a60x DV_TARGET=cv32a60x
@ -26,7 +26,7 @@ if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=vcs-uvm,spike DV_SIMULATORS=vcs-uvm,spike
fi fi
cd cva6/sim/ cd verif/sim/
cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300

16
verif/regress/smoke-tests.sh
View file

@ -14,18 +14,18 @@ if ! [ -n "$RISCV" ]; then
fi fi
# install the required tools # install the required tools
source ./cva6/regress/install-cva6.sh source ./verif/regress/install-cva6.sh
source ./cva6/regress/install-riscv-dv.sh source ./verif/regress/install-riscv-dv.sh
source ./cva6/regress/install-riscv-compliance.sh source ./verif/regress/install-riscv-compliance.sh
source ./cva6/regress/install-riscv-tests.sh source ./verif/regress/install-riscv-tests.sh
source ./cva6/regress/install-riscv-arch-test.sh source ./verif/regress/install-riscv-arch-test.sh
if ! [ -n "$DV_SIMULATORS" ]; then if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=vcs-testharness,spike DV_SIMULATORS=vcs-testharness,spike
fi fi
cd cva6/sim/ cd verif/sim/
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
@ -33,14 +33,14 @@ python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.
python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\ python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\
--gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld"
make -C ../../core-v-cores/cva6 clean make -C ../.. clean
make clean_all make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../tests/custom/common/test.ld\ python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../tests/custom/common/test.ld\
--gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common" --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common"
make -C ../../core-v-cores/cva6 clean make -C ../.. clean
make clean_all make clean_all
cd - cd -

69
verif/sim/Makefile
View file

@ -12,9 +12,8 @@ root-dir := $(dir $(mkfile_path))
ifndef CVA6_REPO_DIR ifndef CVA6_REPO_DIR
$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...) $(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...)
export CVA6_REPO_DIR = $(abspath $(root-dir)../../core-v-cores/cva6/) export CVA6_REPO_DIR = $(abspath $(root-dir)../..)
export CVA6_TB_DIR = $(root-dir)/../tb/core export CVA6_TB_DIR = $(root-dir)/../tb/core
export CORE_V_VERIF = $(root-dir)/../..
endif endif
ifndef TARGET_CFG ifndef TARGET_CFG
export TARGET_CFG = $(target) export TARGET_CFG = $(target)
@ -144,65 +143,65 @@ questa-testharness:
# UVM specific commands, variables # UVM specific commands, variables
############################################################################### ###############################################################################
ALL_VCS_FLAGS = $(if $(VERDI), -kdb -debug_access+all -lca,) -sverilog -full64 -timescale=1ns/1ns ALL_VCS_FLAGS = $(if $(VERDI), -kdb -debug_access+all -lca,) -sverilog -full64 -timescale=1ns/1ns
VCS_WORK_DIR = $(CORE_V_VERIF)/cva6/sim/vcs_results/default/vcs.d VCS_WORK_DIR = $(CVA6_REPO_DIR)/verif/sim/vcs_results/default/vcs.d
SIMV = $(VCS_WORK_DIR)/simv SIMV = $(VCS_WORK_DIR)/simv
export CVA6_UVMT_DIR = $(CORE_V_VERIF)/cva6/tb/uvmt export CVA6_UVMT_DIR = $(CVA6_REPO_DIR)/verif/tb/uvmt
export CVA6_UVMT_PATH = $(CORE_V_VERIF)/cva6/tb/uvmt export CVA6_UVMT_PATH = $(CVA6_REPO_DIR)/verif/tb/uvmt
export CVA6_UVME_PATH = $(CORE_V_VERIF)/cva6/env/uvme export CVA6_UVME_PATH = $(CVA6_REPO_DIR)/verif/env/uvme
export CV_CORE_LC = cva6 export CV_CORE_LC = cva6
export CV_CORE_UC = CVA6 export CV_CORE_UC = CVA6
export DV_UVMT_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/tb/uvmt export DV_UVMT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/tb/uvmt
export DV_UVME_PATH = $(CORE_V_VERIF)/$(CV_CORE_LC)/env/uvme export DV_UVME_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/env/uvme
export DV_UVML_HRTBT_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_hrtbt export DV_UVML_HRTBT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_hrtbt
export DV_UVMA_CORE_CNTRL_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_core_cntrl export DV_UVMA_CORE_CNTRL_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl
export DV_UVMA_RVFI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_rvfi export DV_UVMA_RVFI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi
export DV_UVMA_ISACOV_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_isacov export DV_UVMA_ISACOV_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_isacov
export DV_UVMA_CLKNRST_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_clknrst export DV_UVMA_CLKNRST_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_clknrst
export DV_UVMA_CVXIF_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_cvxif export DV_UVMA_CVXIF_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_cvxif
export DV_UVMA_AXI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_axi export DV_UVMA_AXI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_axi
export DV_UVMA_INTERRUPT_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_interrupt export DV_UVMA_INTERRUPT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_interrupt
export DV_UVMA_DEBUG_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_debug export DV_UVMA_DEBUG_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_debug
export DV_UVMA_OBI_PATH = $(CORE_V_VERIF)/lib/uvm_agents/uvma_obi export DV_UVMA_OBI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_obi
export DV_UVML_TRN_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_trn export DV_UVML_TRN_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_trn
export DV_UVML_MEM_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_mem export DV_UVML_MEM_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_mem
export DV_UVML_LOGS_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_logs export DV_UVML_LOGS_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_logs
export DV_UVML_SB_PATH = $(CORE_V_VERIF)/lib/uvm_libs/uvml_sb export DV_UVML_SB_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_sb
export CV_CORE_PKG = $(CORE_V_VERIF)/core-v-cores/$(CV_CORE_LC) export CV_CORE_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/core-v-cores/$(CV_CORE_LC)
export DESIGN_RTL_DIR = $(CV_CORE_PKG)/rtl export DESIGN_RTL_DIR = $(CV_CORE_PKG)/rtl
DPI_DASM_PKG = $(CORE_V_VERIF)/lib/dpi_dasm DPI_DASM_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/dpi_dasm
DPI_DASM_SPIKE_PKG = $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/dpi_dasm_spike DPI_DASM_SPIKE_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/vendor_lib/dpi_dasm_spike
export DPI_DASM_ROOT = $(DPI_DASM_PKG) export DPI_DASM_ROOT = $(DPI_DASM_PKG)
export DPI_DASM_SPIKE_ROOT = $(DPI_DASM_SPIKE_PKG) export DPI_DASM_SPIKE_ROOT = $(DPI_DASM_SPIKE_PKG)
export TBSRC_HOME = $(CORE_V_VERIF)/cva6/tb export TBSRC_HOME = $(CVA6_REPO_DIR)/verif/tb
export DV_OVPM_HOME = $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/imperas export DV_OVPM_HOME = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/vendor_lib/imperas
export DV_OVPM_MODEL = $(DV_OVPM_HOME)/riscv_$(CV_CORE_UC)_OVPsim export DV_OVPM_MODEL = $(DV_OVPM_HOME)/riscv_$(CV_CORE_UC)_OVPsim
export DV_OVPM_DESIGN = $(DV_OVPM_HOME)/design export DV_OVPM_DESIGN = $(DV_OVPM_HOME)/design
ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \ ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \
$(VCS_HOME)/etc/uvm/src/uvm_pkg.sv +UVM_VERBOSITY=UVM_MEDIUM -ntb_opts uvm-1.2 -timescale=1ns/1ps \ $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv +UVM_VERBOSITY=UVM_MEDIUM -ntb_opts uvm-1.2 -timescale=1ns/1ps \
-assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \ -assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \
+incdir+$(CORE_V_VERIF)/$(CV_CORE_LC)/env/uvme +incdir+$(CORE_V_VERIF)/$(CV_CORE_LC)/tb/uvmt \ +incdir+$(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/env/uvme +incdir+$(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/tb/uvmt \
$(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon)) $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon))
ALL_SIMV_UVM_FLAGS = -licwait 20 $(issrun_opts) \ ALL_SIMV_UVM_FLAGS = -licwait 20 $(issrun_opts) \
-sv_lib $(CORE_V_VERIF)/lib/dpi_dasm/lib/Linux64/libdpi_dasm +signature=I-ADD-01.signature_output \ -sv_lib $(CVA6_REPO_DIR)/verif/core-v-verif/lib/dpi_dasm/lib/Linux64/libdpi_dasm +signature=I-ADD-01.signature_output \
+UVM_TESTNAME=uvmt_cva6_firmware_test_c +UVM_TESTNAME=uvmt_cva6_firmware_test_c
ifneq ($(DEBUG),) # If RTL DEBUG support requested ifneq ($(DEBUG),) # If RTL DEBUG support requested
ifneq ($(VERDI),) # If VERDI interactive mode requested, use GUI and do not run simulation ifneq ($(VERDI),) # If VERDI interactive mode requested, use GUI and do not run simulation
ALL_SIMV_UVM_FLAGS += \ ALL_SIMV_UVM_FLAGS += \
-gui -do $(CORE_V_VERIF)/cva6/sim/init_uvm.do -gui -do $(CVA6_REPO_DIR)/verif/sim/init_uvm.do
else # else: *not* VERDI, use CLI mode and appropriate batch dump controls else # else: *not* VERDI, use CLI mode and appropriate batch dump controls
ifneq ($(TRACE_FAST),) # TRACE_FAST: Generate waveform trace in VPD format ifneq ($(TRACE_FAST),) # TRACE_FAST: Generate waveform trace in VPD format
ALL_SIMV_UVM_FLAGS += \ ALL_SIMV_UVM_FLAGS += \
-ucli -do $(CORE_V_VERIF)/cva6/sim/init_run_uvm_vpd.do -ucli -do $(CVA6_REPO_DIR)/verif/sim/init_run_uvm_vpd.do
SIMV_TRACE_EXTN = vpd SIMV_TRACE_EXTN = vpd
endif endif
ifneq ($(TRACE_COMPACT),) # TRACE_COMPACT: Generate waveform trace in FSDB format ifneq ($(TRACE_COMPACT),) # TRACE_COMPACT: Generate waveform trace in FSDB format
ALL_SIMV_UVM_FLAGS += \ ALL_SIMV_UVM_FLAGS += \
-ucli -do $(CORE_V_VERIF)/cva6/sim/init_run_uvm_fsdb.do -ucli -do $(CVA6_REPO_DIR)/verif/sim/init_run_uvm_fsdb.do
SIMV_TRACE_EXTN = fsdb SIMV_TRACE_EXTN = fsdb
endif endif
endif endif
@ -234,9 +233,9 @@ vcs_uvm_run:
+tohost_addr=$(shell $$RISCV/bin/riscv-none-elf-nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \ +tohost_addr=$(shell $$RISCV/bin/riscv-none-elf-nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
-sv_lib $(dpi-library)/ariane_dpi \ -sv_lib $(dpi-library)/ariane_dpi \
$(cov-run-opt) $(issrun_opts) && \ $(cov-run-opt) $(issrun_opts) && \
mv $(VCS_WORK_DIR)/trace_rvfi_hart_00.dasm $(CORE_V_VERIF)/cva6/sim/ && \ mv $(VCS_WORK_DIR)/trace_rvfi_hart_00.dasm $(CVA6_REPO_DIR)/verif/sim/ && \
{ [ -z "`ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)`" ] || \ { [ -z "`ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)`" ] || \
for i in `ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)` ; do mv $$i $(CORE_V_VERIF)/cva6/sim/`basename $$i` ; done || \ for i in `ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)` ; do mv $$i $(CVA6_REPO_DIR)/verif/sim/`basename $$i` ; done || \
true ; } true ; }
vcs-uvm: vcs-uvm:
@ -252,7 +251,7 @@ generate_cov_dash:
vcs_clean_all: vcs_clean_all:
@echo "[VCS] Cleanup (entire vcs_work dir)" @echo "[VCS] Cleanup (entire vcs_work dir)"
rm -rf $(CORE_V_VERIF)/cva6/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart rm -rf $(CVA6_REPO_DIR)/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart
############################################################################### ###############################################################################
# Common targets and rules # Common targets and rules

4
verif/sim/cva6.py
View file

@ -936,7 +936,7 @@ def load_config(args, cwd):
args.isa = "rv64imc" args.isa = "rv64imc"
elif args.target == "hwconfig": elif args.target == "hwconfig":
current_path = os.getcwd() current_path = os.getcwd()
os.chdir(os.getcwd()+"/../../core-v-cores/cva6") os.chdir(os.getcwd()+"/../../")
[args.isa,args.mabi, args.target, args.hwconfig_opts] = generate_config(args.hwconfig_opts.split()) [args.isa,args.mabi, args.target, args.hwconfig_opts] = generate_config(args.hwconfig_opts.split())
os.chdir(current_path) os.chdir(current_path)
else: else:
@ -1219,7 +1219,7 @@ def main():
sys.exit(130) sys.exit(130)
if __name__ == "__main__": if __name__ == "__main__":
sys.path.append(os.getcwd()+"/../../core-v-cores/cva6/util") sys.path.append(os.getcwd()+"/../../util")
from config_pkg_generator import * from config_pkg_generator import *
main() main()

2
verif/tb/core/Makefile
View file

@ -27,7 +27,7 @@ root-dir := $(dir $(mkfile_path))
ifndef CVA6_REPO_DIR ifndef CVA6_REPO_DIR
$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...) $(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...)
export CVA6_REPO_DIR = $(abspath $(root-dir)../../../core-v-cores/cva6/) export CVA6_REPO_DIR = $(abspath $(root-dir)../../../)
export CVA6_TB_DIR = $(root-dir) export CVA6_TB_DIR = $(root-dir)
endif endif