Updated README with BTB information

btb.sv

@@ -23,12 +23,12 @@ module btb #(
     parameter int BITS_SATURATION_COUNTER = 2
     )
     (
-    input  logic            clk_i,    // Clock
-    input  logic            rst_ni,   // Asynchronous reset active low
-    input  logic            flush_i,  // flush the btb
+    input  logic            clk_i,                     // Clock
+    input  logic            rst_ni,                    // Asynchronous reset active low
+    input  logic            flush_i,                   // flush the btb
 
-    input  logic [63:0]     vpc_i,
-    input  misspredict      misspredict_i,
+    input  logic [63:0]     vpc_i,                     // virtual PC from IF stage
+    input  misspredict      misspredict_i,             // a miss-predict happened -> update data structure
 
     output logic            is_branch_o,               // instruction at vpc_i is a branch
     output logic            predict_taken_o,           // the branch is taken
@@ -89,12 +89,15 @@ module btb #(
     // sequential process
     always_ff @(posedge clk_i or negedge rst_ni) begin
         if(~rst_ni) begin
-             btb_q <= '{default: 0};
+            // TODO: think about the reset value
+            btb_q <= '{default: 0};
         end else begin
             // evict all entries
             if (flush_i) begin
-                for (int i = 0; i < NR_ENTRIES; i++)
-                    btb_q[i].valid <=  1'b0;
+                for (int i = 0; i < NR_ENTRIES; i++) begin
+                    btb_q[i].valid              <=  1'b0;
+                    btb_q[i].saturation_counter <= '{default: 0};
+                end
             end else begin
                 btb_q <=  btb_n;
             end

docs/block_details.md

@@ -20,16 +20,20 @@ The next PC can originate from the following sources:
 5.  Environment Call (`ecall) instruction. Read the CSRs to figure out where to jump.
 6.  Miss-predict: This triggers a pipeline flush and the PC Gen stage starts fetching from there.
 
-### ITLB
+### BTB and BHT
+
+Currently all branch prediction data structures reside in a single register like file. It is indexed with the appropriate number of bits from the PC and contains information about the predicted target address as well as the outcome of a two (actually configurable) saturation counter. The prediction result is used in the subsequent stage to jump (or not).
+
+For a future version a more accurate predictor might be necessary (gshare, tournament,...).
+
 
 ## Instruction Fetch (IF)
 
 In the IF stage we already know the physical PC. The request of the instruction is on its way to the instruction memory. We know the result of the BHT and can set the next PC accordingly. At the end of this stage the instruction PC is passed on to the ID stage. Retrieved instructions are stored in an instruction queue.
 It is possible that a TLB or cache miss occurred. If this is the case the IF stage signals that it is not ready. The pipeline in the direction of the ID stage will empty itself.
 
-### BTB
+### ITLB
 
-### BHT
 
 ### Instruction Queue