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Add System Verilog FPU (#163)

Browse source 
* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals.

* saving...

* ⬆️ Updates for new FPU

* Add sv fpu to FPGA flow

* Use multi-threading capabilities of verilator

- Deactivate non-standard floating point arguments
- Make multi-threading conditional on the availability of verilator 4

* Remove DPI threadsafety

* Reduce FPGA clock frequency

- Remove couple of -v- tests to reduce test-time

* Fix documentation and fpga flow

- Fix cycle time to accommodate FPU
- Fix FPGA constraints

* Change UART frequency
This commit is contained in:
Florian Zaruba 2019-02-19 14:04:05 +01:00
parent 90cebe6e70
commit b1bdc0c02c
29 changed files with 1699 additions and 1657 deletions
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4
CHANGELOG.md
View file

@ -11,6 +11,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
### Changed
- Rerouted the JTAG from PMOD to second channel of FTDI 2232 chip on Genesys 2 board
- Increase available RAM size on Genesys II board to 1 GiB
- Fixed problem which decoded compressed hints as illegal instructions
- Reduce clock frequency of FPGA to 30 MHz to accomodate FPU
- Official support for floating point unit
### 4.0.0

271
Makefile
View file

@ -32,6 +32,11 @@ elf-bin ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
root-dir := $(dir $(mkfile_path))
support_verilator_4 := $(shell (verilator --version | grep '4\.') &> /dev/null; echo $$?)
ifeq ($(support_verilator_4), 0)
verilator_threads := 2
endif
ifndef RISCV
$(error RISCV not set - please point your RISCV variable to your RISCV installation)
endif
@ -39,33 +44,30 @@ endif
# Sources
# Package files -> compile first
ariane_pkg := include/riscv_pkg.sv \
src/debug/dm_pkg.sv \
include/ariane_pkg.sv \
include/std_cache_pkg.sv \
include/serpent_cache_pkg.sv \
src/axi/src/axi_pkg.sv \
src/register_interface/src/reg_intf.sv \
include/axi_intf.sv \
tb/ariane_soc_pkg.sv \
include/ariane_axi_pkg.sv \
src/fpu/src/pkg/fpnew_pkg.vhd \
src/fpu/src/pkg/fpnew_fmts_pkg.vhd \
src/fpu/src/pkg/fpnew_comps_pkg.vhd \
src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
src/fpu/src/pkg/fpnew_pkg_constants.vhd
src/debug/dm_pkg.sv \
include/ariane_pkg.sv \
include/std_cache_pkg.sv \
include/serpent_cache_pkg.sv \
src/axi/src/axi_pkg.sv \
src/register_interface/src/reg_intf.sv \
include/axi_intf.sv \
tb/ariane_soc_pkg.sv \
include/ariane_axi_pkg.sv \
src/fpu/src/fpnew_pkg.sv \
src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
# utility modules
util := $(wildcard src/util/*.svh) \
src/util/instruction_tracer_pkg.sv \
src/util/instruction_tracer_if.sv \
src/tech_cells_generic/src/cluster_clock_gating.sv \
tb/common/mock_uart.sv \
src/util/sram.sv
src/util/instruction_tracer_pkg.sv \
src/util/instruction_tracer_if.sv \
src/tech_cells_generic/src/cluster_clock_gating.sv \
tb/common/mock_uart.sv \
src/util/sram.sv
util := $(addprefix $(root-dir), $(util))
# Test packages
test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
$(wildcard tb/test/*/*_pkg.sv*)
$(wildcard tb/test/*/*_pkg.sv*)
# DPI
dpi := $(patsubst tb/dpi/%.cc,${dpi-library}/%.o,$(wildcard tb/dpi/*.cc))
dpi_hdr := $(wildcard tb/dpi/*.h)
@ -76,66 +78,63 @@ CFLAGS := -I$(QUESTASIM_HOME)/include \
# this list contains the standalone components
src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
$(wildcard src/fpu/src/utils/*.vhd) \
$(wildcard src/fpu/src/ops/*.vhd) \
$(wildcard src/fpu/src/subunits/*.vhd) \
$(filter-out src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \
$(wildcard src/fpu_div_sqrt_mvp/hdl/*.sv)) \
$(wildcard src/frontend/*.sv) \
$(filter-out src/cache_subsystem/std_no_dcache.sv, \
$(wildcard src/cache_subsystem/*.sv)) \
$(wildcard bootrom/*.sv) \
$(wildcard src/clint/*.sv) \
$(wildcard fpga/src/axi2apb/src/*.sv) \
$(wildcard fpga/src/axi_slice/src/*.sv) \
$(wildcard src/plic/*.sv) \
$(wildcard src/axi_node/src/*.sv) \
$(wildcard src/axi_mem_if/src/*.sv) \
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
$(wildcard src/debug/debug_rom/*.sv) \
src/register_interface/src/apb_to_reg.sv \
src/axi/src/axi_multicut.sv \
src/fpu/src/fpnew.vhd \
src/fpu/src/fpnew_top.vhd \
src/common_cells/src/deprecated/generic_fifo.sv \
src/common_cells/src/deprecated/pulp_sync.sv \
src/common_cells/src/deprecated/find_first_one.sv \
src/common_cells/src/rstgen_bypass.sv \
src/common_cells/src/rstgen.sv \
src/common_cells/src/stream_mux.sv \
src/common_cells/src/stream_demux.sv \
src/common_cells/src/stream_arbiter.sv \
src/util/axi_master_connect.sv \
src/util/axi_slave_connect.sv \
src/util/axi_master_connect_rev.sv \
src/util/axi_slave_connect_rev.sv \
src/axi/src/axi_cut.sv \
src/axi/src/axi_join.sv \
src/axi/src/axi_delayer.sv \
src/axi/src/axi_to_axi_lite.sv \
src/fpga-support/rtl/SyncSpRamBeNx64.sv \
src/common_cells/src/sync.sv \
src/common_cells/src/cdc_2phase.sv \
src/common_cells/src/spill_register.sv \
src/common_cells/src/sync_wedge.sv \
src/common_cells/src/edge_detect.sv \
src/common_cells/src/fifo_v3.sv \
src/common_cells/src/fifo_v2.sv \
src/common_cells/src/fifo_v1.sv \
src/common_cells/src/lzc.sv \
src/common_cells/src/rrarbiter.sv \
src/common_cells/src/ready_valid_delay.sv \
src/common_cells/src/lfsr_8bit.sv \
src/common_cells/src/lfsr_16bit.sv \
src/common_cells/src/counter.sv \
src/common_cells/src/pipe_reg_simple.sv \
src/tech_cells_generic/src/cluster_clock_inverter.sv \
src/tech_cells_generic/src/pulp_clock_mux2.sv \
tb/ariane_testharness.sv \
tb/ariane_peripherals.sv \
tb/common/uart.sv \
tb/common/SimDTM.sv \
tb/common/SimJTAG.sv
$(filter-out src/fpu/src/fpnew_pkg.sv, $(wildcard src/fpu/src/*.sv)) \
$(filter-out src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \
$(wildcard src/fpu_div_sqrt_mvp/hdl/*.sv)) \
$(wildcard src/frontend/*.sv) \
$(filter-out src/cache_subsystem/std_no_dcache.sv, \
$(wildcard src/cache_subsystem/*.sv)) \
$(wildcard bootrom/*.sv) \
$(wildcard src/clint/*.sv) \
$(wildcard fpga/src/axi2apb/src/*.sv) \
$(wildcard fpga/src/axi_slice/src/*.sv) \
$(wildcard src/plic/*.sv) \
$(wildcard src/axi_node/src/*.sv) \
$(wildcard src/axi_mem_if/src/*.sv) \
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
$(wildcard src/debug/debug_rom/*.sv) \
src/register_interface/src/apb_to_reg.sv \
src/axi/src/axi_multicut.sv \
src/common_cells/src/deprecated/generic_fifo.sv \
src/common_cells/src/deprecated/pulp_sync.sv \
src/common_cells/src/deprecated/find_first_one.sv \
src/common_cells/src/rstgen_bypass.sv \
src/common_cells/src/rstgen.sv \
src/common_cells/src/stream_mux.sv \
src/common_cells/src/stream_demux.sv \
src/common_cells/src/stream_arbiter.sv \
src/common_cells/src/stream_arbiter_flushable.sv \
src/util/axi_master_connect.sv \
src/util/axi_slave_connect.sv \
src/util/axi_master_connect_rev.sv \
src/util/axi_slave_connect_rev.sv \
src/axi/src/axi_cut.sv \
src/axi/src/axi_join.sv \
src/axi/src/axi_delayer.sv \
src/axi/src/axi_to_axi_lite.sv \
src/fpga-support/rtl/SyncSpRamBeNx64.sv \
src/common_cells/src/sync.sv \
src/common_cells/src/cdc_2phase.sv \
src/common_cells/src/spill_register.sv \
src/common_cells/src/sync_wedge.sv \
src/common_cells/src/edge_detect.sv \
src/common_cells/src/fifo_v3.sv \
src/common_cells/src/fifo_v2.sv \
src/common_cells/src/fifo_v1.sv \
src/common_cells/src/lzc.sv \
src/common_cells/src/rrarbiter.sv \
src/common_cells/src/stream_delay.sv \
src/common_cells/src/lfsr_8bit.sv \
src/common_cells/src/lfsr_16bit.sv \
src/common_cells/src/counter.sv \
src/common_cells/src/shift_reg.sv \
src/tech_cells_generic/src/cluster_clock_inverter.sv \
src/tech_cells_generic/src/pulp_clock_mux2.sv \
tb/ariane_testharness.sv \
tb/ariane_peripherals.sv \
tb/common/uart.sv \
tb/common/SimDTM.sv \
tb/common/SimJTAG.sv
src := $(addprefix $(root-dir), $(src))
@ -154,14 +153,16 @@ riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
riscv-asm-tests-list := ci/riscv-asm-tests.list
riscv-amo-tests-list := ci/riscv-amo-tests.list
riscv-mul-tests-list := ci/riscv-mul-tests.list
riscv-fp-tests-list := ci/riscv-fp-tests.list
riscv-benchmarks-list := ci/riscv-benchmarks.list
riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-)
riscv-amo-tests := $(shell xargs printf '\n%s' < $(riscv-amo-tests-list) | cut -b 1-)
riscv-mul-tests := $(shell xargs printf '\n%s' < $(riscv-mul-tests-list) | cut -b 1-)
riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list) | cut -b 1-)
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
# Search here for include files (e.g.: non-standalone components)
incdir :=
incdir := src/common_cells/include/common_cells
# Compile and sim flags
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW
@ -180,27 +181,27 @@ riscv-torture-bin := java -jar sbt-launch.jar
# if defined, calls the questa targets in batch mode
ifdef batch-mode
questa-flags += -c
questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
questa-cmd += -do " log -r /*; run -all;"
questa-flags += -c
questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
questa-cmd += -do " log -r /*; run -all;"
else
questa-cmd := -do " log -r /*; run -all;"
questa-cmd := -do " log -r /*; run -all;"
endif
# we want to preload the memories
ifdef preload
questa-cmd += +PRELOAD=$(preload)
elf-bin = none
# tandem verify with spike, this requires pre-loading
ifdef tandem
compile_flag += +define+TANDEM
questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
endif
questa-cmd += +PRELOAD=$(preload)
elf-bin = none
# tandem verify with spike, this requires pre-loading
ifdef tandem
compile_flag += +define+TANDEM
questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
endif
endif
# remote bitbang is enabled
ifdef rbb
questa-cmd += +jtag_rbb_enable=1
questa-cmd += +jtag_rbb_enable=1
else
questa-cmd += +jtag_rbb_enable=0
questa-cmd += +jtag_rbb_enable=0
endif
# Build the TB and module using QuestaSim
@ -211,11 +212,11 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ari
# src files
$(library)/.build-srcs: $(util) $(library)
vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
touch $(library)/.build-srcs
@ -259,8 +260,13 @@ $(riscv-amo-tests): build
$(riscv-mul-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-mul-tests-$@.log
$(riscv-fp-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-fp-tests-$@.log
$(riscv-benchmarks): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
@ -277,6 +283,9 @@ run-amo-tests: $(riscv-amo-tests)
run-mul-tests: $(riscv-mul-tests)
$(MAKE) check-mul-tests
run-fp-tests: $(riscv-fp-tests)
$(MAKE) check-fp-tests
check-asm-tests:
ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
@ -286,6 +295,9 @@ check-amo-tests:
check-mul-tests:
ci/check-tests.sh tmp/riscv-mul-tests- $(shell wc -l $(riscv-mul-tests-list) | awk -F " " '{ print $1 }')
check-fp-tests:
ci/check-tests.sh tmp/riscv-fp-tests- $(shell wc -l $(riscv-fp-tests-list) | awk -F " " '{ print $1 }')
# can use -jX to run ci tests in parallel using X processes
run-benchmarks: $(riscv-benchmarks)
$(MAKE) check-benchmarks
@ -294,34 +306,36 @@ check-benchmarks:
ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }')
# verilator-specific
verilate_command := $(verilator) \
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
+define+$(defines) \
src/util/sram.sv \
+incdir+src/axi_node \
--unroll-count 256 \
-Werror-PINMISSING \
-Werror-IMPLICIT \
-Wno-fatal \
-Wno-PINCONNECTEMPTY \
-Wno-ASSIGNDLY \
-Wno-DECLFILENAME \
-Wno-UNOPTFLAT \
-Wno-UNUSED \
-Wno-style \
-Wno-lint \
$(if $(DEBUG),--trace-structs --trace,) \
-LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr" \
-CFLAGS "$(CFLAGS)" -Wall --cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--Mdir $(ver-library) -O3 \
--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \
tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc
verilate_command := $(verilator) \
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
+define+$(defines) \
src/util/sram.sv \
+incdir+src/axi_node \
$(if $(verilator_threads), --threads $(verilator_threads)) \
--unroll-count 256 \
-Werror-PINMISSING \
-Werror-IMPLICIT \
-Wno-fatal \
-Wno-PINCONNECTEMPTY \
-Wno-ASSIGNDLY \
-Wno-DECLFILENAME \
-Wno-UNUSED \
-Wno-UNOPTFLAT \
-Wno-style \
$(if $(PROFILE),--stats --stats-vars --profile-cfuncs,) \
-Wno-lint \
$(if $(DEBUG),--trace-structs --trace,) \
-LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr$(if $(PROFILE), -g -pg,)" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,)" -Wall --cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--Mdir $(ver-library) -O3 \
--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \
tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc
# User Verilator, at some point in the future this will be auto-generated
verilate:
@echo "[Verilator] Building Model"
@echo "[Verilator] Building Model$(if $(PROFILE), for Profiling,)"
$(verilate_command)
cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk
@ -337,10 +351,13 @@ $(addsuffix -verilator,$(riscv-amo-tests)): verilate
$(addsuffix -verilator,$(riscv-mul-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
$(addsuffix -verilator,$(riscv-fp-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
$(addsuffix -verilator,$(riscv-benchmarks)): verilate
$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(riscv-mul-tests))
run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(riscv-fp-tests)) $(addsuffix -verilator, $(riscv-fp-tests))
# split into two halfs for travis jobs (otherwise they will time out)
run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% ,$(riscv-asm-tests)))
@ -351,6 +368,8 @@ run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests))
run-mul-verilator: $(addsuffix -verilator, $(riscv-mul-tests))
run-fp-verilator: $(addsuffix -verilator, $(riscv-fp-tests))
run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
# torture-specific
@ -401,10 +420,10 @@ check-torture:
fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(util) $(uart_src)
@echo "[FPGA] Generate sources"
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(util)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(src)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(src)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
@echo "[FPGA] Generate Bitstream"
cd fpga && make BOARD="genesys2" XILINX_PART="xc7k325tffg900-2" XILINX_BOARD="digilentinc.com:genesys2:part0:1.1" CLK_PERIOD_NS="20"

6
README.md
View file

@ -15,7 +15,6 @@ Table of Contents
* [Table of Contents](#table-of-contents)
* [Getting Started](#getting-started)
* [Running User-Space Applications](#running-user-space-applications)
* [FPU Support](#fpu-support)
* [FPGA Emulation](#fpga-emulation)
* [Programming the Memory Configuration File](#programming-the-memory-configuration-file)
* [Preparing the SD Card](#preparing-the-sd-card)
@ -102,10 +101,6 @@ $ make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf b
> Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files.
### FPU Support
> There is preliminary support for floating point extensions F and D. At the moment floating point support will only be available in QuestaSim as the FPU is written in VHDL. This is likely to change. The floating point extensions can be enabled by setting `RVF` and `RVD` to `1'b1` in the `include/ariane_pkg.sv` file.
## FPGA Emulation
We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/pulp-platform/ariane/releases).
@ -168,7 +163,6 @@ To get started, connect the micro USB port that is labeled with JTAG to your mac
Once attached to your system, the FTDI chip should be listed when you type `lsusb`
```
Bus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
```

2
bootrom/ariane.dts
View file

@ -18,7 +18,7 @@
reg = <0>;
status = "okay";
compatible = "eth, ariane", "riscv";
riscv,isa = "rv64imacsu";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller

8
ci/check-tests.sh
View file

@ -12,7 +12,7 @@ cd $ROOT
if [[ -z "$-" ]]; then
GREEN=''
RED=''
NC=''
NC=''
else
GREEN='\033[0;32m'
RED='\033[0;31m'
@ -28,7 +28,7 @@ fi
# get NUM_TOTAL number of tests
NUM_TOTAL=$2
echo "list containint tests: $2"
echo "list containing tests: $2"
echo "checking files:"
ls "${1}"*.log
@ -45,7 +45,7 @@ echo "NUM_FAILED: $NUM_FAILED"
echo "NUM_FATAL: $NUM_FATAL"
echo "NUM_ERROR: $NUM_ERROR"
if [[ $(($NUM_FAILED)) -gt 0 ]]; then
if [[ $(($NUM_FAILED)) -gt 0 ]]; then
echo -e "${RED}FAILED $NUM_FAILED of $NUM_TOTAL tests ${NC}"
exit 1;
elif [[ $(($NUM_FATAL)) -ne 0 ]]; then
@ -60,4 +60,4 @@ elif [[ $(($NUM_PASSED)) -ne $(($NUM_TOTAL)) ]]; then
else
echo -e "${GREEN}PASSED all $NUM_TOTAL tests ${NC}"
exit 0;
fi
fi

52
ci/float.config Normal file
View file

@ -0,0 +1,52 @@
torture.generator.nseqs 1000
torture.generator.memsize 1024
torture.generator.fprnd 0
torture.generator.amo false
torture.generator.mul true
torture.generator.divider true
torture.generator.segment true
torture.generator.loop true
torture.generator.loop_size 64
torture.generator.mix.xmem 15
torture.generator.mix.xbranch 25
torture.generator.mix.xalu 15
torture.generator.mix.fgen 20
torture.generator.mix.fpmem 10
torture.generator.mix.fax 10
torture.generator.mix.fdiv 5
torture.generator.mix.vec 0
torture.generator.vec.vf 1
torture.generator.vec.seq 20
torture.generator.vec.memsize 128
torture.generator.vec.numsregs 64
torture.generator.vec.mul false
torture.generator.vec.div false
torture.generator.vec.mix true
torture.generator.vec.fpu false
torture.generator.vec.fma false
torture.generator.vec.fcvt false
torture.generator.vec.fdiv false
torture.generator.vec.amo false
torture.generator.vec.seg false
torture.generator.vec.stride false
torture.generator.vec.pred_alu true
torture.generator.vec.pred_mem true
torture.generator.vec.mix.valu 20
torture.generator.vec.mix.vpop 60
torture.generator.vec.mix.vmem 20
torture.generator.vec.mix.vonly 0
torture.testrun.maxcycles 10000000
torture.testrun.virtual false
torture.testrun.seek true
torture.testrun.dump false
torture.testrun.vec false
torture.overnight.errors 1
torture.overnight.minutes 1
torture.overnight.outdir output/failedtests
torture.overnight.email your@email.address

11
ci/install-verilator.sh
View file

@ -9,14 +9,15 @@ fi
if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then
echo "Installing Verilator"
wget https://www.veripool.org/ftp/verilator-3.924.tgz
tar xzf verilator*.t*gz
rm verilator*.t*gz
rm verilator*.t*gz
wget https://www.veripool.org/ftp/verilator-4.008.tgz
tar xzf verilator*.t*gz
rm verilator*.t*gz
cd verilator-*
mkdir -p $VERILATOR_ROOT
# copy scripts
autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS}
cp -r * $VERILATOR_ROOT/
autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS}
cp -r * $VERILATOR_ROOT/
make test
else
echo "Using Verilator from cached directory."

6
ci/path-setup.sh
View file

@ -5,12 +5,12 @@ export CI_BUILD_DIR=$TOP/ariane-repo
#customize this to your setup
export QUESTASIM_HOME=
export QUESTASIM_VERSION=
export QUESTASIM_FLAGS=-noautoldlibpath
export QUESTASIM_FLAGS=
export CXX=g++-7 CC=gcc-7
# where to install the tools
export RISCV=$TOP/riscv_install
export VERILATOR_ROOT=$TOP/verilator-3.924/
export VERILATOR_ROOT=$TOP/verilator-4.008/
export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
export LIBRARY_PATH=$RISCV/lib
@ -19,4 +19,4 @@ export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
# number of parallel jobs to use for make commands and simulation
export NUM_JOBS=8
export NUM_JOBS=8

20
ci/riscv-asm-tests.list
View file

@ -78,26 +78,6 @@ rv64ui-v-or
rv64ui-v-ori
rv64ui-v-sub
rv64ui-v-subw
rv64ui-v-xor
rv64ui-v-xori
rv64ui-v-sll
rv64ui-v-slli
rv64ui-v-slliw
rv64ui-v-slt
rv64ui-v-slti
rv64ui-v-sltiu
rv64ui-v-sltu
rv64ui-v-sra
rv64ui-v-srai
rv64ui-v-sraiw
rv64ui-v-sraw
rv64ui-v-srl
rv64ui-v-srli
rv64ui-v-srliw
rv64ui-v-srlw
rv64ui-v-lb
rv64ui-v-lbu
rv64ui-v-ld
rv64ui-v-lh
rv64ui-v-lhu
rv64ui-v-lui

38
ci/riscv-fp-tests.list Normal file
View file

@ -0,0 +1,38 @@
rv64uf-p-fadd
rv64uf-p-fclass
rv64uf-p-fcmp
rv64uf-p-fcvt
rv64uf-p-fcvt_w
rv64uf-p-fdiv
rv64uf-p-fmadd
rv64uf-p-fmin
rv64uf-p-ldst
rv64uf-p-move
rv64uf-p-recoding
rv64uf-v-fadd
rv64uf-v-fclass
rv64uf-v-fcmp
rv64uf-v-fcvt
rv64uf-v-fcvt_w
rv64uf-v-fdiv
rv64uf-v-fmadd
rv64uf-v-fmin
rv64uf-v-ldst
rv64uf-v-move
rv64uf-v-recoding
rv64ud-p-fadd
rv64ud-p-fclass
rv64ud-p-fcmp
rv64ud-p-fcvt
rv64ud-p-fcvt_w
rv64ud-p-fdiv
rv64ud-p-fmadd
rv64ud-p-fmin
rv64ud-v-fadd
rv64ud-v-fclass
rv64ud-v-fcmp
rv64ud-v-fcvt
rv64ud-v-fcvt_w
rv64ud-v-fdiv
rv64ud-v-fmadd
rv64ud-v-fmin

12
fpga/constraints/ariane.xdc
View file

@ -3,10 +3,10 @@
create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck]
set_input_jitter tck 1.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 10.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 10.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 10.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
# set multicycle path on reset, on the FPGA we do not care about the reset anyway
set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 4
set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 3 -hold

38
fpga/constraints/genesys-2.xdc
View file

@ -1,22 +1,12 @@
## Buttons
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports cpu_resetn]
## PMOD Header JC
# set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports tck]
# set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33} [get_ports tdi]
# set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVCMOS33} [get_ports tdo]
# set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS33} [get_ports tms]
# set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports trst_n]
# accept sub-optimal placement
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
## To use FTDI FT2232 JTAG
set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { tck }];
set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }];
set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { tck }];
set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }];
## UART
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports tx]
@ -72,7 +62,8 @@ set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS15} [get_ports { eth_mdio
#############################################
# Modified for 125MHz receive clock
create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
set_clock_groups -asynchronous -group [get_clocks eth_rxclk -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
## SD Card
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
@ -85,13 +76,12 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
## JTAG
# minimize routing delay
set_max_delay -to [get_ports { td } ] 5
set_max_delay -from [get_ports { tms } ] 5
set_max_delay -from [get_ports { trst_n } ] 5
# reset signal
set_max_delay -to [get_ports { tdo } ] 20
set_max_delay -from [get_ports { tms } ] 20
set_max_delay -from [get_ports { tdi } ] 20
set_max_delay -from [get_ports { trst_n } ] 20
# reset signal
set_false_path -from [get_ports { trst_n } ]
# constrain clock domain crossing
set_false_path -from [get_clocks tck] -to [get_clocks clk_out1]
set_max_delay -from [get_clocks tck] -to [get_clocks clk_out1] 5
set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]

4
fpga/scripts/prologue.tcl
View file

@ -22,4 +22,6 @@ set_property board_part $::env(XILINX_BOARD) [current_project]
# set number of threads to 8 (maximum, unfortunately)
set_param general.maxThreads 8
set_msg_config -id {[Synth 8-5858]} -new_severity "info"
set_msg_config -id {[Synth 8-5858]} -new_severity "info"
set_msg_config -id {[Synth 8-4480]} -limit 1000

7
fpga/scripts/run.tcl
View file

@ -29,13 +29,14 @@ source scripts/add_sources.tcl
set_property top ${project}_xilinx [current_fileset]
if {$::env(BOARD) eq "genesys2"} {
read_verilog -sv {src/genesysii.svh}
read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh}
set file "src/genesysii.svh"
set registers "../src/common_cells/include/common_cells/registers.svh"
} else {
exit 1
}
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*$registers"]]
set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
update_compile_order -fileset sources_1
@ -46,6 +47,8 @@ add_files -fileset constrs_1 -norecurse constraints/$project.xdc
# synth_design -retiming -rtl -name rtl_1 -verilog_define SYNTHESIS -verilog_define
synth_design -rtl -name rtl_1
set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
launch_runs synth_1
wait_on_run synth_1
open_run synth_1

6
fpga/src/bootrom/ariane.dts
View file

@ -13,12 +13,12 @@
#size-cells = <0>;
timebase-frequency = <25000000>; // 25 MHz
CPU0: cpu@0 {
clock-frequency = <50000000>; // 50 MHz
clock-frequency = <30000000>; // 30 MHz
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "eth, ariane", "riscv";
riscv,isa = "rv64imacsu";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
@ -71,7 +71,7 @@
uart@10000000 {
compatible = "ns16750";
reg = <0x0 0x10000000 0x0 0x1000>;
clock-frequency = <50000000>;
clock-frequency = <30000000>;
current-speed = <115200>;
interrupt-parent = <&PLIC0>;
interrupts = <1>;

1146
fpga/src/bootrom/bootrom.h
View file

File diff suppressed because it is too large Load diff

608
fpga/src/bootrom/bootrom.sv
View file

@ -254,7 +254,7 @@ module bootrom (
64'h00000000_00000030,
64'h00000000_67000000,
64'h10000000_03000000,
64'h0000e5e4_e3e2e1ee,
64'h00007fe3_023e1800,
64'hf9010000_06000000,
64'h03000000_00000000,
64'h03000000_58010000,
@ -326,7 +326,7 @@ module bootrom (
64'h47010000_04000000,
64'h03000000_00c20100,
64'h39010000_04000000,
64'h03000000_80f0fa02,
64'h03000000_80c3c901,
64'h4b000000_04000000,
64'h03000000_00100000,
64'h00000000_00000010,
@ -425,7 +425,7 @@ module bootrom (
64'h0a000000_03000000,
64'h00000000_7364656c,
64'h01000000_02000000,
64'h00000008_00000000,
64'h00000040_00000000,
64'h00000080_00000000,
64'h67000000_10000000,
64'h03000000_00007972,
@ -454,7 +454,7 @@ module bootrom (
64'h00003933_76732c76,
64'h63736972_7c000000,
64'h0b000000_03000000,
64'h00007573_63616d69,
64'h00006364_66616d69,
64'h34367672_72000000,
64'h0b000000_03000000,
64'h00000076_63736972,
@ -467,7 +467,7 @@ module bootrom (
64'h67000000_04000000,
64'h03000000_00757063,
64'h5b000000_04000000,
64'h03000000_80f0fa02,
64'h03000000_80c3c901,
64'h4b000000_04000000,
64'h03000000_00000030,
64'h40757063_01000000,
@ -545,312 +545,312 @@ module bootrom (
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_a0018402,
64'h17058593_00000597,
64'h15058593_00000597,
64'h01f41413_0010041b,
64'he911d31f_f0ef057e,
64'h65a14505_eeaff0ef,
64'hda050513_00001517,
64'hec4ff0ef_e4061141,
64'hbbb5f00f_f0ef0a65,
64'h05130000_1517b3f5,
64'he0050513_00001517,
64'hf98ff0ef_8526f1cf,
64'hf0eff025_05130000,
64'h1517f28f_f0efef65,
64'he911d23f_f0ef057e,
64'h65a14505_edcff0ef,
64'hd8050513_00001517,
64'hea4ff0ef_e4063805,
64'h05132005_85931141,
64'h01c9c537_65f1bbb5,
64'hf00ff0ef_09450513,
64'h00001517_b3f5dee5,
64'h05130000_1517f98f,
64'hf0ef8526_f1cff0ef,
64'hef050513_00001517,
64'hf28ff0ef_ee450513,
64'h00001517_c50d84aa,
64'hc33ff0ef_8552865a,
64'h020aa583_f44ff0ef,
64'h0c050513_00001517,
64'hf57993e3_08048493,
64'hf58ff0ef_2985e3e5,
64'h05130000_1517ff2c,
64'h1be382ff_f0ef0905,
64'h00094503_f74ff0ef,
64'h0e050513_00001517,
64'h803ff0ef_7088f86f,
64'hf0ef0e25_05130000,
64'h1517815f_f0ef6c88,
64'hf98ff0ef_0e450513,
64'h00001517_827ff0ef,
64'h07048c13_02848913,
64'h6888fb2f_f0ef0ee5,
64'h05130000_1517ff2c,
64'h1be3887f_f0ef0905,
64'h00094503_01090c13,
64'hfd0ff0ef_0ec50513,
64'h00001517_fe991be3,
64'h8a5ff0ef_09050009,
64'h4503ff04_8913feef,
64'hf0ef0ea5_05130000,
64'h15178bff_f0ef0ff9,
64'hf513803f_f0ef0e65,
64'h05130000_1517b5fd,
64'hef050513_00001517,
64'h89bff0ef_854e81ff,
64'hf0efff25_05130000,
64'h151782bf_f0effe65,
64'h05130000_1517c50d,
64'h84aac33f_f0ef8552,
64'h865a020a_a583f44f,
64'hf0ef0d25_05130000,
64'h1517f579_93e30804,
64'h8493f58f_f0ef2985,
64'he5050513_00001517,
64'hff2c1be3_82fff0ef,
64'h09050009_4503f74f,
64'hf0ef0f25_05130000,
64'h1517803f_f0ef7088,
64'hf86ff0ef_0f450513,
64'h00001517_815ff0ef,
64'h6c88f98f_f0ef0f65,
64'h05130000_1517827f,
64'hf0ef0704_8c130284,
64'h89136888_fb2ff0ef,
64'h10050513_00001517,
64'hff2c1be3_887ff0ef,
64'h09050009_45030109,
64'h0c13fd0f_f0ef0fe5,
64'h05130000_1517fe99,
64'h1be38a5f_f0ef0905,
64'h00094503_ff048913,
64'hfeeff0ef_0fc50513,
64'h00001517_8bfff0ef,
64'h0ff9f513_803ff0ef,
64'h0f850513_00001517,
64'hb5fdf025_05130000,
64'h151789bf_f0ef854e,
64'h81fff0ef_00450513,
64'h00001517_82bff0ef,
64'hff850513_00001517,
64'hc50d0804_89aa8a8a,
64'hd39ff0ef_850a4605,
64'h71010489_258384df,
64'hf0eff425_05130000,
64'h151789bf_f0ef4556,
64'h85fff0ef_13450513,
64'h00001517_8adff0ef,
64'h4546871f_f0ef1265,
64'h05130000_15178fff,
64'hf0ef6526_883ff0ef,
64'h11850513_00001517,
64'h911ff0ef_7502895f,
64'hf0ef11a5_05130000,
64'h1517923f_f0ef6562,
64'h8a7ff0ef_11450513,
64'h00001517_8f5ff0ef,
64'h45528b9f_f0ef1165,
64'h05130000_1517907f,
64'hf0ef4542_8cbff0ef,
64'h11850513_00001517,
64'h919ff0ef_45328ddf,
64'hf0ef11a5_05130000,
64'h151792bf_f0ef4522,
64'h8efff0ef_11c50513,
64'h00001517_97dff0ef,
64'h4b916502_903ff0ef,
64'h12050513_00001517,
64'h90fff0ef_10c50513,
64'h00001517_bf6154f9,
64'h91fff0ef_01450513,
64'h00001517_9adff0ef,
64'h8526931f_f0ef1165,
64'h05130000_151793df,
64'h080489aa_8a8ad39f,
64'hf0ef850a_46057101,
64'h04892583_84dff0ef,
64'hf3050513_00001517,
64'h89bff0ef_455685ff,
64'hf0ef1225_05130000,
64'h15178adf_f0ef4546,
64'h871ff0ef_11450513,
64'h00001517_8ffff0ef,
64'h6526883f_f0ef1065,
64'h05130000_1517911f,
64'hf0ef7502_895ff0ef,
64'h10850513_00001517,
64'h923ff0ef_65628a7f,
64'hf0ef1025_05130000,
64'h15178f5f_f0ef4552,
64'h8b9ff0ef_10450513,
64'h00001517_907ff0ef,
64'h45428cbf_f0ef1065,
64'h05130000_1517919f,
64'hf0ef4532_8ddff0ef,
64'h10850513_00001517,
64'h92bff0ef_45228eff,
64'hf0ef10a5_05130000,
64'h1517c905_84aa890a,
64'he49ff0ef_850a4585,
64'h46057101_95bff0ef,
64'h11050513_00001517,
64'h80826161_6c026ba2,
64'h6b426ae2_7a0279a2,
64'h794274e2_64068526,
64'h60a6fb04_011354fd,
64'h987ff0ef_11450513,
64'h00001517_c51ddf3f,
64'hf0ef8b2e_8a2a0880,
64'he062e45e_ec56f44e,
64'hf84afc26_e486e85a,
64'hf052e0a2_715db765,
64'h54798082_61696baa,
64'h6b4a6aea_7a0a79aa,
64'h794a74ea_640e60ae,
64'h8522547d_9d3ff0ef,
64'h13850513_00001517,
64'hc59ff0ef_c5dff0ef,
64'hc61ff0ef_c65ff0ef,
64'hc69ff0ef_c6dff0ef,
64'hc71ff0ef_c75ff0ef,
64'ha805c7bf_f0efc87f,
64'hf0ef4531_45814605,
64'h4401f930_46e319fd,
64'ha17ff0ef_19c50513,
64'h00001517_e7990359,
64'he7b30724_1a632901,
64'h90411442_8c49caff,
64'hf0ef9041_03051413,
64'h84a20085_151bcbff,
64'hf0effd64_1ae30404,
64'h0413ff74_97e3892a,
64'hf13ff0ef_0485854a,
64'h0007c583_009407b3,
64'h04000b93_4481c67f,
64'hf0ef850a_04000593,
64'h86224901_84262004,
64'h8b13ff45_1ee3cfff,
64'hf0ef3e80_0a930fe0,
64'h0a13e951_d15ff0ef,
64'h454985a2_0ff67613,
64'h00166613_0015161b,
64'hf49ff0ef_0ff47593,
64'hf51ff0ef_0ff5f593,
64'h0084559b_f5dff0ef,
64'h0ff5f593_0104559b,
64'hf69ff0ef_45010ff5,
64'hf5930184_559bfee7,
64'h9be30785_00c68023,
64'h00f106b3_08000713,
64'h567d4781_0209d993,
64'h842e84aa_e55ee95a,
64'hed56f152_f94ae586,
64'hfd26e1a2_02061993,
64'hf54e7155_80829141,
64'h15428d3d_8ff90057,
64'h979b1701_67090107,
64'hd79b0105_179b4105,
64'h551b0105_151b8d2d,
64'h00c59513_8da9893d,
64'h0045d51b_8da99141,
64'h15428d5d_05220085,
64'h579b8082_07f57513,
64'h8d2d0045_15938d2d,
64'h8d3d0045_d51b0075,
64'hd79b8de9_80820141,
64'h853e6402_60a24781,
64'hc11157f5_f89ff0ef,
64'hc51157f9_efbff0ef,
64'hc91157fd_eb7ff0ef,
64'hfc6de03f_f0ef347d,
64'h4429b91f_f0ef2de5,
64'h05130000_1517c89f,
64'hf0efe022_e4061141,
64'h80826105_00153513,
64'h64a26442_60e20004,
64'h051bfc94_0ce3e37f,
64'hf0efeb3f_f0ef3065,
64'h05130000_151785aa,
64'h842ae53f_f0ef0290,
64'h05134000_05b70770,
64'h0613fbdf_f0ef4485,
64'he822ec06_e4261101,
64'h80820141_00153513,
64'h157d6402_60a20004,
64'h051bef3f_f0ef3405,
64'h051385a2_00001517,
64'he89ff0ef_842ae97f,
64'hf0efe022_e4060370,
64'h05134581_06500613,
64'h11418082_61056902,
64'h64a26442_60e20015,
64'h3513f565_05130004,
64'h051b0124_986388bd,
64'h00f91b63_45014785,
64'hec9ff0ef_ecdff0ef,
64'h842aed3f_f0ef84aa,
64'hed9ff0ef_eddff0ef,
64'hee1ff0ef_892aeeff,
64'hf0efe04a_e426e822,
64'hec064521_1aa00593,
64'h08700613_1101bfcd,
64'h45018082_61056902,
64'h64a26442_60e24505,
64'hf89ff0ef_45853ce5,
64'h05130000_1517fe99,
64'h15e3c00d_f25ff0ef,
64'h892a347d_f35ff0ef,
64'h45014581_09500613,
64'h44857104_0413e04a,
64'hec06e426_6409e822,
64'h1101cd1f_f06f6105,
64'h3c850513_00001517,
64'h60e26442_da7ff0ef,
64'h852e65a2_cebff0ef,
64'h41050513_00001517,
64'hcf7ff0ef_8522cfdf,
64'hf0efe42e_ec064165,
64'h05130000_1517842a,
64'he8221101_80826145,
64'h64e27402_70a2f47d,
64'h147d0007_d4634187,
64'hd79b0185_179bfa7f,
64'hf0efeb5f_f0ef8532,
64'h06400413_6622ec1f,
64'hf0ef0ff4_7513ec9f,
64'hf0ef0ff5_75130084,
64'h551bed5f_f0ef0ff5,
64'h75130104_551bee1f,
64'hf0ef0ff5_75130184,
64'h551beedf_f0ef0404,
64'he513febf_f0ef84aa,
64'h842eec26_f022e432,
64'hf4067179_f07ff06f,
64'h0ff00513_8082557d,
64'hb7e900d7_00230785,
64'h00f60733_06c82683,
64'hff798b05_5178bf4d,
64'hd6b80785_0007c703,
64'h80824501_d3b84719,
64'hdbb8577d_200007b7,
64'h00b6ef63_0007869b,
64'h20000837_20000537,
64'hfff58b85_537c2000,
64'h0737d3b8_200007b7,
64'h10600713_fff537fd,
64'h00010320_079304b7,
64'h616340a7_873b87aa,
64'h200006b7_dbb85779,
64'h200007b7_06b7ec63,
64'h10000793_80826105,
64'h64a2d3b8_4719dbb8,
64'h644260e2_0ff47513,
64'h577d2000_07b7e25f,
64'hf0ef51a5_05130000,
64'h1517eb3f_f0ef9101,
64'h15024088_e3bff0ef,
64'h53850513_00001517,
64'he3958b85_240153fc,
64'h57e0ff65_8b050647,
64'h849353f8_d3b81060,
64'h07132000_07b7fff5,
64'h37fd0001_06400793,
64'hd7a8dbb8_5779e426,
64'he822ec06_200007b7,
64'h1101e81f_f06f6105,
64'h56850513_00001517,
64'h64a260e2_6442d03c,
64'h4799e99f_f0ef58e5,
64'h05130000_1517f27f,
64'hf0ef9101_02049513,
64'h2481eb1f_f0ef5865,
64'h05130000_15175064,
64'hd03c1660_0793ec5f,
64'hf0ef5ba5_05130000,
64'h1517f53f_f0ef9101,
64'h02049513_2481eddf,
64'hf0ef5b25_05130000,
64'h15175064_d03c1040,
64'h07932000_0437fff5,
64'h37fd0001_47a9c3b8,
64'h47292000_07b7f05f,
64'hf0efe426_e822ec06,
64'h5d250513_11010000,
64'h15178082_41088082,
64'hc10c8082_610560e2,
64'hee1ff0ef_00914503,
64'hee9ff0ef_00814503,
64'hf55ff0ef_ec06002c,
64'h11018082_61456942,
64'h151797df_f0ef4b91,
64'h6502903f_f0ef10e5,
64'h05130000_151790ff,
64'hf0ef0fa5_05130000,
64'h1517bf61_54f991ff,
64'hf0ef0025_05130000,
64'h15179adf_f0ef8526,
64'h931ff0ef_10450513,
64'h00001517_93dff0ef,
64'h0f850513_00001517,
64'hc90584aa_890ae49f,
64'hf0ef850a_45854605,
64'h710195bf_f0ef0fe5,
64'h05130000_15178082,
64'h61616c02_6ba26b42,
64'h6ae27a02_79a27942,
64'h74e26406_852660a6,
64'hfb040113_54fd987f,
64'hf0ef1025_05130000,
64'h1517c51d_df3ff0ef,
64'h8b2e8a2a_0880e062,
64'he45eec56_f44ef84a,
64'hfc26e486_e85af052,
64'he0a2715d_b7655479,
64'h80826169_6baa6b4a,
64'h6aea7a0a_79aa794a,
64'h74ea640e_60ae8522,
64'h547d9d3f_f0ef1265,
64'h05130000_1517c59f,
64'hf0efc5df_f0efc61f,
64'hf0efc65f_f0efc69f,
64'hf0efc6df_f0efc71f,
64'hf0efc75f_f0efa805,
64'hc7bff0ef_c87ff0ef,
64'h45314581_46054401,
64'hf93046e3_19fda17f,
64'hf0ef18a5_05130000,
64'h1517e799_0359e7b3,
64'h07241a63_29019041,
64'h14428c49_cafff0ef,
64'h90410305_141384a2,
64'h0085151b_cbfff0ef,
64'hfd641ae3_04040413,
64'hff7497e3_892af13f,
64'hf0ef0485_854a0007,
64'hc5830094_07b30400,
64'h0b934481_c67ff0ef,
64'h850a0400_05938622,
64'h49018426_20048b13,
64'hff451ee3_cffff0ef,
64'h3e800a93_0fe00a13,
64'he951d15f_f0ef4549,
64'h85a20ff6_76130016,
64'h66130015_161bf49f,
64'hf0ef0ff4_7593f51f,
64'hf0ef0ff5_f5930084,
64'h559bf5df_f0ef0ff5,
64'hf5930104_559bf69f,
64'hf0ef4501_0ff5f593,
64'h0184559b_fee79be3,
64'h078500c6_802300f1,
64'h06b30800_0713567d,
64'h47810209_d993842e,
64'h84aae55e_e95aed56,
64'hf152f94a_e586fd26,
64'he1a20206_1993f54e,
64'h71558082_91411542,
64'h8d3d8ff9_0057979b,
64'h17016709_0107d79b,
64'h0105179b_4105551b,
64'h0105151b_8d2d00c5,
64'h95138da9_893d0045,
64'hd51b8da9_91411542,
64'h8d5d0522_0085579b,
64'h808207f5_75138d2d,
64'h00451593_8d2d8d3d,
64'h0045d51b_0075d79b,
64'h8de98082_0141853e,
64'h640260a2_4781c111,
64'h57f5f89f_f0efc511,
64'h57f9efbf_f0efc911,
64'h57fdeb7f_f0effc6d,
64'he03ff0ef_347d4429,
64'hb91ff0ef_2cc50513,
64'h00001517_c89ff0ef,
64'he022e406_11418082,
64'h61050015_351364a2,
64'h644260e2_0004051b,
64'hfc940ce3_e37ff0ef,
64'heb3ff0ef_2f450513,
64'h00001517_85aa842a,
64'he53ff0ef_02900513,
64'h400005b7_07700613,
64'hfbdff0ef_4485e822,
64'hec06e426_11018082,
64'h01410015_3513157d,
64'h640260a2_0004051b,
64'hef3ff0ef_32e50513,
64'h85a20000_1517e89f,
64'hf0ef842a_e97ff0ef,
64'he022e406_03700513,
64'h45810650_06131141,
64'h80826105_690264a2,
64'h644260e2_00153513,
64'hf5650513_0004051b,
64'h01249863_88bd00f9,
64'h1b634501_4785ec9f,
64'hf0efecdf_f0ef842a,
64'hed3ff0ef_84aaed9f,
64'hf0efeddf_f0efee1f,
64'hf0ef892a_eefff0ef,
64'he04ae426_e822ec06,
64'h45211aa0_05930870,
64'h06131101_bfcd4501,
64'h80826105_690264a2,
64'h644260e2_4505f89f,
64'hf0ef4585_3bc50513,
64'h00001517_fe9915e3,
64'hc00df25f_f0ef892a,
64'h347df35f_f0ef4501,
64'h45810950_06134485,
64'h71040413_e04aec06,
64'he4266409_e8221101,
64'hcd1ff06f_61053b65,
64'h05130000_151760e2,
64'h6442da7f_f0ef852e,
64'h65a2cebf_f0ef3fe5,
64'h05130000_1517cf7f,
64'hf0ef8522_cfdff0ef,
64'he42eec06_40450513,
64'h00001517_842ae822,
64'h11018082_614564e2,
64'h740270a2_f47d147d,
64'h0007d463_4187d79b,
64'h0185179b_fa7ff0ef,
64'heb5ff0ef_85320640,
64'h04136622_ec1ff0ef,
64'h0ff47513_ec9ff0ef,
64'h0ff57513_0084551b,
64'hed5ff0ef_0ff57513,
64'h0104551b_ee1ff0ef,
64'h0ff57513_0184551b,
64'heedff0ef_0404e513,
64'hfebff0ef_84aa842e,
64'hec26f022_e432f406,
64'h7179f07f_f06f0ff0,
64'h05138082_557db7e9,
64'h00d70023_078500f6,
64'h073306c8_2683ff79,
64'h8b055178_bf4dd6b8,
64'h07850007_c7038082,
64'h4501d3b8_4719dbb8,
64'h577d2000_07b700b6,
64'hef630007_869b2000,
64'h08372000_0537fff5,
64'h8b85537c_20000737,
64'hd3b82000_07b71060,
64'h0713fff5_37fd0001,
64'h03200793_04b76163,
64'h40a7873b_87aa2000,
64'h06b7dbb8_57792000,
64'h07b706b7_ec631000,
64'h07938082_610564a2,
64'hd3b84719_dbb86442,
64'h60e20ff4_7513577d,
64'h200007b7_e25ff0ef,
64'h50850513_00001517,
64'heb3ff0ef_91011502,
64'h4088e3bf_f0ef5265,
64'h05130000_1517e395,
64'h8b852401_53fc57e0,
64'hff658b05_06478493,
64'h53f8d3b8_10600713,
64'h200007b7_fff537fd,
64'h00010640_0793d7a8,
64'hdbb85779_e426e822,
64'hec062000_07b71101,
64'he81ff06f_61055565,
64'h05130000_151764a2,
64'h60e26442_d03c4799,
64'he99ff0ef_57c50513,
64'h00001517_f27ff0ef,
64'h91010204_95132481,
64'heb1ff0ef_57450513,
64'h00001517_5064d03c,
64'h16600793_ec5ff0ef,
64'h5a850513_00001517,
64'hf53ff0ef_91010204,
64'h95132481_eddff0ef,
64'h5a050513_00001517,
64'h5064d03c_10400793,
64'h20000437_fff537fd,
64'h000147a9_c3b84729,
64'h200007b7_f05ff0ef,
64'he426e822_ec065c05,
64'h05131101_00001517,
64'h80824108_8082c10c,
64'h80826105_60e2ecff,
64'hf0ef0091_4503ed7f,
64'hf0ef0081_4503f55f,
64'hf0efec06_002c1101,
64'h80826145_694264e2,
64'h740270a2_fe9410e3,
64'hef9ff0ef_00914503,
64'hf01ff0ef_34610081,
64'h4503f81f_f0ef0ff5,
64'h7513002c_00895533,
64'h54e10380_0413892a,
64'hf406e84a_ec26f022,
64'h71798082_61456942,
64'h64e27402_70a2fe94,
64'h10e3f0bf_f0ef0091,
64'h4503f13f_f0ef3461,
64'h00814503_f81ff0ef,
64'h10e3f3bf_f0ef0091,
64'h4503f43f_f0ef3461,
64'h00814503_fc3ff0ef,
64'h0ff57513_002c0089,
64'h553354e1_03800413,
64'h892af406_e84aec26,
64'hf0227179_80826145,
64'h694264e2_740270a2,
64'hfe9410e3_f4dff0ef,
64'h00914503_f55ff0ef,
64'h34610081_4503fc3f,
64'hf0ef0ff5_7513002c,
64'h0089553b_54e14461,
64'h892af406_e84aec26,
64'hf0227179_808200f5,
64'h80230007_c78300e5,
64'h80a397aa_81110007,
64'h4703973e_00f57713,
64'h98078793_00001797,
64'hb7f50405_fa5ff0ef,
64'h80820141_640260a2,
64'he5090004_4503842a,
64'he406e022_11418082,
64'h00e78823_02000713,
64'h00e78423_fc700713,
64'h00e78623_470d0007,
64'h822300e7_8023476d,
64'h553b54e1_4461892a,
64'hf406e84a_ec26f022,
64'h71798082_00f58023,
64'h0007c783_00e580a3,
64'h97aa8111_00074703,
64'h973e00f5_771396e7,
64'h87930000_1797b7f5,
64'h0405f93f_f0ef8082,
64'h01416402_60a2e509,
64'h00044503_842ae406,
64'he0221141_808200e7,
64'h88230200_071300e7,
64'h8423fc70_071300e7,
64'h8623470d_00a78223,
64'h0ff57513_00e78023,
64'h0085551b_0ff57713,
64'h00e78623_f8000713,
64'h00078223_100007b7,
64'h02b5553b_0045959b,
64'h808200a7_0023dfe5,
64'h0207f793_01474783,
64'h10000737_80820205,
@ -885,7 +885,7 @@ module bootrom (
64'h4009091b_02000937,
64'h00448493_0124a023,
64'h00100913_020004b7,
64'h24d000ef_01a11113,
64'h25f000ef_01a11113,
64'h0210011b_03249663,
64'hf1402973_00000493,
64'h30491073_00800913

2
fpga/src/bootrom/src/main.c
View file

@ -5,7 +5,7 @@
int main()
{
init_uart();
init_uart(30000000, 115200);
print_uart("Hello World!\r\n");
int res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384);

8
fpga/src/bootrom/src/uart.c
View file

@ -23,12 +23,14 @@ void write_serial(char a)
write_reg_u8(UART_THR, a);
}
void init_uart()
void init_uart(uint32_t freq, uint32_t baud)
{
uint32_t divisor = freq / (baud << 4);
write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts
write_reg_u8(UART_LINE_CONTROL, 0x80); // Enable DLAB (set baud rate divisor)
write_reg_u8(UART_DLAB_LSB, 0x1B); // Set divisor to 27 (lo byte) 115200 baud
write_reg_u8(UART_DLAB_MSB, 0x00); // (hi byte)
write_reg_u8(UART_DLAB_LSB, divisor); // divisor (lo byte)
write_reg_u8(UART_DLAB_MSB, (divisor >> 8) & 0xFF); // divisor (hi byte)
write_reg_u8(UART_LINE_CONTROL, 0x03); // 8 bits, no parity, one stop bit
write_reg_u8(UART_FIFO_CONTROL, 0xC7); // Enable FIFO, clear them, with 14-byte threshold
write_reg_u8(UART_MODEM_CONTROL, 0x20); // Autoflow mode

2
fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
View file

@ -13,7 +13,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT3_REQUESTED_PHASE {90.000} \

20
include/ariane_pkg.sv
View file

@ -62,8 +62,8 @@ package ariane_pkg;
`endif
// Floating-point extensions configuration
localparam bit RVF = 1'b0; // Is F extension enabled
localparam bit RVD = 1'b0; // Is D extension enabled
localparam bit RVF = 1'b1; // Is F extension enabled
localparam bit RVD = 1'b1; // Is D extension enabled
localparam bit RVA = 1'b1; // Is A extension enabled
// Transprecision floating-point extensions configuration
@ -73,14 +73,14 @@ package ariane_pkg;
localparam bit XFVEC = 1'b0; // Is vectorial float extension (Xfvec) enabled
// Transprecision float unit
localparam logic [30:0] LAT_COMP_FP32 = 'd3;
localparam logic [30:0] LAT_COMP_FP64 = 'd4;
localparam logic [30:0] LAT_COMP_FP16 = 'd3;
localparam logic [30:0] LAT_COMP_FP16ALT = 'd3;
localparam logic [30:0] LAT_COMP_FP8 = 'd2;
localparam logic [30:0] LAT_DIVSQRT = 'd2;
localparam logic [30:0] LAT_NONCOMP = 'd1;
localparam logic [30:0] LAT_CONV = 'd2;
localparam int unsigned LAT_COMP_FP32 = 'd2;
localparam int unsigned LAT_COMP_FP64 = 'd3;
localparam int unsigned LAT_COMP_FP16 = 'd1;
localparam int unsigned LAT_COMP_FP16ALT = 'd1;
localparam int unsigned LAT_COMP_FP8 = 'd1;
localparam int unsigned LAT_DIVSQRT = 'd2;
localparam int unsigned LAT_NONCOMP = 'd1;
localparam int unsigned LAT_CONV = 'd2;
// --------------------------------------
// vvvv Don't change these by hand! vvvv

14
openpiton/ariane_verilog_wrap.sv
View file

@ -111,6 +111,20 @@ module ariane_verilog_wrap #(
// reset gate this
assign rst_n = wake_up_cnt_q[$high(wake_up_cnt_q)] & reset_l;
// reset_synchronizer #(
// .NUM_REGS(2)
// ) i_sync (
// .clk_i ( clk_i ),
// .rst_ni ( rst_n ),
// .tmode_i ( 1'b0 ),
// .rst_no ( spc_grst_l )
// );
synchronizer i_sync (
.clk ( clk_i ),
.presyncdata ( rst_n ),
.syncdata ( spc_grst_l )
);
/////////////////////////////
// synchronizers

2
src/axi

@ -1 +1 @@
Subproject commit de1af467229315ee6af31fea96664c7aae5638a9
Subproject commit d94d601e55213d770beceebfab7786adf7baf8ce

2
src/common_cells

@ -1 +1 @@
Subproject commit b4769f4121ed42e99dd168122e036ce1f218637b
Subproject commit c5e93e3e10abc719fed12dd92d41c1af9a0054c6

4
src/decoder.sv
View file

@ -298,9 +298,9 @@ module decoder (
5'b00000 : begin
instruction_o.rs2 = instr.rvftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit
if (instr.rvftype.repl)
instruction_o.op = FMV_F2X; // vfmv.x.vfmt - FPR to GPR Move
else
instruction_o.op = FMV_X2F; // vfmv.vfmt.x - GPR to FPR Move
else
instruction_o.op = FMV_F2X; // vfmv.x.vfmt - FPR to GPR Move
check_fprm = 1'b0; // no rounding for moves
end
5'b00001 : begin

2
src/fpu

@ -1 +1 @@
Subproject commit 0d4970af8fbe35e88a6d0395c51cfb58b6d1faf9
Subproject commit 9fa89ab655dfe630c22360e21c259ee2091427f8

2
src/fpu_div_sqrt_mvp

@ -1 +1 @@
Subproject commit 3736c4c844074bd64c3c505c017181db71b738b4
Subproject commit d94bf84ff56fca7e3f8e0a719c8a493ec6c39153

1055
src/fpu_wrap.sv
View file

File diff suppressed because it is too large Load diff

4
src/load_store_unit.sv
View file

@ -205,7 +205,7 @@ module load_store_unit #(
// ----------------------------
// Output Pipeline Register
// ----------------------------
pipe_reg_simple #(
shift_reg #(
.dtype ( logic[$bits(ld_valid) + $bits(ld_trans_id) + $bits(ld_result) + $bits(ld_ex) - 1: 0]),
.Depth ( NR_LOAD_PIPE_REGS )
) i_pipe_reg_load (
@ -215,7 +215,7 @@ module load_store_unit #(
.d_o ( {load_valid_o, load_trans_id_o, load_result_o, load_exception_o} )
);
pipe_reg_simple #(
shift_reg #(
.dtype ( logic[$bits(st_valid) + $bits(st_trans_id) + $bits(st_result) + $bits(st_ex) - 1: 0]),
.Depth ( NR_STORE_PIPE_REGS )
) i_pipe_reg_store (