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https://github.com/openhwgroup/cva6.git
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Convert DV into a submodule (#1591)
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parent
b6ff6887c7
commit
b2a59c9617
4 changed files with 5 additions and 25 deletions
3
.gitmodules
vendored
3
.gitmodules
vendored
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@ -40,3 +40,6 @@
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[submodule "core/cache_subsystem/hpdcache"]
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path = core/cache_subsystem/hpdcache
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url = https://github.com/openhwgroup/cv-hpdcache.git
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[submodule "verif/sim/dv"]
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path = verif/sim/dv
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url = https://github.com/google/riscv-dv.git
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1
verif/.gitignore
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1
verif/.gitignore
vendored
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@ -39,7 +39,6 @@ tests/riscv-compliance/
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tests/riscv-arch-test/
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tests/riscv-tests/
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tests/riscv-isa-sim/
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sim/dv/
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sim/vcs_results
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sim/verilator_work
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sim/out_*
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@ -20,27 +20,4 @@ export RTL_PATH=$ROOT_PROJECT/
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export TB_PATH=$ROOT_PROJECT/verif/tb/core
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export TESTS_PATH=$ROOT_PROJECT/verif/tests
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if [ -z "$DV_REPO" ]; then
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export DV_REPO="https://github.com/chipsalliance/riscv-dv.git"
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export DV_BRANCH="master"
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export DV_HASH="f0c570d11236f94f9c5449870223a5ac717cc580"
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export DV_PATCH=
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fi
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echo "Repo: " $DV_REPO
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echo "Branch:" $DV_BRANCH
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echo "Hash: " $DV_HASH
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echo "Patch: " $DV_PATCH
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mkdir -p verif/sim
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if ! [ -d verif/sim/dv ]; then
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git clone $DV_REPO -b $DV_BRANCH verif/sim/dv
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cd verif/sim/dv; git checkout $DV_HASH;
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if [[ -n "$DV_PATCH" && -f "$DV_PATCH" ]]; then
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git apply "$DV_PATCH"
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fi
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cd -
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# install riscv-dv dependencies
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cd verif/sim/dv; pip3 install -r requirements.txt; cd -
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fi
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touch verif/sim/dv/__init__.py
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(cd verif/sim/dv; pip3 install -r requirements.txt)
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1
verif/sim/dv
Submodule
1
verif/sim/dv
Submodule
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@ -0,0 +1 @@
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Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580
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