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CVA6 : Disable register crossing in Functional coverage

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This commit is contained in:
Ayoub Jalali 2023-08-29 15:33:20 +02:00
parent 17e0f4caf4
commit b2cbb30236
1 changed files with 3 additions and 3 deletions
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6
cva6/env/uvme/uvme_cva6_cfg.sv vendored
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@ -73,11 +73,11 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
soft sys_clk_period == uvme_cva6_sys_default_clk_period; // see uvme_cva6_constants.sv soft sys_clk_period == uvme_cva6_sys_default_clk_period; // see uvme_cva6_constants.sv
} }
constraint cvxif_feature { //CVA6 do not support dual read & write also the memory interface constraint cvxif_feature { //CV32A60X do not support dual read & write also the memory interface
cvxif_cfg.dual_read_write_support_x == 0; cvxif_cfg.dual_read_write_support_x == 0;
cvxif_cfg.load_store_support_x == 0; cvxif_cfg.load_store_support_x == 0;
cvxif_cfg.seq_cus_instr_x2_enabled == 1; cvxif_cfg.seq_cus_instr_x2_enabled == 1;
cvxif_cfg.reg_cus_crosses_enabled == 1; cvxif_cfg.reg_cus_crosses_enabled == 0;
} }
constraint cva6_riscv_cons { constraint cva6_riscv_cons {
xlen == uvma_core_cntrl_pkg::MXL_32; xlen == uvma_core_cntrl_pkg::MXL_32;
@ -145,7 +145,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
isacov_cfg.seq_instr_group_x3_enabled == 0; isacov_cfg.seq_instr_group_x3_enabled == 0;
isacov_cfg.seq_instr_group_x4_enabled == 0; isacov_cfg.seq_instr_group_x4_enabled == 0;
isacov_cfg.seq_instr_x2_enabled == 1; isacov_cfg.seq_instr_x2_enabled == 1;
isacov_cfg.reg_crosses_enabled == 1; isacov_cfg.reg_crosses_enabled == 0;
isacov_cfg.reg_hazards_enabled == 1; isacov_cfg.reg_hazards_enabled == 1;
rvfi_cfg.nret == RVFI_NRET; rvfi_cfg.nret == RVFI_NRET;