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🐛 Fix bug which led to an unreachable program buffer

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This commit is contained in:
Florian Zaruba 2018-07-27 23:56:53 +02:00
parent 4d9ab6adfe
commit b37d9c1c5e
4 changed files with 8 additions and 7 deletions
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8
Makefile
View file

@ -109,16 +109,16 @@ $(library)/.build-interfaces: $(interfaces)
$(library):
# Create the library
vlib${questa_version} ${library}
# +jtag_rbb_enable=1
sim: build $(library)/ariane_dpi.so
vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug +jtag_rbb_enable=1 \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do "run -all; do tb/wave/wave_core.do; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
simc: build $(library)/ariane_dpi.so
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug +jtag_rbb_enable=1 \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do "run -all; do tb/wave/wave_core.do; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
run-asm-tests: build
$(foreach test, $(riscv-ci-tests), vsim$(questa_version) +permissive -64 +BASEDIR=$(riscv-test-dir) +max-cycles=$(max_cycles) \

3
src/csr_regfile.sv
View file

@ -831,7 +831,8 @@ module csr_regfile #(
dscratch0_q <= 64'b0;
// machine mode registers
mstatus_q <= 64'b0;
mtvec_q <= {boot_addr_i[63:2], 2'b0}; // set to boot address + direct mode
// set to boot address + direct mode + 4 byte offset which is the initial trap
mtvec_q <= {boot_addr_i[63:3], 3'h4};
medeleg_q <= 64'b0;
mideleg_q <= 64'b0;
mip_q <= 64'b0;

2
src/debug/dm_mem.sv
View file

@ -332,7 +332,7 @@ module dm_mem #(
// check whether we need to execute the program buffer
if (ac_ar.postexec) begin
// issue a nop, we will automatically run into the program buffer
abstract_cmd[2][31:0] = riscv::nop();
abstract_cmd[2][63:32] = riscv::nop();
end
end
// not supported at the moment

2
tb

@ -1 +1 @@
Subproject commit 2c56aa7d93c08107266a128ceb8dd22351e0d944
Subproject commit 05e67667d39c09e19e24011045f97b5c749f1461