github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-19 11:54:46 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Merge branch 'master' of github.com:msfschaffner/ariane

Browse source
This commit is contained in:
Michael Schaffner 2019-01-08 13:10:50 +01:00
commit b3a1b28136
No known key found for this signature in database
GPG key ID: 7AA09AE049819C2C
3 changed files with 10 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
Makefile
View file

@ -71,7 +71,7 @@ dpi := $(patsubst tb/dpi/%.cc,${dpi-library}/%.o,$(wildcard tb/dpi/*.cc))
dpi_hdr := $(wildcard tb/dpi/*.h)
dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
CFLAGS := -I$(QUESTASIM_HOME)/include \
-Itb/riscv-isa-sim/install/include/spike \
-I$(RISCV)/include \
-std=c++11 -I../tb/dpi
# this list contains the standalone components

15
src/debug/dm_mem.sv
View file

@ -289,17 +289,17 @@ module dm_mem #(
// --------------------
dm::AccessRegister: begin
if (ac_ar.aarsize < 4 && ac_ar.transfer && ac_ar.write) begin
// this range is reserved
if (ac_ar.regno[15:14] != '0) begin
abstract_cmd[0][31:0] = riscv::illegal();
// GPR/FPR access
if (ac_ar.regno[12]) begin
end else if (ac_ar.regno[12]) begin
// determine whether we want to access the floating point register or not
if (ac_ar.regno[5]) begin
abstract_cmd[0][31:0] = riscv::float_load(ac_ar.aarsize, ac_ar.regno[4:0], 0, dm::DataAddr);
end else begin
abstract_cmd[0][31:0] = riscv::load(ac_ar.aarsize, ac_ar.regno[4:0], 0, dm::DataAddr);
end
// this range is reserved
end else if (ac_ar.regno[15:14] != '0) begin
abstract_cmd[0][31:0] = riscv::illegal();
// CSR access
end else begin
// data register to CSR
@ -313,16 +313,17 @@ module dm_mem #(
abstract_cmd[1][63:32] = riscv::csrr(riscv::CSR_DSCRATCH0, 8);
end
end else if (ac_ar.aarsize < 4 && ac_ar.transfer && !ac_ar.write) begin
// this range is reserved
if (ac_ar.regno[15:14] != '0) begin
abstract_cmd[0][31:0] = riscv::illegal();
// GPR/FPR access
if (ac_ar.regno[12]) begin
end else if (ac_ar.regno[12]) begin
// determine whether we want to access the floating point register or not
if (ac_ar.regno[5]) begin
abstract_cmd[0][31:0] = riscv::float_store(ac_ar.aarsize, ac_ar.regno[4:0], 0, dm::DataAddr);
end else begin
abstract_cmd[0][31:0] = riscv::store(ac_ar.aarsize, ac_ar.regno[4:0], 0, dm::DataAddr);
end
end else if (ac_ar.regno[15:14] != '0) begin
abstract_cmd[0][31:0] = riscv::illegal();
// CSR access
end else begin
// CSR register to data

2
src/debug/dm_pkg.sv
View file

@ -141,7 +141,7 @@ package dm;
typedef struct packed {
logic [31:29] zero3;
logic [28:24] progbufsize;
logic [23:12] zero2;
logic [23:13] zero2;
logic busy;
logic zero1;
cmderr_t cmderr;