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[CSR] Fix bits when RVS and RVU not available (#2074)

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MarioOpenHWGroup 2024-05-22 15:54:51 +02:00 • committed by GitHub
parent 1c6da9b739
commit b48a2bb63d
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1 changed files with 14 additions and 1 deletions
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15
core/csr_regfile.sv
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@ -773,7 +773,8 @@ module csr_regfile
// -> last bit of pmpaddr must be set 0/1 based on the mode:
// NA4, NAPOT: 1
// TOR, OFF: 0
if (pmpcfg_q[index].addr_mode[1] == 1'b1) csr_rdata = pmpaddr_q[index][CVA6Cfg.PLEN-3:0];
if (pmpcfg_q[index].addr_mode[1] == 1'b1 || pmpcfg_q[index].addr_mode == 'h0)
csr_rdata = pmpaddr_q[index][CVA6Cfg.PLEN-3:0];
else csr_rdata = {pmpaddr_q[index][CVA6Cfg.PLEN-3:1], 1'b0};
end
default: read_access_exception = 1'b1;
@ -1249,6 +1250,18 @@ module csr_regfile
if (!CVA6Cfg.RVV) begin
mstatus_d.vs = riscv::Off;
end
if (!CVA6Cfg.RVS) begin
mstatus_d.sie = riscv::Off;
mstatus_d.spie = riscv::Off;
mstatus_d.spp = riscv::Off;
mstatus_d.sum = riscv::Off;
mstatus_d.mxr = riscv::Off;
mstatus_d.tvm = riscv::Off;
mstatus_d.tsr = riscv::Off;
end
if (!CVA6Cfg.RVU) begin
mstatus_d.mprv = riscv::Off;
end
// If h-extension is not enabled, priv level HS is reserved
if (!CVA6Cfg.RVH) begin
if (mstatus_d.mpp == riscv::PRIV_LVL_HS) begin