Design Document, add ID_STAGE description (#1832)

core/commit_stage.sv

@@ -36,13 +36,13 @@ module commit_stage
     input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
     // Acknowledge that we are indeed committing - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o,
-    // Register file write address - ID_STAGE
+    // Register file write address - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_o,
-    // Register file write data - ID_STAGE
+    // Register file write data - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_o,
-    // Register file write enable - ID_STAGE
+    // Register file write enable - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_o,
-    // Floating point register enable - ID_STAGE
+    // Floating point register enable - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_o,
     // Result of AMO operation - CACHE
     input amo_resp_t amo_resp_i,

core/compressed_decoder.sv

@@ -22,9 +22,13 @@
 module compressed_decoder #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
 ) (
+    // Input instruction coming from fetch stage - FRONTEND
     input  logic [31:0] instr_i,
+    // Output instruction in uncompressed format - decoder
     output logic [31:0] instr_o,
+    // Input instruction is illegal - decoder
     output logic        illegal_instr_o,
+    // Output instruction is compressed - decoder
     output logic        is_compressed_o
 );
 

core/decoder.sv

@@ -24,28 +24,48 @@ module decoder
 #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
 ) (
-    input logic debug_req_i,  // external debug request
-    input logic [riscv::VLEN-1:0] pc_i,  // PC from IF
-    input logic is_compressed_i,  // is a compressed instruction
-    input logic [15:0] compressed_instr_i,  // compressed form of instruction
-    input logic is_illegal_i,  // illegal compressed instruction
-    input logic [31:0] instruction_i,  // instruction from IF
+    // Debug (async) request - SUBSYSTEM
+    input logic debug_req_i,
+    // PC from fetch stage - FRONTEND
+    input logic [riscv::VLEN-1:0] pc_i,
+    // Is a compressed instruction - compressed_decoder
+    input logic is_compressed_i,
+    // Compressed form of instruction - FRONTEND
+    input logic [15:0] compressed_instr_i,
+    // Illegal compressed instruction - compressed_decoder
+    input logic is_illegal_i,
+    // Instruction from fetch stage - FRONTEND
+    input logic [31:0] instruction_i,
+    // Is a branch predict instruction - FRONTEND
     input branchpredict_sbe_t branch_predict_i,
-    input exception_t ex_i,  // if an exception occured in if
-    input logic [1:0] irq_i,  // external interrupt
-    input irq_ctrl_t irq_ctrl_i,  // interrupt control and status information from CSRs
-    // From CSR
-    input riscv::priv_lvl_t priv_lvl_i,  // current privilege level
-    input logic debug_mode_i,  // we are in debug mode
-    input riscv::xs_t fs_i,  // floating point extension status
-    input logic [2:0] frm_i,  // floating-point dynamic rounding mode
-    input riscv::xs_t vs_i,  // vector extension status
-    input logic tvm_i,  // trap virtual memory
-    input logic tw_i,  // timeout wait
-    input logic tsr_i,  // trap sret
-    output scoreboard_entry_t instruction_o,  // scoreboard entry to scoreboard
-    output logic [31:0] orig_instr_o,  // instruction opcode to issue read operand for CVXIF
-    output logic is_control_flow_instr_o  // this instruction will change the control flow
+    // If an exception occured in fetch stage - FRONTEND
+    input exception_t ex_i,
+    // Level sensitive (async) interrupts - SUBSYSTEM
+    input logic [1:0] irq_i,
+    // Interrupt control status - CSR_REGFILE
+    input irq_ctrl_t irq_ctrl_i,
+    // Current privilege level - CSR_REGFILE
+    input riscv::priv_lvl_t priv_lvl_i,
+    // Is debug mode - CSR_REGFILE
+    input logic debug_mode_i,
+    // Floating point extension status - CSR_REGFILE
+    input riscv::xs_t fs_i,
+    // Floating-point dynamic rounding mode - CSR_REGFILE
+    input logic [2:0] frm_i,
+    // Vector extension status - CSR_REGFILE
+    input riscv::xs_t vs_i,
+    // Trap virtual memory - CSR_REGFILE
+    input logic tvm_i,
+    // Timeout wait - CSR_REGFILE
+    input logic tw_i,
+    // Trap sret - CSR_REGFILE
+    input logic tsr_i,
+    // Instruction to be added to scoreboard entry - ISSUE_STAGE
+    output scoreboard_entry_t instruction_o,
+    // Instruction - ISSUE_STAGE
+    output logic [31:0] orig_instr_o,
+    // Is a control flow instruction - ISSUE_STAGE
+    output logic is_control_flow_instr_o
 );
   logic illegal_instr;
   logic illegal_instr_bm;

core/ex_stage.sv

@@ -28,67 +28,67 @@ module ex_stage
     input logic flush_i,
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic debug_mode_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // rs1 forwarding - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] rs1_forwarding_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // rs2 forwarding - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] rs2_forwarding_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FU data useful to execute instruction - ISSUE_STAGE
     input fu_data_t fu_data_i,
-    // PC of the current instruction - ID_STAGE
+    // PC of the current instruction - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] pc_i,
-    // Report whether isntruction is compressed - ID_STAGE
+    // Report whether isntruction is compressed - ISSUE_STAGE
     input logic is_compressed_instr_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // TO_BE_COMPLETED - ISSUE_STAGE
     output riscv::xlen_t flu_result_o,
-    // ID of the scoreboard entry at which a=to write back - ID_STAGE
+    // ID of the scoreboard entry at which a=to write back - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] flu_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // TO_BE_COMPLETED - ISSUE_STAGE
     output exception_t flu_exception_o,
-    // FLU is ready - ID_STAGE
+    // FLU is ready - ISSUE_STAGE
     output logic flu_ready_o,
-    // FLU result is valid - ID_STAGE
+    // FLU result is valid - ISSUE_STAGE
     output logic flu_valid_o,
-    // ALU result is valid - ID_STAGE
+    // ALU instruction is valid - ISSUE_STAGE
     input logic alu_valid_i,
-    // Branch unit result is valid - ID_STAGE
+    // Branch unit instruction is valid - ISSUE_STAGE
     input logic branch_valid_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Information of branch prediction - ISSUE_STAGE
     input branchpredict_sbe_t branch_predict_i,
-    // The branch engine uses the write back from the ALU - CONTROLLER PERF_COUNTER FRONTEND ISSUE_STAGE
+    // The branch engine uses the write back from the ALU - several_modules
     output bp_resolve_t resolved_branch_o,
-    // ID signaling that we resolved the branch - ID_STAGE
+    // Signaling that we resolved the branch - ISSUE_STAGE
     output logic resolve_branch_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CSR instruction is valid - ISSUE_STAGE
     input logic csr_valid_i,
-    // TO_BE_COMPLETED - CSR_REGISTERS
+    // CSR address to write - COMMIT_STAGE
     output logic [11:0] csr_addr_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic csr_commit_i,
-    // MULT result is valid - ID_STAGE
+    // MULT instruction is valid - ISSUE_STAGE
     input logic mult_valid_i,
-    // FU is ready - ID_STAGE
+    // LSU is ready - ISSUE_STAGE
     output logic lsu_ready_o,
-    // LSU result is valid - ID_STAGE
+    // LSU instruction is valid - ISSUE_STAGE
     input logic lsu_valid_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Load result is valid - ISSUE_STAGE
     output logic load_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Load result valid - ISSUE_STAGE
     output riscv::xlen_t load_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Load instruction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] load_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Exception generated by load instruction - ISSUE_STAGE
     output exception_t load_exception_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Store result is valid - ISSUe_STAGE
     output logic store_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Store result - ISSUE_STAGE
     output riscv::xlen_t store_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Store instruction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] store_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Exception generated by store instruction - ISSUE_STAGE
     output exception_t store_exception_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic lsu_commit_i,
-    // Commit queue is ready to accept another commit request - COMMIT_STAGE
+    // Commit queue ready to accept another commit request - COMMIT_STAGE
     output logic lsu_commit_ready_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic [TRANS_ID_BITS-1:0] commit_tran_id_i,
@@ -96,49 +96,49 @@ module ex_stage
     input logic stall_st_pending_i,
     // TO_BE_COMPLETED - COMMIT_STAGE
     output logic no_st_pending_o,
-    // TO_BE_COMPLETED - COMMIT_STAGE
+    // Atomic result is valid - COMMIT_STAGE
     input logic amo_valid_commit_i,
-    // FU is ready - ID_STAGE
+    // FU is ready - ISSUE_STAGE
     output logic fpu_ready_o,
-    // Output is ready - ID_STAGE
+    // FPU instruction is ready - ISSUE_STAGE
     input logic fpu_valid_i,
-    // report FP format - ID_STAGE
+    // FPU format - ISSUE_STAGE
     input logic [1:0] fpu_fmt_i,
-    // FP rm - ID_STAGE
+    // FPU rm - ISSUE_STAGE
     input logic [2:0] fpu_rm_i,
-    // FP frm - ID_STAGE
+    // FPU frm - ISSUE_STAGE
     input logic [2:0] fpu_frm_i,
-    // FP precision control - CSR_REGFILE
+    // FPU precision control - CSR_REGFILE
     input logic [6:0] fpu_prec_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FPU transaction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] fpu_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FPU result - ISSUE_STAGE
     output riscv::xlen_t fpu_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FPU valid - ISSUE_STAGE
     output logic fpu_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FPU exception - ISSUE_STAGE
     output exception_t fpu_exception_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF instruction is valid - ISSUE_STAGE
     input logic x_valid_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF is ready - ISSUE_STAGE
     output logic x_ready_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // undecoded instruction - ISSUE_STAGE
     input logic [31:0] x_off_instr_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF transaction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] x_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF exception - ISSUE_STAGE
     output exception_t x_exception_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF result - ISSUE_STAGE
     output riscv::xlen_t x_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF result valid - ISSUE_STAGE
     output logic x_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF write enable - ISSUE_STAGE
     output logic x_we_o,
-    // TO_BE_COMPLETED - SUBSYSTEM
+    // CVXIF request - SUBSYSTEM
     output cvxif_pkg::cvxif_req_t cvxif_req_o,
-    // TO_BE_COMPLETED - SUBSYSTEM
+    // CVXIF response - SUBSYSTEM
     input cvxif_pkg::cvxif_resp_t cvxif_resp_i,
-    // TO_BE_COMPLETED - ACC_DISPATCHER
+    // accelerate port result is valid - ACC_DISPATCHER
     input logic acc_valid_i,
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic enable_translation_i,
@@ -146,13 +146,13 @@ module ex_stage
     input logic en_ld_st_translation_i,
     // TO_BE_COMPLETED - CONTROLLER
     input logic flush_tlb_i,
-    // TO_BE_COMPLETED - CSR_REGFILE
+    // Privilege mode - CSR_REGFILE
     input riscv::priv_lvl_t priv_lvl_i,
-    // TO_BE_COMPLETED - CSR_REGFILE
+    // Privilege level at which load and stores should happen - CSR_REGFILE
     input riscv::priv_lvl_t ld_st_priv_lvl_i,
-    // TO_BE_COMPLETED - CSR_REGFILE
+    // Supervisor user memory - CSR_REGFILE
     input logic sum_i,
-    // TO_BE_COMPLETED - CSR_REGFILE
+    // Make executable readable - CSR_REGFILE
     input logic mxr_i,
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic [riscv::PPNW-1:0] satp_ppn_i,
@@ -183,9 +183,9 @@ module ex_stage
     input riscv::pmpcfg_t [15:0] pmpcfg_i,
     // Report the PMP addresses - CSR_REGFILE
     input logic [15:0][riscv::PLEN-3:0] pmpaddr_i,
-    // Information dedicated to RVFI - SUBSYSTEM
+    // Information dedicated to RVFI - RVFI
     output lsu_ctrl_t rvfi_lsu_ctrl_o,
-    // Information dedicated to RVFI - SUBSYSTEM
+    // Information dedicated to RVFI - RVFI
     output [riscv::PLEN-1:0] rvfi_mem_paddr_o
 );
 

core/id_stage.sv

@@ -32,7 +32,7 @@ module id_stage #(
     output logic fetch_entry_ready_o,
     // Handshake's data between decode and issue - ISSUE
     output ariane_pkg::scoreboard_entry_t issue_entry_o,
-    // instruction value - ISSUE
+    // Instruction value - ISSUE
     output logic [31:0] orig_instr_o,
     // Handshake's valid between decode and issue - ISSUE
     output logic issue_entry_valid_o,
@@ -40,27 +40,27 @@ module id_stage #(
     output logic is_ctrl_flow_o,
     // Handshake's acknowlege between decode and issue - ISSUE
     input logic issue_instr_ack_i,
-    // Information dedicated to RVFI- SUBSYSTEM
+    // Information dedicated to RVFI - RVFI
     output logic rvfi_is_compressed_o,
-    // Report current privilege level - CSR
+    // Current privilege level - CSR_REGFILE
     input riscv::priv_lvl_t priv_lvl_i,
-    // Report floating point extension status - CSR
+    // Floating point extension status - CSR_REGFILE
     input riscv::xs_t fs_i,
-    // Report floating point dynamic rounding mode - CSR
+    // Floating point dynamic rounding mode - CSR_REGFILE
     input logic [2:0] frm_i,
-    // Report vector extension status - CSR
+    // Vector extension status - CSR_REGFILE
     input riscv::xs_t vs_i,
     // Level sensitive (async) interrupts - SUBSYSTEM
     input logic [1:0] irq_i,
-    // TBD - CSR
+    // Interrupt control status - CSR_REGFILE
     input ariane_pkg::irq_ctrl_t irq_ctrl_i,
-    // Report if current mode is debug - CSR
+    // Is current mode debug ? - CSR_REGFILE
     input logic debug_mode_i,
-    // TBD - CSR
+    // Trap virtual memory - CSR_REGFILE
     input logic tvm_i,
-    // TBD - CSR
+    // Timeout wait - CSR_REGFILE
     input logic tw_i,
-    // TBD- CSR
+    // Trap sret - CSR_REGFILE
     input logic tsr_i
 );
   // ID/ISSUE register stage

core/instr_realign.sv

@@ -43,7 +43,7 @@ module instr_realign
     output logic [INSTR_PER_FETCH-1:0] valid_o,
     // Instruction address - FRONTEND
     output logic [INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] addr_o,
-    // Instruction - instr_scan, instr_queue
+    // Instruction - instr_scan&instr_queue
     output logic [INSTR_PER_FETCH-1:0][31:0] instr_o
 );
   // as a maximum we support a fetch width of 64-bit, hence there can be 4 compressed instructions

core/issue_stage.sv

@@ -23,67 +23,67 @@ module issue_stage
     input logic clk_i,
     // Asynchronous reset active low - SUBSYSTEM
     input logic rst_ni,
-    // TO_BE_COMPLETED - PERF_COUNTERS
+    // Is scoreboard full - PERF_COUNTERS
     output logic sb_full_o,
     // TO_BE_COMPLETED - CONTROLLER
     input logic flush_unissued_instr_i,
     // TO_BE_COMPLETED - CONTROLLER
     input logic flush_i,
-    // zero when accelerate port is disable - ACC_DISPATCHER
+    // Stall inserted by Acc dispatcher - ACC_DISPATCHER
     input logic stall_i,
-    // Handshake's data between decode and issue - ID_STAGE
+    // Handshake's data with decode stage - ID_STAGE
     input scoreboard_entry_t decoded_instr_i,
     // instruction value - ID_STAGE
     input logic [31:0] orig_instr_i,
-    // Handshake's valid between decode and issue - ID_STAGE
+    // Handshake's valid with decode stage - ID_STAGE
     input logic decoded_instr_valid_i,
-    // Report if instruction is a control flow instruction - ID_STAGE
+    // Is instruction a control flow instruction - ID_STAGE
     input logic is_ctrl_flow_i,
-    // Handshake's acknowlege between decode and issue - ID_STAGE
+    // Handshake's acknowlege with decode stage - ID_STAGE
     output logic decoded_instr_ack_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // rs1 forwarding - EX_STAGE
     output [riscv::VLEN-1:0] rs1_forwarding_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // rs2 forwarding - EX_STAGE
     output [riscv::VLEN-1:0] rs2_forwarding_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // FU data useful to execute instruction - EX_STAGE
     output fu_data_t fu_data_o,
     // TO_BE_COMPLETED - EX_STAGE
     output logic [riscv::VLEN-1:0] pc_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // Is compressed instruction - EX_STAGE
     output logic is_compressed_instr_o,
     // TO_BE_COMPLETED - EX_STAGE
     input logic flu_ready_i,
-    // TO_BE_COMPLETED - EX_STAGE
+    // ALU FU is valid - EX_STAGE
     output logic alu_valid_o,
     // TO_BE_COMPLETED - EX_STAGE
     input logic resolve_branch_i,
-    // TO_BE_COMPLETED - EX_STAGE
+    // Load store unit FU is ready - EX_STAGE
     input logic lsu_ready_i,
-    // TO_BE_COMPLETED - EX_STAGE
+    // Load store unit FU is valid - EX_STAGE
     output logic lsu_valid_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // Branch unit is valid - EX_STAGE
     output logic branch_valid_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // Information of branch prediction - EX_STAGE
     output branchpredict_sbe_t branch_predict_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // Mult FU is valid - EX_STAGE
     output logic mult_valid_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // FPU FU is ready - EX_STAGE
     input logic fpu_ready_i,
-    // TO_BE_COMPLETED - EX_STAGE
+    // FPU FU is valid - EX_STAGE
     output logic fpu_valid_o,
-    // Report FP fmt field - EX_STAGE
+    // FPU fmt field - EX_STAGE
     output logic [1:0] fpu_fmt_o,
-    // report FP rm field - EX_STAGE
+    // FPU rm field - EX_STAGE
     output logic [2:0] fpu_rm_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // CSR is valid - EX_STAGE
     output logic csr_valid_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // CVXIF FU is valid - EX_STAGE
     output logic x_issue_valid_o,
-    // TO_BE_COMPLETED - EX_STAGE
+    // CVXIF is FU ready - EX_STAGE
     input logic x_issue_ready_i,
-    // TO_BE_COMPLETED - EX_STAGE
+    // CVXIF offloader instruction value - EX_STAGE
     output logic [31:0] x_off_instr_o,
-    // TO_BE_COMPLETED - ACC_DISPATCHER
+    // Issue scoreboard entry - ACC_DISPATCHER
     output scoreboard_entry_t issue_instr_o,
     // TO_BE_COMPLETED - ACC_DISPATCHER
     output logic issue_instr_hs_o,
@@ -93,7 +93,7 @@ module issue_stage
     input bp_resolve_t resolved_branch_i,
     // TO_BE_COMPLETED - EX_STAGE
     input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i,
-    // exception from execute stage or CVXIF offloaded instruction - EX_STAGE
+    // exception from execute stage or CVXIF - EX_STAGE
     input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_i,
     // TO_BE_COMPLETED - EX_STAGE
     input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i,
@@ -113,9 +113,9 @@ module issue_stage
     input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
     // Issue stall - PERF_COUNTERS
     output logic stall_issue_o,
-    // Information dedicated to RVFI - SUBSYSTEM
+    // Information dedicated to RVFI - RVFI
     output logic [TRANS_ID_BITS-1:0] rvfi_issue_pointer_o,
-    // Information dedicated to RVFI - SUBSYSTEM
+    // Information dedicated to RVFI - RVFI
     output logic [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] rvfi_commit_pointer_o
 );
   // ---------------------------------------------------

docs/04_cv32a65x_design/source/architecture.rst

@@ -12,23 +12,27 @@
 Architecture and Modules
 ========================
 
-The CV32A6 v0.1.0 subsystem is composed of 8 modules.
+The CV32A65X is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
+
+For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1GHz depending of technology.
+
+The CV32A65X subsystem is composed of 8 modules.
 
 .. figure:: ../images/subsystems.png
    :name: CV32A6 v0.1.0 modules
    :align: center
    :alt:
 
-   CV32A6 v0.1.0 modules
+   CV32A65X modules
 
 Connections between modules are illustrated in the following block diagram. FRONTEND, DECODE, ISSUE, EXECUTE, COMMIT and CONTROLLER are part of the pipeline. And CACHES implements the instruction and data caches and CSRFILE contains registers.
 
-.. figure:: ../images/CVA6_subsystems.png
-   :name: CVA6 subsystem
+.. figure:: ../images/CV32A65X_subsystems.png
+   :name: CV32A65X subsystem
    :align: center
    :alt:
 
-   CV32A6 v0.1.0 pipeline and modules
+   CV32A65X pipeline and modules
 
 .. toctree::
    :hidden:

docs/04_cv32a65x_design/source/cv32a6_frontend.rst

@@ -15,11 +15,19 @@ FRONTEND Module
 Description
 -----------
 
-The FRONTEND module implements two first stages of the cva6 pipeline, PC gen and Fetch stages.
+The FRONTEND module implements two first stages of the cva6 pipeline,
+PC gen and Fetch stages.
 
-PC gen stage is responsible for generating the next program counter hosting a Branch Target Buffer (BTB) a Branch History Table (BHT) and a Return Address Stack (RAS) to speculate on the branch target address.
+PC gen stage is responsible for generating the next program counter
+hosting a Branch Target Buffer (BTB) a Branch History Table (BHT) and
+a Return Address Stack (RAS) to speculate on the branch target address.
 
-Fetch stage requests data to the CACHE module, realigns the data to store them in instruction queue and transmits the instructions to the DECODE module. FRONTEND can fetch up to 2 instructions per cycles when C extension instructions is used, but as instruction queue limits the data rate, up to one instruction per cycle can be sent to DECODE.
+Fetch stage requests data to the CACHE module, realigns the data to
+store them in instruction queue and transmits the instructions to the
+DECODE module.
+FRONTEND can fetch up to 2 instructions per cycles when
+C extension instructions is used, but as instruction queue limits the
+data rate, up to one instruction per cycle can be sent to DECODE.
 
 The module is connected to:
 
@@ -80,8 +88,8 @@ Memory *and MMU (MMU is not enabled in CV32A6 v0.1.0)* can feedback potential ex
 
 
 
-Architecture and Submodules
----------------------------
+Submodules
+----------
 
 .. figure:: ../images/frontend_modules.png
    :name: FRONTEND submodules
@@ -94,20 +102,16 @@ Architecture and Submodules
 Instr_realign submodule
 ~~~~~~~~~~~~~~~~~~~~~~~
 
-.. include:: port_instr_realign.rst
-
-
 The 32-bit aligned block coming from the CACHE module enters the instr_realign submodule. This submodule extracts the instructions from the 32-bit blocks, up to two instructions because it is possible to fetch two instructions when C extension is used. If the instructions are not compressed, it is possible that the instruction is not aligned on the block size but rather interleaved with two cache blocks. In that case, two cache accesses are needed. The instr_realign submodule provides at maximum one instruction per cycle. Not complete instruction is stored in instr_realign submodule before being provided in the next cycles.
 
 In case of mispredict, flush, replay or branch predict, the instr_realign is re-initialized, the internal register storing the instruction alignment state is reset.
 
+.. include:: port_instr_realign.rst
+
 
 Instr_queue submodule
 ~~~~~~~~~~~~~~~~~~~~~
 
-.. include:: port_instr_queue.rst
-
-
 The instr_queue receives 32bit block from CACHES to create a valid stream of instructions to be decoded (by DECODE), to be issued (by ISSUE) and executed (by EXECUTE). FRONTEND pushes in FIFO to store the instructions and related information needed in case of mispredict or exception: instructions, instruction control flow type, exception, exception address and predicted address. DECODE pops them when decode stage is ready and indicates to the FRONTEND the instruction has been consummed.
 
 The instruction queue contains max 4 instructions.
@@ -118,28 +122,32 @@ If the instruction queue is full, a replay request is sent to inform the fetch m
 
 The instruction queue can be flushed by CONTROLLER.
 
+.. include:: port_instr_queue.rst
 
 
 Instr_scan submodule
 ~~~~~~~~~~~~~~~~~~~~
 
-.. include:: port_instr_scan.rst
-
-
 The instr_scan submodule pre-decodes the fetched instructions, instructions could be compressed or not. The outputs are used by the branch prediction feature. The instr_scan submodule tells if the instruction is compressed and provides the intruction type: branch, jump, return, jalr, imm, call or others.
 
+.. include:: port_instr_scan.rst
+
 
 BHT (Branch History Table) submodule
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. include:: port_bht.rst
 
 
-When a branch instruction is resolved by the EXECUTE, the relative information is stored in the Branch History Table.
+When a branch instruction is resolved by the EXECUTE, the relative
+information is stored in the Branch History Table.
 
 The information is stored in a 1024 entry table.
 
-The Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure.
+The Branch History table is a two-bit saturation counter that takes the
+virtual address of the current fetched instruction by the CACHE.
+It states whether the current branch request should be taken or not.
+The two bit counter is updated by the successive execution of the current
+instructions as shown in the following figure.
 
 .. figure:: ../images/bht.png
    :name: BHT saturation
@@ -150,40 +158,53 @@ The Branch History table is a two-bit saturation counter that takes the virtual
 
 The BHT is not updated if processor is in debug mode.
 
-When a branch instruction is pre-decoded by instr_scan submodule, the BHT informs whether the PC address is in the BHT. In this case, the BHT predicts whether the branch is taken and provides the corresponding target address.
+When a branch instruction is pre-decoded by instr_scan submodule, the BHT
+informs whether the PC address is in the BHT. In this case, the BHT
+predicts whether the branch is taken and provides the corresponding target
+address.
 
 The BHT is never flushed.
 
+.. include:: port_bht.rst
+
 
 BTB (Branch Target Buffer) submodule
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. include:: port_btb.rst
 
-
-When a unconditional jumps to a register (JALR instruction) is mispredicted by the EXECUTE, the relative information is stored into the BTB, that is to say the JALR PC and the target address.
+When a unconditional jumps to a register (JALR instruction) is mispredicted
+by the EXECUTE, the relative information is stored into the BTB, that is
+to say the JALR PC and the target address.
 
 The information is stored in a 8 entry table.
 
 The BTB is not updated if processor is in debug mode.
 
-When a branch instruction is pre-decoded by instr_scan submodule, the BTB informs whether the input PC address is in BTB. In this case, the BTB provides the corresponding target address.
+When a branch instruction is pre-decoded by instr_scan submodule, the BTB
+informs whether the input PC address is in BTB. In this case, the BTB
+provides the corresponding target address.
 
 The BTB is never flushed.
 
+.. include:: port_btb.rst
+
 
 
 RAS (Return Address Stack) submodule
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. include:: port_ras.rst
 
-
-When an unconditional jumps to a known target address (JAL instruction) is consummed by the instr_queue, the next pc after the JAL instruction and the return address are stored into a FIFO.
+When an unconditional jumps to a known target address (JAL instruction)
+is consummed by the instr_queue, the next pc after the JAL instruction
+and the return address are stored into a FIFO.
 
 The RAS FIFO depth is 2.
 
-When a branch instruction is pre-decoded by instr_scan submodule, the RAS informs whether the input PC address is in RAS. In this case, the RAS provides the corresponding target address.
+When a branch instruction is pre-decoded by instr_scan submodule, the
+RAS informs whether the input PC address is in RAS. In this case, the
+RAS provides the corresponding target address.
 
 The RAS is never flushed.
 
+.. include:: port_ras.rst
+

docs/04_cv32a65x_design/source/cva6_commit_stage.rst

@@ -27,3 +27,4 @@ Functionality
 -------------
 
 TO BE COMPLETED
+

docs/04_cv32a65x_design/source/cva6_controller.rst

@@ -27,3 +27,4 @@ Functionality
 -------------
 
 TO BE COMPLETED
+

docs/04_cv32a65x_design/source/cva6_id_stage.rst

@@ -15,15 +15,68 @@ ID_STAGE Module
 Description
 -----------
 
-The ID_STAGE module implements ... TO BE COMPLETED
+The ID_STAGE module implements the decode stage of the pipeline.
+Its main purpose is to decode RISC-V instructions coming from FRONTEND module
+(fetch stage) and send them to the ISSUE_STAGE module (issue stage).
+
+The compressed_decoder module checks whether the incoming instruction is
+compressed and output the corresponding uncompressed instruction.
+Then the decoder module decodes the instruction and send it to the
+issue stage.
+
 
 The module is connected to:
 
-* TO BE COMPLETED
+* CONTROLLER module can flush ID_STAGE decode stage
+* FRONTEND module sends instrution to ID_STAGE module
+* ISSUE module receives the decoded instruction from ID_STAGE module
+* CSR_REGFILE module sends status information about privilege mode, traps, extension support.
 
 .. include:: port_id_stage.rst
 
+
+
 Functionality
 -------------
 
 TO BE COMPLETED
+
+
+Submodules
+----------
+
+.. figure:: ../images/id_stage_modules.png
+   :name: ID_STAGE submodules
+   :align: center
+   :alt:
+
+   ID_STAGE submodules
+
+
+Compressed_decoder
+~~~~~~~~~~~~~~~~~~
+
+The compressed_decoder module decompresses all the compressed
+instructions taking a 16-bit compressed instruction and expanding it
+to its 32-bit equivalent.
+All compressed instructions have a 32-bit equivalent.
+
+.. include:: port_compressed_decoder.rst
+
+Decoder
+~~~~~~~
+
+The decoder module takes the output of compressed_decoder module and decodes
+it.
+It transforms the instruction to the most fundamental control structure
+in pipeline, a scoreboard entry.
+
+The scoreboard entry contains an exception entry which is composed of a
+valid field, a cause and a value called TVAL.
+As TVALEn configuration parameter is zero, the TVAL field is not implemented.
+A potential illegal instruction exception can be detected during decoding.
+If no exception has happened previously in fetch stage, the decoder will
+valid the exception and add the cause and tval value to the scoreboard entry.
+
+.. include:: port_decoder.rst
+

docs/04_cv32a65x_design/source/cva6_issue_stage.rst

@@ -9,13 +9,25 @@
 
 .. _CVA6_ISSUE_STAGE:
 
-ID_STAGE Module
-===============
+ISSUE_STAGE Module
+==================
 
 Description
 -----------
 
-The ISSUE_STAGE module implements ... TO BE COMPLETED
+The execution can be roughly divided into four parts: issue(1),
+read operands(2), execute(3) and write-back(4).
+The ISSUE_STAGE module handles step one, two and four.
+The ISSUE_STAGE module receives the decoded instructions and issues them
+to the various functional units.
+
+A data-structure called scoreboard is used to keep track of data related
+to the issue instruction: which functional unit it is in and which
+register it will write-back to.
+The scoreboard handle the write-back data received from the COMMIT_STAGE module.
+
+Furthermore it contains the CPU’s register file.
+
 
 The module is connected to:
 
@@ -27,3 +39,28 @@ Functionality
 -------------
 
 TO BE COMPLETED
+
+
+Submodules
+----------
+
+.. figure:: ../images/issue_stage_modules.png
+   :name: ISSUE_STAGE submodules
+   :align: center
+   :alt:
+
+   ISSUE_STAGE submodules
+
+Scoreboard
+~~~~~~~~~~
+
+TO BE COMPLETED
+
+.. include:: port_scoreboard.rst
+
+Issue_read_operands
+~~~~~~~~~~~~~~~~~~~
+
+TO BE COMPLETED
+
+.. include:: port_issue_read_operands.rst

docs/04_cv32a65x_design/source/index.rst

@@ -17,7 +17,6 @@ Editor: **Jean Roch Coulon**
    :caption: Contents:
 
    intro
-   overview
    subsystem
    functionality
    architecture

docs/04_cv32a65x_design/source/overview.rst

@@ -1,20 +0,0 @@
-..
-   Copyright 2022 Thales DIS design services SAS
-   Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-   you may not use this file except in compliance with the License.
-   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-   You may obtain a copy of the License at https://solderpad.org/licenses/
-
-   Original Author: Jean-Roch COULON - Thales
-
-
-
-Overview
-========
-
-[TO BE COMPLETED]
-
-The CVA6 core is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
-
-For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1GHz depending of technology.
-

docs/04_cv32a65x_design/source/parameters_cv32a65x.rst

@@ -13,7 +13,7 @@
    :header-rows: 1
 
    * - Name
-     - Description
+     - description
      - Value
 
    * - NrCommitPorts

docs/04_cv32a65x_design/source/port_bht.rst

@@ -14,48 +14,47 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``flush_i``
      - in
+     - Fetch flush request
      - CONTROLLER
      - logic
-     - Fetch flush request
-
-   * - ``debug_mode_i``
-     - in
-     - CSR
-     - logic
-     - Debug mode state
 
    * - ``vpc_i``
      - in
+     - Virtual PC
      - CACHE
      - logic[riscv::VLEN-1:0]
-     - Virtual PC
 
    * - ``bht_update_i``
      - in
+     - Update bht with resolved address
      - EXECUTE
      - ariane_pkg::bht_update_t
-     - Update bht with resolved address
 
    * - ``bht_prediction_o``
      - out
+     - Prediction from bht
      - FRONTEND
      - ariane_pkg::bht_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0]
-     - Prediction from bht
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| As DebugEn = 0,
+|   ``debug_mode_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_btb.rst

@@ -14,48 +14,47 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``flush_i``
      - in
+     - Fetch flush request
      - CONTROLLER
      - logic
-     - Fetch flush request
-
-   * - ``debug_mode_i``
-     - in
-     - CSR
-     - logic
-     - Debug mode state
 
    * - ``vpc_i``
      - in
+     - Virtual PC
      - CACHE
      - logic[riscv::VLEN-1:0]
-     - Virtual PC
 
    * - ``btb_update_i``
      - in
+     - Update BTB with resolved address
      - EXECUTE
      - ariane_pkg::btb_update_t
-     - Update BTB with resolved address
 
    * - ``btb_prediction_o``
      - out
+     - BTB Prediction
      - FRONTEND
      - ariane_pkg::btb_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0]
-     - BTB Prediction
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| As DebugEn = 0,
+|   ``debug_mode_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_commit_stage.rst

@@ -14,186 +14,185 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``halt_i``
      - in
+     - Request to halt the core
      - CONTROLLER
      - logic
-     - Request to halt the core
 
    * - ``flush_dcache_i``
      - in
+     - request to flush dcache, also flush the pipeline
      - CACHE
      - logic
-     - request to flush dcache, also flush the pipeline
 
    * - ``exception_o``
      - out
+     - TO_BE_COMPLETED
      - EX_STAGE
      - exception_t
-     - TO_BE_COMPLETED
 
    * - ``dirty_fp_state_o``
      - out
+     - Mark the F state as dirty
      - CSR_REGFILE
      - logic
-     - Mark the F state as dirty
 
    * - ``single_step_i``
      - in
+     - TO_BE_COMPLETED
      - CSR_REGFILE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``commit_instr_i``
      - in
+     - The instruction we want to commit
      - ISSUE_STAGE
      - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
-     - The instruction we want to commit
 
    * - ``commit_ack_o``
      - out
+     - Acknowledge that we are indeed committing
      - ISSUE_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0]
-     - Acknowledge that we are indeed committing
 
    * - ``waddr_o``
      - out
+     - Register file write address
      - ID_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
-     - Register file write address
 
    * - ``wdata_o``
      - out
+     - Register file write data
      - ID_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0]
-     - Register file write data
 
    * - ``we_gpr_o``
      - out
+     - Register file write enable
      - ID_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0]
-     - Register file write enable
 
    * - ``we_fpr_o``
      - out
+     - Floating point register enable
      - ID_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0]
-     - Floating point register enable
-
-   * - ``amo_resp_i``
-     - in
-     - CACHE
-     - amo_resp_t
-     - Result of AMO operation
 
    * - ``pc_o``
      - out
+     - TO_BE_COMPLETED
      - FRONTEND_CSR
      - logic[riscv::VLEN-1:0]
-     - TO_BE_COMPLETED
 
    * - ``csr_op_o``
      - out
+     - Decoded CSR operation
      - CSR_REGFILE
      - fu_op
-     - Decoded CSR operation
 
    * - ``csr_wdata_o``
      - out
+     - Data to write to CSR
      - CSR_REGFILE
      - riscv::xlen_t
-     - Data to write to CSR
 
    * - ``csr_rdata_i``
      - in
+     - Data to read from CSR
      - CSR_REGFILE
      - riscv::xlen_t
-     - Data to read from CSR
 
    * - ``csr_exception_i``
      - in
+     - Exception or interrupt occurred in CSR stage (the same as commit)
      - CSR_REGFILE
      - exception_t
-     - Exception or interrupt occurred in CSR stage (the same as commit)
 
    * - ``csr_write_fflags_o``
      - out
+     - Write the fflags CSR
      - CSR_REGFILE
      - logic
-     - Write the fflags CSR
 
    * - ``commit_lsu_o``
      - out
+     - Commit the pending store
      - EX_STAGE
      - logic
-     - Commit the pending store
 
    * - ``commit_lsu_ready_i``
      - in
+     - Commit buffer of LSU is ready
      - EX_STAGE
      - logic
-     - Commit buffer of LSU is ready
 
    * - ``commit_tran_id_o``
      - out
+     - Transaction id of first commit port
      - ID_STAGE
      - logic[TRANS_ID_BITS-1:0]
-     - Transaction id of first commit port
 
    * - ``amo_valid_commit_o``
      - out
+     - Valid AMO in commit stage
      - EX_STAGE
      - logic
-     - Valid AMO in commit stage
 
    * - ``no_st_pending_i``
      - in
+     - no store is pending
      - EX_STAGE
      - logic
-     - no store is pending
 
    * - ``commit_csr_o``
      - out
+     - Commit the pending CSR instruction
      - EX_STAGE
      - logic
-     - Commit the pending CSR instruction
 
    * - ``fence_i_o``
      - out
+     - Flush I$ and pipeline
      - CONTROLLER
      - logic
-     - Flush I$ and pipeline
 
    * - ``fence_o``
      - out
+     - Flush D$ and pipeline
      - CONTROLLER
      - logic
-     - Flush D$ and pipeline
 
    * - ``flush_commit_o``
      - out
+     - Request a pipeline flush
      - CONTROLLER
      - logic
-     - Request a pipeline flush
 
    * - ``sfence_vma_o``
      - out
+     - Flush TLBs and pipeline
      - CONTROLLER
      - logic
-     - Flush TLBs and pipeline
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| As RVA = 0,
+|   ``amo_resp_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_compressed_decoder.rst

@@ -0,0 +1,47 @@
+..
+   Copyright 2024 Thales DIS France SAS
+   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: Jean-Roch COULON - Thales
+
+.. _CVA6_compressed_decoder_ports:
+
+.. list-table:: compressed_decoder module IO ports
+   :header-rows: 1
+
+   * - Signal
+     - IO
+     - Description
+     - connexion
+     - Type
+
+   * - ``instr_i``
+     - in
+     - Input instruction coming from fetch stage
+     - FRONTEND
+     - logic[31:0]
+
+   * - ``instr_o``
+     - out
+     - Output instruction in uncompressed format
+     - decoder
+     - logic[31:0]
+
+   * - ``illegal_instr_o``
+     - out
+     - Input instruction is illegal
+     - decoder
+     - logic
+
+   * - ``is_compressed_o``
+     - out
+     - Output instruction is compressed
+     - decoder
+     - logic
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+none

docs/04_cv32a65x_design/source/port_controller.rst

@@ -14,156 +14,146 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``set_pc_commit_o``
      - out
+     - Set PC om PC Gen
      - FRONTEND
      - logic
-     - Set PC om PC Gen
 
    * - ``flush_if_o``
      - out
+     - Flush the IF stage
      - FRONTEND
      - logic
-     - Flush the IF stage
 
    * - ``flush_unissued_instr_o``
      - out
+     - Flush un-issued instructions of the scoreboard
      - FRONTEND
      - logic
-     - Flush un-issued instructions of the scoreboard
 
    * - ``flush_id_o``
      - out
+     - Flush ID stage
      - ID_STAGE
      - logic
-     - Flush ID stage
 
    * - ``flush_ex_o``
      - out
+     - Flush EX stage
      - EX_STAGE
      - logic
-     - Flush EX stage
 
    * - ``flush_bp_o``
      - out
+     - Flush branch predictors
      - FRONTEND
      - logic
-     - Flush branch predictors
 
    * - ``flush_icache_o``
      - out
+     - Flush ICache
      - CACHE
      - logic
-     - Flush ICache
 
    * - ``flush_dcache_o``
      - out
+     - Flush DCache
      - CACHE
      - logic
-     - Flush DCache
 
    * - ``flush_dcache_ack_i``
      - in
+     - Acknowledge the whole DCache Flush
      - CACHE
      - logic
-     - Acknowledge the whole DCache Flush
 
    * - ``flush_tlb_o``
      - out
+     - Flush TLBs
      - EX_STAGE
      - logic
-     - Flush TLBs
 
    * - ``halt_csr_i``
      - in
+     - Halt request from CSR (WFI instruction)
      - CSR_REGFILE
      - logic
-     - Halt request from CSR (WFI instruction)
-
-   * - ``halt_acc_i``
-     - in
-     - ACC_DISPATCHER
-     - logic
-     - Halt request from accelerator dispatcher
 
    * - ``halt_o``
      - out
+     - Halt signal to commit stage
      - COMMIT_STAGE
      - logic
-     - Halt signal to commit stage
 
    * - ``eret_i``
      - in
+     - Return from exception
      - CSR_REGFILE
      - logic
-     - Return from exception
 
    * - ``ex_valid_i``
      - in
-     - FRONTEND
-     - logic
      - We got an exception, flush the pipeline
-
-   * - ``set_debug_pc_i``
-     - in
      - FRONTEND
      - logic
-     - set the debug pc from CSR
 
    * - ``resolved_branch_i``
      - in
+     - We got a resolved branch, check if we need to flush the front-end
      - EX_STAGE
      - bp_resolve_t
-     - We got a resolved branch, check if we need to flush the front-end
 
    * - ``flush_csr_i``
      - in
+     - We got an instruction which altered the CSR, flush the pipeline
      - CSR_REGFILE
      - logic
-     - We got an instruction which altered the CSR, flush the pipeline
 
    * - ``fence_i_i``
      - in
+     - fence.i in
      - ACC_DISPATCH
      - logic
-     - fence.i in
 
    * - ``fence_i``
      - in
+     - fence in
      - ACC_DISPATCH
      - logic
-     - fence in
 
    * - ``sfence_vma_i``
      - in
+     - We got an instruction to flush the TLBs and pipeline
      - COMMIT_STAGE
      - logic
-     - We got an instruction to flush the TLBs and pipeline
 
    * - ``flush_commit_i``
      - in
+     - Flush request from commit stage
      - COMMIT_STAGE
      - logic
-     - Flush request from commit stage
 
-   * - ``flush_acc_i``
-     - in
-     - ACC_DISPATCHER
-     - logic
-     - Flush request from accelerator
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| As EnableAccelerator = 0,
+|   ``halt_acc_i`` input is tied to 0
+|   ``flush_acc_i`` input is tied to 0
+| As DebugEn = 0,
+|   ``set_debug_pc_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_csr_regfile.rst

@@ -14,348 +14,294 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``time_irq_i``
      - in
+     - Timer threw a interrupt
      - SUBSYSTEM
      - logic
-     - Timer threw a interrupt
 
    * - ``flush_o``
      - out
+     - send a flush request out when a CSR with a side effect changes
      - CONTROLLER
      - logic
-     - send a flush request out when a CSR with a side effect changes
 
    * - ``halt_csr_o``
      - out
+     - halt requested
      - CONTROLLER
      - logic
-     - halt requested
 
    * - ``commit_instr_i``
      - in
+     - Instruction to be committed
      - ID_STAGE
      - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
-     - Instruction to be committed
 
    * - ``commit_ack_i``
      - in
+     - Commit acknowledged a instruction -> increase instret CSR
      - COMMIT_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0]
-     - Commit acknowledged a instruction -> increase instret CSR
 
    * - ``boot_addr_i``
      - in
+     - Address from which to start booting, mtvec is set to the same address
      - SUBSYSTEM
      - logic[riscv::VLEN-1:0]
-     - Address from which to start booting, mtvec is set to the same address
 
    * - ``hart_id_i``
      - in
+     - Hart id in a multicore environment (reflected in a CSR)
      - SUBSYSTEM
      - logic[riscv::XLEN-1:0]
-     - Hart id in a multicore environment (reflected in a CSR)
 
    * - ``ex_i``
      - in
+     - We've got an exception from the commit stage, take it
      - COMMIT_STAGE
      - exception_t
-     - We've got an exception from the commit stage, take it
 
    * - ``csr_op_i``
      - in
+     - Operation to perform on the CSR file
      - COMMIT_STAGE
      - fu_op
-     - Operation to perform on the CSR file
 
    * - ``csr_addr_i``
      - in
+     - Address of the register to read/write
      - EX_STAGE
      - logic[11:0]
-     - Address of the register to read/write
 
    * - ``csr_wdata_i``
      - in
+     - Write data in
      - COMMIT_STAGE
      - logic[riscv::XLEN-1:0]
-     - Write data in
 
    * - ``csr_rdata_o``
      - out
+     - Read data out
      - COMMIT_STAGE
      - logic[riscv::XLEN-1:0]
-     - Read data out
 
    * - ``dirty_fp_state_i``
      - in
+     - Mark the FP sate as dirty
      - COMMIT_STAGE
      - logic
-     - Mark the FP sate as dirty
 
    * - ``csr_write_fflags_i``
      - in
+     - Write fflags register e.g.: we are retiring a floating point instruction
      - COMMIT_STAGE
      - logic
-     - Write fflags register e.g.: we are retiring a floating point instruction
-
-   * - ``dirty_v_state_i``
-     - in
-     - ACC_DISPATCHER
-     - logic
-     - Mark the V state as dirty
 
    * - ``pc_i``
      - in
+     - PC of instruction accessing the CSR
      - COMMIT_STAGE
      - logic[riscv::VLEN-1:0]
-     - PC of instruction accessing the CSR
 
    * - ``csr_exception_o``
      - out
+     - attempts to access a CSR without appropriate privilege
      - COMMIT_STAGE
      - exception_t
-     - attempts to access a CSR without appropriate privilege
 
    * - ``epc_o``
      - out
+     - Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly
      - FRONTEND
      - logic[riscv::VLEN-1:0]
-     - Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly
 
    * - ``eret_o``
      - out
+     - Return from exception, set the PC of epc_o
      - FRONTEND
      - logic
-     - Return from exception, set the PC of epc_o
 
    * - ``trap_vector_base_o``
      - out
+     - Output base of exception vector, correct CSR is output (mtvec, stvec)
      - FRONTEND
      - logic[riscv::VLEN-1:0]
-     - Output base of exception vector, correct CSR is output (mtvec, stvec)
 
    * - ``priv_lvl_o``
      - out
+     - Current privilege level the CPU is in
      - EX_STAGE
      - riscv::priv_lvl_t
-     - Current privilege level the CPU is in
-
-   * - ``acc_fflags_ex_i``
-     - in
-     - ACC_DISPATCHER
-     - logic[4:0]
-     - Imprecise FP exception from the accelerator (fcsr.fflags format)
-
-   * - ``acc_fflags_ex_valid_i``
-     - in
-     - ACC_DISPATCHER
-     - logic
-     - An FP exception from the accelerator occurred
 
    * - ``fs_o``
      - out
+     - Floating point extension status
      - ID_STAGE
      - riscv::xs_t
-     - Floating point extension status
 
    * - ``fflags_o``
      - out
+     - Floating-Point Accured Exceptions
      - COMMIT_STAGE
      - logic[4:0]
-     - Floating-Point Accured Exceptions
 
    * - ``frm_o``
      - out
+     - Floating-Point Dynamic Rounding Mode
      - EX_STAGE
      - logic[2:0]
-     - Floating-Point Dynamic Rounding Mode
 
    * - ``fprec_o``
      - out
+     - Floating-Point Precision Control
      - EX_STAGE
      - logic[6:0]
-     - Floating-Point Precision Control
 
    * - ``vs_o``
      - out
+     - Vector extension status
      - ID_STAGE
      - riscv::xs_t
-     - Vector extension status
 
    * - ``irq_ctrl_o``
      - out
+     - interrupt management to id stage
      - ID_STAGE
      - irq_ctrl_t
-     - interrupt management to id stage
 
    * - ``en_translation_o``
      - out
+     - enable VA translation
      - EX_STAGE
      - logic
-     - enable VA translation
 
    * - ``en_ld_st_translation_o``
      - out
+     - enable VA translation for load and stores
      - EX_STAGE
      - logic
-     - enable VA translation for load and stores
 
    * - ``ld_st_priv_lvl_o``
      - out
+     - Privilege level at which load and stores should happen
      - EX_STAGE
      - riscv::priv_lvl_t
-     - Privilege level at which load and stores should happen
 
    * - ``sum_o``
      - out
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``mxr_o``
      - out
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``satp_ppn_o``
      - out
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[riscv::PPNW-1:0]
-     - TO_BE_COMPLETED
 
    * - ``asid_o``
      - out
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[AsidWidth-1:0]
-     - TO_BE_COMPLETED
 
    * - ``irq_i``
      - in
+     - external interrupt in
      - SUBSYSTEM
      - logic[1:0]
-     - external interrupt in
 
    * - ``ipi_i``
      - in
+     - inter processor interrupt -> connected to machine mode sw
      - SUBSYSTEM
      - logic
-     - inter processor interrupt -> connected to machine mode sw
-
-   * - ``debug_req_i``
-     - in
-     - ID_STAGE
-     - logic
-     - debug request in
 
    * - ``set_debug_pc_o``
      - out
+     - TO_BE_COMPLETED
      - FRONTEND
      - logic
-     - TO_BE_COMPLETED
 
    * - ``tvm_o``
      - out
+     - trap virtual memory
      - ID_STAGE
      - logic
-     - trap virtual memory
 
    * - ``tw_o``
      - out
+     - timeout wait
      - ID_STAGE
      - logic
-     - timeout wait
 
    * - ``tsr_o``
      - out
+     - trap sret
      - ID_STAGE
      - logic
-     - trap sret
 
    * - ``debug_mode_o``
      - out
+     - we are in debug mode -> that will change some decoding
      - EX_STAGE
      - logic
-     - we are in debug mode -> that will change some decoding
 
    * - ``single_step_o``
      - out
+     - we are in single-step mode
      - COMMIT_STAGE
      - logic
-     - we are in single-step mode
 
    * - ``icache_en_o``
      - out
+     - L1 ICache Enable
      - CACHE
      - logic
-     - L1 ICache Enable
 
    * - ``dcache_en_o``
      - out
+     - L1 DCache Enable
      - CACHE
      - logic
-     - L1 DCache Enable
 
-   * - ``acc_cons_en_o``
-     - out
-     - ACC_DISPATCHER
-     - logic
-     - Accelerator memory consistent mode
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
 
-   * - ``perf_addr_o``
-     - out
-     - PERF_COUNTERS
-     - logic[11:0]
-     - read/write address to performance counter module
-
-   * - ``perf_data_o``
-     - out
-     - PERF_COUNTERS
-     - logic[riscv::XLEN-1:0]
-     - write data to performance counter module
-
-   * - ``perf_data_i``
-     - in
-     - PERF_COUNTERS
-     - logic[riscv::XLEN-1:0]
-     - read data from performance counter module
-
-   * - ``perf_we_o``
-     - out
-     - PERF_COUNTERS
-     - logic
-     - TO_BE_COMPLETED
-
-   * - ``pmpcfg_o``
-     - out
-     - ACC_DISPATCHER
-     - riscv::pmpcfg_t[15:0]
-     - PMP configuration containing pmpcfg for max 16 PMPs
-
-   * - ``pmpaddr_o``
-     - out
-     - ACC_DISPATCHER
-     - logic[15:0][riscv::PLEN-3:0]
-     - PMP addresses
-
-   * - ``mcountinhibit_o``
-     - out
-     - PERF_COUNTERS
-     - logic[31:0]
-     - TO_BE_COMPLETED
+| As EnableAccelerator = 0,
+|   ``dirty_v_state_i`` input is tied to 0
+|   ``acc_fflags_ex_i`` input is tied to 0
+|   ``acc_fflags_ex_valid_i`` input is tied to 0
+|   ``acc_cons_en_o`` output is tied to 0
+|   ``pmpcfg_o`` output is tied to 0
+|   ``pmpaddr_o`` output is tied to 0
+| As DebugEn = 0,
+|   ``debug_req_i`` input is tied to 0
+| As PerfCounterEn = 0,
+|   ``perf_addr_o`` output is tied to 0
+|   ``perf_data_o`` output is tied to 0
+|   ``perf_data_i`` input is tied to 0
+|   ``perf_we_o`` output is tied to 0
+|   ``mcountinhibit_o`` output is tied to 0

docs/04_cv32a65x_design/source/port_cva6.rst

@@ -14,84 +14,83 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``boot_addr_i``
      - in
+     - Reset boot address
      - SUBSYSTEM
      - logic[riscv::VLEN-1:0]
-     - Reset boot address
 
    * - ``hart_id_i``
      - in
+     - Hard ID reflected as CSR
      - SUBSYSTEM
      - logic[riscv::XLEN-1:0]
-     - Hard ID reflected as CSR
 
    * - ``irq_i``
      - in
+     - Level sensitive (async) interrupts
      - SUBSYSTEM
      - logic[1:0]
-     - Level sensitive (async) interrupts
 
    * - ``ipi_i``
      - in
+     - Inter-processor (async) interrupt
      - SUBSYSTEM
      - logic
-     - Inter-processor (async) interrupt
 
    * - ``time_irq_i``
      - in
-     - SUBSYSTEM
-     - logic
      - Timer (async) interrupt
-
-   * - ``debug_req_i``
-     - in
      - SUBSYSTEM
      - logic
-     - Debug (async) request
 
    * - ``rvfi_probes_o``
      - out
+     - Probes to build RVFI, can be left open when not used
      - SUBSYSTEM
      - rvfi_probes_t
-     - Probes to build RVFI, can be left open when not used
 
    * - ``cvxif_req_o``
      - out
+     - CVXIF request
      - SUBSYSTEM
      - cvxif_req_t
-     - CVXIF request
 
    * - ``cvxif_resp_i``
      - in
+     - CVXIF response
      - SUBSYSTEM
      - cvxif_resp_t
-     - CVXIF response
 
    * - ``noc_req_o``
      - out
+     - noc request, can be AXI or OpenPiton
      - SUBSYSTEM
      - noc_req_t
-     - noc request, can be AXI or OpenPiton
 
    * - ``noc_resp_i``
      - in
+     - noc response, can be AXI or OpenPiton
      - SUBSYSTEM
      - noc_resp_t
-     - noc response, can be AXI or OpenPiton
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| As DebugEn = 0,
+|   ``debug_req_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_decoder.rst

@@ -0,0 +1,122 @@
+..
+   Copyright 2024 Thales DIS France SAS
+   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: Jean-Roch COULON - Thales
+
+.. _CVA6_decoder_ports:
+
+.. list-table:: decoder module IO ports
+   :header-rows: 1
+
+   * - Signal
+     - IO
+     - Description
+     - connexion
+     - Type
+
+   * - ``pc_i``
+     - in
+     - PC from fetch stage
+     - FRONTEND
+     - logic[riscv::VLEN-1:0]
+
+   * - ``is_compressed_i``
+     - in
+     - Is a compressed instruction
+     - compressed_decoder
+     - logic
+
+   * - ``compressed_instr_i``
+     - in
+     - Compressed form of instruction
+     - FRONTEND
+     - logic[15:0]
+
+   * - ``is_illegal_i``
+     - in
+     - Illegal compressed instruction
+     - compressed_decoder
+     - logic
+
+   * - ``instruction_i``
+     - in
+     - Instruction from fetch stage
+     - FRONTEND
+     - logic[31:0]
+
+   * - ``branch_predict_i``
+     - in
+     - Is a branch predict instruction
+     - FRONTEND
+     - branchpredict_sbe_t
+
+   * - ``ex_i``
+     - in
+     - If an exception occured in fetch stage
+     - FRONTEND
+     - exception_t
+
+   * - ``irq_i``
+     - in
+     - Level sensitive (async) interrupts
+     - SUBSYSTEM
+     - logic[1:0]
+
+   * - ``irq_ctrl_i``
+     - in
+     - Interrupt control status
+     - CSR_REGFILE
+     - irq_ctrl_t
+
+   * - ``tvm_i``
+     - in
+     - Trap virtual memory
+     - CSR_REGFILE
+     - logic
+
+   * - ``tw_i``
+     - in
+     - Timeout wait
+     - CSR_REGFILE
+     - logic
+
+   * - ``tsr_i``
+     - in
+     - Trap sret
+     - CSR_REGFILE
+     - logic
+
+   * - ``instruction_o``
+     - out
+     - Instruction to be added to scoreboard entry
+     - ISSUE_STAGE
+     - scoreboard_entry_t
+
+   * - ``orig_instr_o``
+     - out
+     - Instruction
+     - ISSUE_STAGE
+     - logic[31:0]
+
+   * - ``is_control_flow_instr_o``
+     - out
+     - Is a control flow instruction
+     - ISSUE_STAGE
+     - logic
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| As DebugEn = 0,
+|   ``debug_req_i`` input is tied to 0
+|   ``debug_mode_i`` input is tied to 0
+| As PRIV = MachineOnly,
+|   ``priv_lvl_i`` input is tied to MachineMode
+| As RVF = 0,
+|   ``fs_i`` input is tied to 0
+|   ``frm_i`` input is tied to 0
+| As RVV = 0,
+|   ``vs_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_ex_stage.rst

@@ -14,504 +14,400 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``flush_i``
      - in
+     - Fetch flush request
      - CONTROLLER
      - logic
-     - Fetch flush request
-
-   * - ``debug_mode_i``
-     - in
-     - CSR_REGFILE
-     - logic
-     - TO_BE_COMPLETED
 
    * - ``rs1_forwarding_i``
      - in
+     - rs1 forwarding
      - ID_STAGE
      - logic[riscv::VLEN-1:0]
-     - TO_BE_COMPLETED
 
    * - ``rs2_forwarding_i``
      - in
+     - rs2 forwarding
      - ID_STAGE
      - logic[riscv::VLEN-1:0]
-     - TO_BE_COMPLETED
 
    * - ``fu_data_i``
      - in
+     - FU data useful to execute instruction
      - ID_STAGE
      - fu_data_t
-     - TO_BE_COMPLETED
 
    * - ``pc_i``
      - in
+     - PC of the current instruction
      - ID_STAGE
      - logic[riscv::VLEN-1:0]
-     - PC of the current instruction
 
    * - ``is_compressed_instr_i``
      - in
+     - Report whether isntruction is compressed
      - ID_STAGE
      - logic
-     - Report whether isntruction is compressed
 
    * - ``flu_result_o``
      - out
+     - TO_BE_COMPLETED
      - ID_STAGE
      - riscv::xlen_t
-     - TO_BE_COMPLETED
 
    * - ``flu_trans_id_o``
      - out
+     - ID of the scoreboard entry at which a=to write back
      - ID_STAGE
      - logic[TRANS_ID_BITS-1:0]
-     - ID of the scoreboard entry at which a=to write back
 
    * - ``flu_exception_o``
      - out
+     - TO_BE_COMPLETED
      - ID_STAGE
      - exception_t
-     - TO_BE_COMPLETED
 
    * - ``flu_ready_o``
      - out
+     - FLU is ready
      - ID_STAGE
      - logic
-     - FLU is ready
 
    * - ``flu_valid_o``
      - out
+     - FLU result is valid
      - ID_STAGE
      - logic
-     - FLU result is valid
 
    * - ``alu_valid_i``
      - in
+     - ALU result is valid
      - ID_STAGE
      - logic
-     - ALU result is valid
 
    * - ``branch_valid_i``
      - in
+     - Branch unit result is valid
      - ID_STAGE
      - logic
-     - Branch unit result is valid
 
    * - ``branch_predict_i``
      - in
+     - Information of branch prediction
      - ID_STAGE
      - branchpredict_sbe_t
-     - TO_BE_COMPLETED
 
    * - ``resolved_branch_o``
      - out
-     - none
+     - The branch engine uses the write back from the ALU
+     - several_modules
      - bp_resolve_t
-     - none
 
    * - ``resolve_branch_o``
      - out
+     - ID signaling that we resolved the branch
      - ID_STAGE
      - logic
-     - ID signaling that we resolved the branch
 
    * - ``csr_valid_i``
      - in
+     - CSR result is valid
      - ID_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``csr_addr_o``
      - out
+     - TO_BE_COMPLETED
      - CSR_REGISTERS
      - logic[11:0]
-     - TO_BE_COMPLETED
 
    * - ``csr_commit_i``
      - in
+     - TO_BE_COMPLETED
      - COMMIT_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``mult_valid_i``
      - in
+     - MULT result is valid
      - ID_STAGE
      - logic
-     - MULT result is valid
 
    * - ``lsu_ready_o``
      - out
+     - FU is ready
      - ID_STAGE
      - logic
-     - FU is ready
 
    * - ``lsu_valid_i``
      - in
+     - LSU result is valid
      - ID_STAGE
      - logic
-     - LSU result is valid
 
    * - ``load_valid_o``
      - out
+     - Load result is valid
      - ID_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``load_result_o``
      - out
+     - Load result valid
      - ID_STAGE
      - riscv::xlen_t
-     - TO_BE_COMPLETED
 
    * - ``load_trans_id_o``
      - out
+     - Load instruction ID
      - ID_STAGE
      - logic[TRANS_ID_BITS-1:0]
-     - TO_BE_COMPLETED
 
    * - ``load_exception_o``
      - out
+     - Exception generated by load instruction
      - ID_STAGE
      - exception_t
-     - TO_BE_COMPLETED
 
    * - ``store_valid_o``
      - out
+     - Store result is valid
      - ID_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``store_result_o``
      - out
+     - Store result
      - ID_STAGE
      - riscv::xlen_t
-     - TO_BE_COMPLETED
 
    * - ``store_trans_id_o``
      - out
+     - Store instruction ID
      - ID_STAGE
      - logic[TRANS_ID_BITS-1:0]
-     - TO_BE_COMPLETED
 
    * - ``store_exception_o``
      - out
+     - Exception generated by store instruction
      - ID_STAGE
      - exception_t
-     - TO_BE_COMPLETED
 
    * - ``lsu_commit_i``
      - in
+     - TO_BE_COMPLETED
      - COMMIT_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``lsu_commit_ready_o``
      - out
+     - Commit queue ready to accept another commit request
      - COMMIT_STAGE
      - logic
-     - Commit queue is ready to accept another commit request
 
    * - ``commit_tran_id_i``
      - in
+     - TO_BE_COMPLETED
      - COMMIT_STAGE
      - logic[TRANS_ID_BITS-1:0]
-     - TO_BE_COMPLETED
-
-   * - ``stall_st_pending_i``
-     - in
-     - ACC_DISPATCHER
-     - logic
-     - TO_BE_COMPLETED
 
    * - ``no_st_pending_o``
      - out
+     - TO_BE_COMPLETED
      - COMMIT_STAGE
      - logic
-     - TO_BE_COMPLETED
-
-   * - ``amo_valid_commit_i``
-     - in
-     - COMMIT_STAGE
-     - logic
-     - TO_BE_COMPLETED
-
-   * - ``fpu_ready_o``
-     - out
-     - ID_STAGE
-     - logic
-     - FU is ready
-
-   * - ``fpu_valid_i``
-     - in
-     - ID_STAGE
-     - logic
-     - Output is ready
-
-   * - ``fpu_fmt_i``
-     - in
-     - ID_STAGE
-     - logic[1:0]
-     - report FP format
-
-   * - ``fpu_rm_i``
-     - in
-     - ID_STAGE
-     - logic[2:0]
-     - FP rm
-
-   * - ``fpu_frm_i``
-     - in
-     - ID_STAGE
-     - logic[2:0]
-     - FP frm
-
-   * - ``fpu_prec_i``
-     - in
-     - CSR_REGFILE
-     - logic[6:0]
-     - FP precision control
-
-   * - ``fpu_trans_id_o``
-     - out
-     - ID_STAGE
-     - logic[TRANS_ID_BITS-1:0]
-     - TO_BE_COMPLETED
-
-   * - ``fpu_result_o``
-     - out
-     - ID_STAGE
-     - riscv::xlen_t
-     - TO_BE_COMPLETED
-
-   * - ``fpu_valid_o``
-     - out
-     - ID_STAGE
-     - logic
-     - TO_BE_COMPLETED
-
-   * - ``fpu_exception_o``
-     - out
-     - ID_STAGE
-     - exception_t
-     - TO_BE_COMPLETED
 
    * - ``x_valid_i``
      - in
-     - ID_STAGE
+     - CVXIF instruction is valid
+     - ISSUE_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``x_ready_o``
      - out
-     - ID_STAGE
+     - CVXIF is ready
+     - ISSUE_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``x_off_instr_i``
      - in
+     - TO_BE_COMPLETED
      - ID_STAGE
      - logic[31:0]
-     - TO_BE_COMPLETED
 
    * - ``x_trans_id_o``
      - out
+     - TO_BE_COMPLETED
      - ID_STAGE
      - logic[TRANS_ID_BITS-1:0]
-     - TO_BE_COMPLETED
 
    * - ``x_exception_o``
      - out
+     - TO_BE_COMPLETED
      - ID_STAGE
      - exception_t
-     - TO_BE_COMPLETED
 
    * - ``x_result_o``
      - out
+     - TO_BE_COMPLETED
      - ID_STAGE
      - riscv::xlen_t
-     - TO_BE_COMPLETED
 
    * - ``x_valid_o``
      - out
+     - TO_BE_COMPLETED
      - ID_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``x_we_o``
      - out
+     - TO_BE_COMPLETED
      - ID_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``cvxif_req_o``
      - out
+     - TO_BE_COMPLETED
      - SUBSYSTEM
      - cvxif_pkg::cvxif_req_t
-     - TO_BE_COMPLETED
 
    * - ``cvxif_resp_i``
      - in
+     - TO_BE_COMPLETED
      - SUBSYSTEM
      - cvxif_pkg::cvxif_resp_t
-     - TO_BE_COMPLETED
-
-   * - ``acc_valid_i``
-     - in
-     - ACC_DISPATCHER
-     - logic
-     - TO_BE_COMPLETED
 
    * - ``enable_translation_i``
      - in
+     - TO_BE_COMPLETED
      - CSR_REGFILE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``en_ld_st_translation_i``
      - in
+     - TO_BE_COMPLETED
      - CSR_REGFILE
      - logic
-     - TO_BE_COMPLETED
-
-   * - ``flush_tlb_i``
-     - in
-     - CONTROLLER
-     - logic
-     - TO_BE_COMPLETED
-
-   * - ``priv_lvl_i``
-     - in
-     - CSR_REGFILE
-     - riscv::priv_lvl_t
-     - TO_BE_COMPLETED
-
-   * - ``ld_st_priv_lvl_i``
-     - in
-     - CSR_REGFILE
-     - riscv::priv_lvl_t
-     - TO_BE_COMPLETED
 
    * - ``sum_i``
      - in
+     - Supervisor user memory
      - CSR_REGFILE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``mxr_i``
      - in
+     - Make executable readable
      - CSR_REGFILE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``satp_ppn_i``
      - in
+     - TO_BE_COMPLETED
      - CSR_REGFILE
      - logic[riscv::PPNW-1:0]
-     - TO_BE_COMPLETED
 
    * - ``asid_i``
      - in
+     - TO_BE_COMPLETED
      - CSR_REGFILE
      - logic[ASID_WIDTH-1:0]
-     - TO_BE_COMPLETED
 
    * - ``icache_areq_i``
      - in
+     - icache translation response
      - CACHE
      - icache_arsp_t
-     - icache translation response
 
    * - ``icache_areq_o``
      - out
+     - icache translation request
      - CACHE
      - icache_areq_t
-     - icache translation request
 
    * - ``dcache_req_ports_i``
      - in
+     - TO_BE_COMPLETED
      - CACHE
      - dcache_req_o_t[2:0]
-     - TO_BE_COMPLETED
 
    * - ``dcache_req_ports_o``
      - out
+     - TO_BE_COMPLETED
      - CACHE
      - dcache_req_i_t[2:0]
-     - TO_BE_COMPLETED
 
    * - ``dcache_wbuffer_empty_i``
      - in
+     - TO_BE_COMPLETED
      - CACHE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``dcache_wbuffer_not_ni_i``
      - in
-     - CACHE
-     - logic
      - TO_BE_COMPLETED
-
-   * - ``amo_req_o``
-     - out
      - CACHE
-     - amo_req_t
-     - AMO request
-
-   * - ``amo_resp_i``
-     - in
-     - CACHE
-     - amo_resp_t
-     - AMO response from cache
-
-   * - ``itlb_miss_o``
-     - out
-     - PERF_COUNTERS
      - logic
-     - To count the instruction TLB misses
-
-   * - ``dtlb_miss_o``
-     - out
-     - PERF_COUNTERS
-     - logic
-     - To count the data TLB misses
 
    * - ``pmpcfg_i``
      - in
+     - Report the PMP configuration
      - CSR_REGFILE
      - riscv::pmpcfg_t[15:0]
-     - Report the PMP configuration
 
    * - ``pmpaddr_i``
      - in
+     - Report the PMP addresses
      - CSR_REGFILE
      - logic[15:0][riscv::PLEN-3:0]
-     - Report the PMP addresses
 
-   * - ``rvfi_lsu_ctrl_o``
-     - out
-     - SUBSYSTEM
-     - lsu_ctrl_t
-     - Information dedicated to RVFI
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
 
-   * - ``rvfi_mem_paddr_o``
-     - out
-     - SUBSYSTEM
-     - [riscv::PLEN-1:0]
-     - Information dedicated to RVFI
+| As DebugEn = 0,
+|   ``debug_mode_i`` input is tied to 0
+| As EnableAccelerator = 0,
+|   ``stall_st_pending_i`` input is tied to 0
+|   ``acc_valid_i`` input is tied to 0
+| As RVA = 0,
+|   ``amo_valid_commit_i`` input is tied to 0
+|   ``amo_req_o`` output is tied to 0
+|   ``amo_resp_i`` input is tied to 0
+| As RVF = 0,
+|   ``fpu_ready_o`` output is tied to 0
+|   ``fpu_valid_i`` input is tied to 0
+|   ``fpu_fmt_i`` input is tied to 0
+|   ``fpu_rm_i`` input is tied to 0
+|   ``fpu_frm_i`` input is tied to 0
+|   ``fpu_prec_i`` input is tied to 0
+|   ``fpu_trans_id_o`` output is tied to 0
+|   ``fpu_result_o`` output is tied to 0
+|   ``fpu_valid_o`` output is tied to 0
+|   ``fpu_exception_o`` output is tied to 0
+| As MMUPresent = 0,
+|   ``flush_tlb_i`` input is tied to 0
+| As PRIV = MachineOnly,
+|   ``priv_lvl_i`` input is tied to MachineMode
+|   ``ld_st_priv_lvl_i`` input is tied to MAchineMode
+| As PerfCounterEn = 0,
+|   ``itlb_miss_o`` output is tied to 0
+|   ``dtlb_miss_o`` output is tied to 0
+| As IsRVFI = 0,
+|   ``rvfi_lsu_ctrl_o`` output is tied to 0
+|   ``rvfi_mem_paddr_o`` output is tied to 0

docs/04_cv32a65x_design/source/port_frontend.rst

@@ -14,126 +14,116 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``flush_i``
      - in
+     - Fetch flush request
      - CONTROLLER
      - logic
-     - Fetch flush request
-
-   * - ``flush_bp_i``
-     - in
-     - zero
-     - logic
-     - flush branch prediction
 
    * - ``halt_i``
      - in
+     - halt commit stage
      - CONTROLLER
      - logic
-     - halt commit stage
-
-   * - ``debug_mode_i``
-     - in
-     - CSR
-     - logic
-     - Debug mode state
 
    * - ``boot_addr_i``
      - in
+     - Next PC when reset
      - SUBSYSTEM
      - logic[riscv::VLEN-1:0]
-     - Next PC when reset
 
    * - ``resolved_branch_i``
      - in
+     - mispredict event and next PC
      - EXECUTE
      - bp_resolve_t
-     - mispredict event and next PC
 
    * - ``set_pc_commit_i``
      - in
+     - Set the PC coming from COMMIT as next PC
      - CONTROLLER
      - logic
-     - Set the PC coming from COMMIT as next PC
 
    * - ``pc_commit_i``
      - in
+     - Next PC when flushing pipeline
      - COMMIT
      - logic[riscv::VLEN-1:0]
-     - Next PC when flushing pipeline
 
    * - ``epc_i``
      - in
+     - Next PC when returning from exception
      - CSR
      - logic[riscv::VLEN-1:0]
-     - Next PC when returning from exception
 
    * - ``eret_i``
      - in
+     - Return from exception event
      - CSR
      - logic
-     - Return from exception event
 
    * - ``trap_vector_base_i``
      - in
+     - Next PC when jumping into exception
      - CSR
      - logic[riscv::VLEN-1:0]
-     - Next PC when jumping into exception
 
    * - ``ex_valid_i``
      - in
+     - Exception event
      - COMMIT
      - logic
-     - Exception event
-
-   * - ``set_debug_pc_i``
-     - in
-     - CSR
-     - logic
-     - Debug event
 
    * - ``icache_dreq_o``
      - out
+     - Handshake between CACHE and FRONTEND (fetch)
      - CACHES
      - icache_dreq_t
-     - Handshake between CACHE and FRONTEND (fetch)
 
    * - ``icache_dreq_i``
      - in
+     - Handshake between CACHE and FRONTEND (fetch)
      - CACHES
      - icache_drsp_t
-     - Handshake between CACHE and FRONTEND (fetch)
 
    * - ``fetch_entry_o``
      - out
+     - Handshake's data between fetch and decode
      - ID_STAGE
      - fetch_entry_t
-     - Handshake's data between fetch and decode
 
    * - ``fetch_entry_valid_o``
      - out
+     - Handshake's valid between fetch and decode
      - ID_STAGE
      - logic
-     - Handshake's valid between fetch and decode
 
    * - ``fetch_entry_ready_i``
      - in
+     - Handshake's ready between fetch and decode
      - ID_STAGE
      - logic
-     - Handshake's ready between fetch and decode
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| For any HW configuration,
+|   ``flush_bp_i`` input is tied to zero
+| As DebugEn = 0,
+|   ``debug_mode_i`` input is tied to 0
+|   ``set_debug_pc_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_id_stage.rst

@@ -14,144 +14,117 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``flush_i``
      - in
+     - Fetch flush request
      - CONTROLLER
      - logic
-     - Fetch flush request
-
-   * - ``debug_req_i``
-     - in
-     - SUBSYSTEM
-     - logic
-     - Debug (async) request
 
    * - ``fetch_entry_i``
      - in
+     - Handshake's data between fetch and decode
      - FRONTEND
      - ariane_pkg::fetch_entry_t
-     - Handshake's data between fetch and decode
 
    * - ``fetch_entry_valid_i``
      - in
+     - Handshake's valid between fetch and decode
      - FRONTEND
      - logic
-     - Handshake's valid between fetch and decode
 
    * - ``fetch_entry_ready_o``
      - out
+     - Handshake's ready between fetch and decode
      - FRONTEND
      - logic
-     - Handshake's ready between fetch and decode
 
    * - ``issue_entry_o``
      - out
+     - Handshake's data between decode and issue
      - ISSUE
      - ariane_pkg::scoreboard_entry_t
-     - Handshake's data between decode and issue
 
    * - ``orig_instr_o``
      - out
+     - Instruction value
      - ISSUE
      - logic[31:0]
-     - instruction value
 
    * - ``issue_entry_valid_o``
      - out
+     - Handshake's valid between decode and issue
      - ISSUE
      - logic
-     - Handshake's valid between decode and issue
 
    * - ``is_ctrl_flow_o``
      - out
+     - Report if instruction is a control flow instruction
      - ISSUE
      - logic
-     - Report if instruction is a control flow instruction
 
    * - ``issue_instr_ack_i``
      - in
+     - Handshake's acknowlege between decode and issue
      - ISSUE
      - logic
-     - Handshake's acknowlege between decode and issue
-
-   * - ``rvfi_is_compressed_o``
-     - out
-     - none
-     - logic
-     - none
-
-   * - ``priv_lvl_i``
-     - in
-     - CSR
-     - riscv::priv_lvl_t
-     - Report current privilege level
-
-   * - ``fs_i``
-     - in
-     - CSR
-     - riscv::xs_t
-     - Report floating point extension status
-
-   * - ``frm_i``
-     - in
-     - CSR
-     - logic[2:0]
-     - Report floating point dynamic rounding mode
-
-   * - ``vs_i``
-     - in
-     - CSR
-     - riscv::xs_t
-     - Report vector extension status
 
    * - ``irq_i``
      - in
+     - Level sensitive (async) interrupts
      - SUBSYSTEM
      - logic[1:0]
-     - Level sensitive (async) interrupts
 
    * - ``irq_ctrl_i``
      - in
-     - CSR
+     - Interrupt control status
+     - CSR_REGFILE
      - ariane_pkg::irq_ctrl_t
-     - TBD
-
-   * - ``debug_mode_i``
-     - in
-     - CSR
-     - logic
-     - Report if current mode is debug
 
    * - ``tvm_i``
      - in
-     - CSR
+     - Trap virtual memory
+     - CSR_REGFILE
      - logic
-     - TBD
 
    * - ``tw_i``
      - in
-     - CSR
+     - Timeout wait
+     - CSR_REGFILE
      - logic
-     - TBD
 
    * - ``tsr_i``
      - in
-     - none
+     - Trap sret
+     - CSR_REGFILE
      - logic
-     - none
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| As DebugEn = 0,
+|   ``debug_req_i`` input is tied to 0
+|   ``debug_mode_i`` input is tied to 0
+| As IsRVFI = 0,
+|   ``rvfi_is_compressed_o`` output is tied to 0
+| As PRIV = MachineOnly,
+|   ``priv_lvl_i`` input is tied to MachineMode
+| As RVF = 0,
+|   ``fs_i`` input is tied to 0
+|   ``frm_i`` input is tied to 0
+| As RVV = 0,
+|   ``vs_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_instr_queue.rst

@@ -14,108 +14,112 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``flush_i``
      - in
+     - Fetch flush request
      - CONTROLLER
      - logic
-     - Fetch flush request
 
    * - ``instr_i``
      - in
+     - Instruction
      - instr_realign
      - logic[ariane_pkg::INSTR_PER_FETCH-1:0][31:0]
-     - Instruction
 
    * - ``addr_i``
      - in
+     - Instruction address
      - instr_realign
      - logic[ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0]
-     - Instruction address
 
    * - ``valid_i``
      - in
+     - Instruction is valid
      - instr_realign
      - logic[ariane_pkg::INSTR_PER_FETCH-1:0]
-     - Instruction is valid
 
    * - ``ready_o``
      - out
+     - Handshake’s ready with CACHE
      - CACHE
      - logic
-     - Handshake’s ready with CACHE
 
    * - ``consumed_o``
      - out
+     - Indicates instructions consummed, or popped by ID_STAGE
      - FRONTEND
      - logic[ariane_pkg::INSTR_PER_FETCH-1:0]
-     - Indicates instructions consummed, or popped by ID_STAGE
 
    * - ``exception_i``
      - in
+     - Exception (which is page-table fault)
      - CACHE
      - ariane_pkg::frontend_exception_t
-     - Exception (which is page-table fault)
 
    * - ``exception_addr_i``
      - in
+     - Exception address
      - CACHE
      - logic[riscv::VLEN-1:0]
-     - Exception address
 
    * - ``predict_address_i``
      - in
+     - Branch predict
      - FRONTEND
      - logic[riscv::VLEN-1:0]
-     - Branch predict
 
    * - ``cf_type_i``
      - in
+     - Instruction predict address
      - FRONTEND
      - ariane_pkg::cf_t[ariane_pkg::INSTR_PER_FETCH-1:0]
-     - Instruction predict address
 
    * - ``replay_o``
      - out
+     - Replay instruction because one of the FIFO was  full
      - FRONTEND
      - logic
-     - Replay instruction because one of the FIFO was  full
 
    * - ``replay_addr_o``
      - out
+     - Address at which to replay the fetch
      - FRONTEND
      - logic[riscv::VLEN-1:0]
-     - Address at which to replay the fetch
 
    * - ``fetch_entry_o``
      - out
+     - Handshake’s data with ID_STAGE
      - ID_STAGE
      - ariane_pkg::fetch_entry_t
-     - Handshake’s data with ID_STAGE
 
    * - ``fetch_entry_valid_o``
      - out
+     - Handshake’s valid with ID_STAGE
      - ID_STAGE
      - logic
-     - Handshake’s valid with ID_STAGE
 
    * - ``fetch_entry_ready_i``
      - in
+     - Handshake’s ready with ID_STAGE
      - ID_STAGE
      - logic
-     - Handshake’s ready with ID_STAGE
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+none

docs/04_cv32a65x_design/source/port_instr_realign.rst

@@ -14,66 +14,70 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``flush_i``
      - in
+     - Fetch flush request
      - CONTROLLER
      - logic
-     - Fetch flush request
 
    * - ``valid_i``
      - in
+     - 32-bit block is valid
      - CACHE
      - logic
-     - 32-bit block is valid
 
    * - ``serving_unaligned_o``
      - out
+     - Instruction is unaligned
      - FRONTEND
      - logic
-     - Instruction is unaligned
 
    * - ``address_i``
      - in
+     - 32-bit block address
      - CACHE
      - logic[riscv::VLEN-1:0]
-     - 32-bit block address
 
    * - ``data_i``
      - in
+     - 32-bit block
      - CACHE
      - logic[FETCH_WIDTH-1:0]
-     - 32-bit block
 
    * - ``valid_o``
      - out
+     - instruction is valid
      - FRONTEND
      - logic[INSTR_PER_FETCH-1:0]
-     - instruction is valid
 
    * - ``addr_o``
      - out
+     - Instruction address
      - FRONTEND
      - logic[INSTR_PER_FETCH-1:0][riscv::VLEN-1:0]
-     - Instruction address
 
    * - ``instr_o``
      - out
-     - none
+     - Instruction
+     - instr_scan&instr_queue
      - logic[INSTR_PER_FETCH-1:0][31:0]
-     - none
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+none

docs/04_cv32a65x_design/source/port_instr_scan.rst

@@ -14,90 +14,94 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``instr_i``
      - in
+     - Instruction to be predecoded
      - instr_realign
      - logic[31:0]
-     - Instruction to be predecoded
 
    * - ``rvi_return_o``
      - out
+     - Return instruction
      - FRONTEND
      - logic
-     - Return instruction
 
    * - ``rvi_call_o``
      - out
+     - JAL instruction
      - FRONTEND
      - logic
-     - JAL instruction
 
    * - ``rvi_branch_o``
      - out
+     - Branch instruction
      - FRONTEND
      - logic
-     - Branch instruction
 
    * - ``rvi_jalr_o``
      - out
+     - JALR instruction
      - FRONTEND
      - logic
-     - JALR instruction
 
    * - ``rvi_jump_o``
      - out
+     - Unconditional jump instruction
      - FRONTEND
      - logic
-     - Unconditional jump instruction
 
    * - ``rvi_imm_o``
      - out
+     - Instruction immediat
      - FRONTEND
      - logic[riscv::VLEN-1:0]
-     - Instruction immediat
 
    * - ``rvc_branch_o``
      - out
+     - Branch compressed instruction
      - FRONTEND
      - logic
-     - Branch compressed instruction
 
    * - ``rvc_jump_o``
      - out
+     - Unconditional jump compressed instruction
      - FRONTEND
      - logic
-     - Unconditional jump compressed instruction
 
    * - ``rvc_jr_o``
      - out
+     - JR compressed instruction
      - FRONTEND
      - logic
-     - JR compressed instruction
 
    * - ``rvc_return_o``
      - out
+     - Return compressed instruction
      - FRONTEND
      - logic
-     - Return compressed instruction
 
    * - ``rvc_jalr_o``
      - out
+     - JALR compressed instruction
      - FRONTEND
      - logic
-     - JALR compressed instruction
 
    * - ``rvc_call_o``
      - out
+     - JAL compressed instruction
      - FRONTEND
      - logic
-     - JAL compressed instruction
 
    * - ``rvc_imm_o``
      - out
+     - Instruction compressed immediat
      - FRONTEND
      - logic[riscv::VLEN-1:0]
-     - Instruction compressed immediat
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+none

docs/04_cv32a65x_design/source/port_issue_read_operands.rst

@@ -0,0 +1,287 @@
+..
+   Copyright 2024 Thales DIS France SAS
+   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: Jean-Roch COULON - Thales
+
+.. _CVA6_issue_read_operands_ports:
+
+.. list-table:: issue_read_operands module IO ports
+   :header-rows: 1
+
+   * - Signal
+     - IO
+     - Description
+     - connexion
+     - Type
+
+   * - ``Clock``
+     - in
+     - none
+     - none
+     - logicclk_i,//
+
+   * - ``low``
+     - in
+     - none
+     - none
+     - logicrst_ni,//Asynchronousresetactive
+
+   * - ``flush_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``stall_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``issue_instr_i``
+     - in
+     - none
+     - none
+     - scoreboard_entry_t
+
+   * - ``orig_instr_i``
+     - in
+     - none
+     - none
+     - logic[31:0]
+
+   * - ``issue_instr_valid_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``issue_ack_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``rs1_o``
+     - out
+     - none
+     - none
+     - logic[REG_ADDR_SIZE-1:0]
+
+   * - ``rs1_i``
+     - in
+     - none
+     - none
+     - riscv::xlen_t
+
+   * - ``rs1_valid_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``rs2_o``
+     - out
+     - none
+     - none
+     - logic[REG_ADDR_SIZE-1:0]
+
+   * - ``rs2_i``
+     - in
+     - none
+     - none
+     - riscv::xlen_t
+
+   * - ``rs2_valid_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``rs3_o``
+     - out
+     - none
+     - none
+     - logic[REG_ADDR_SIZE-1:0]
+
+   * - ``rs3_i``
+     - in
+     - none
+     - none
+     - rs3_len_t
+
+   * - ``rs3_valid_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``rd_clobber_gpr_i``
+     - in
+     - none
+     - none
+     - fu_t[2**REG_ADDR_SIZE-1:0]
+
+   * - ``rd_clobber_fpr_i``
+     - in
+     - none
+     - none
+     - fu_t[2**REG_ADDR_SIZE-1:0]
+
+   * - ``fu_data_o``
+     - out
+     - none
+     - none
+     - fu_data_t
+
+   * - ``fu_data_o.operanda``
+     - out
+     - none
+     - none
+     - riscv::xlen_trs1_forwarding_o,//unregisteredversionof
+
+   * - ``fu_data_o.operandb``
+     - out
+     - none
+     - none
+     - riscv::xlen_trs2_forwarding_o,//unregisteredversionof
+
+   * - ``pc_o``
+     - out
+     - none
+     - none
+     - logic[riscv::VLEN-1:0]
+
+   * - ``is_compressed_instr_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``request``
+     - in
+     - none
+     - none
+     - logicflu_ready_i,//Fixedlatencyunitreadytoacceptanew
+
+   * - ``valid``
+     - out
+     - none
+     - none
+     - logicalu_valid_o,//Outputis
+
+   * - ``instruction``
+     - out
+     - none
+     - none
+     - logicbranch_valid_o,//thisisavalidbranch
+
+   * - ``branch_predict_o``
+     - out
+     - none
+     - none
+     - branchpredict_sbe_t
+
+   * - ``ready``
+     - in
+     - none
+     - none
+     - logiclsu_ready_i,//FUis
+
+   * - ``valid``
+     - out
+     - none
+     - none
+     - logiclsu_valid_o,//Outputis
+
+   * - ``valid``
+     - out
+     - none
+     - none
+     - logicmult_valid_o,//Outputis
+
+   * - ``ready``
+     - in
+     - none
+     - none
+     - logicfpu_ready_i,//FUis
+
+   * - ``valid``
+     - out
+     - none
+     - none
+     - logicfpu_valid_o,//Outputis
+
+   * - ``instr.``
+     - out
+     - none
+     - none
+     - logic[1:0]fpu_fmt_o,//FPfmtfieldfrom
+
+   * - ``instr.``
+     - out
+     - none
+     - none
+     - logic[2:0]fpu_rm_o,//FPrmfieldfrom
+
+   * - ``valid``
+     - out
+     - none
+     - none
+     - logiccsr_valid_o,//Outputis
+
+   * - ``cvxif_valid_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``cvxif_ready_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``cvxif_off_instr_o``
+     - out
+     - none
+     - none
+     - logic[31:0]
+
+   * - ``waddr_i``
+     - in
+     - none
+     - none
+     - logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
+
+   * - ``wdata_i``
+     - in
+     - none
+     - none
+     - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0]
+
+   * - ``we_gpr_i``
+     - in
+     - none
+     - none
+     - logic[CVA6Cfg.NrCommitPorts-1:0]
+
+   * - ``we_fpr_i``
+     - in
+     - none
+     - none
+     - logic[CVA6Cfg.NrCommitPorts-1:0]
+
+   * - ``entries``
+     - out
+     - none
+     - none
+     - logicstall_issue_o//stallsignal,wedonotwanttofetchanymore
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+none

docs/04_cv32a65x_design/source/port_issue_stage.rst

@@ -14,300 +14,257 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
-
-   * - ``sb_full_o``
-     - out
-     - PERF_COUNTERS
-     - logic
-     - TO_BE_COMPLETED
 
    * - ``flush_unissued_instr_i``
      - in
+     - TO_BE_COMPLETED
      - CONTROLLER
      - logic
-     - TO_BE_COMPLETED
 
    * - ``flush_i``
      - in
+     - TO_BE_COMPLETED
      - CONTROLLER
      - logic
-     - TO_BE_COMPLETED
-
-   * - ``stall_i``
-     - in
-     - ACC_DISPATCHER
-     - logic
-     - zero when accelerate port is disable
 
    * - ``decoded_instr_i``
      - in
+     - Handshake's data with decode stage
      - ID_STAGE
      - scoreboard_entry_t
-     - Handshake's data between decode and issue
 
    * - ``orig_instr_i``
      - in
+     - instruction value
      - ID_STAGE
      - logic[31:0]
-     - instruction value
 
    * - ``decoded_instr_valid_i``
      - in
+     - Handshake's valid with decode stage
      - ID_STAGE
      - logic
-     - Handshake's valid between decode and issue
 
    * - ``is_ctrl_flow_i``
      - in
+     - Is instruction a control flow instruction
      - ID_STAGE
      - logic
-     - Report if instruction is a control flow instruction
 
    * - ``decoded_instr_ack_o``
      - out
+     - Handshake's acknowlege with decode stage
      - ID_STAGE
      - logic
-     - Handshake's acknowlege between decode and issue
 
    * - ``rs1_forwarding_o``
      - out
+     - rs1 forwarding
      - EX_STAGE
      - [riscv::VLEN-1:0]
-     - TO_BE_COMPLETED
 
    * - ``rs2_forwarding_o``
      - out
+     - rs2 forwarding
      - EX_STAGE
      - [riscv::VLEN-1:0]
-     - TO_BE_COMPLETED
 
    * - ``fu_data_o``
      - out
+     - FU data useful to execute instruction
      - EX_STAGE
      - fu_data_t
-     - TO_BE_COMPLETED
 
    * - ``pc_o``
      - out
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[riscv::VLEN-1:0]
-     - TO_BE_COMPLETED
 
    * - ``is_compressed_instr_o``
      - out
+     - Is compressed instruction
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``flu_ready_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``alu_valid_o``
      - out
+     - ALU FU is valid
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``resolve_branch_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``lsu_ready_i``
      - in
+     - Load store unit FU is ready
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``lsu_valid_o``
      - out
+     - Load store unit FU is valid
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``branch_valid_o``
      - out
+     - Branch unit is valid
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``branch_predict_o``
      - out
+     - Information of branch prediction
      - EX_STAGE
      - branchpredict_sbe_t
-     - TO_BE_COMPLETED
 
    * - ``mult_valid_o``
      - out
+     - Mult FU is valid
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``fpu_ready_i``
      - in
+     - FPU FU is ready
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
-
-   * - ``fpu_valid_o``
-     - out
-     - EX_STAGE
-     - logic
-     - TO_BE_COMPLETED
-
-   * - ``fpu_fmt_o``
-     - out
-     - EX_STAGE
-     - logic[1:0]
-     - Report FP fmt field
-
-   * - ``fpu_rm_o``
-     - out
-     - EX_STAGE
-     - logic[2:0]
-     - report FP rm field
 
    * - ``csr_valid_o``
      - out
+     - CSR is valid
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``x_issue_valid_o``
      - out
+     - CVXIF FU is valid
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``x_issue_ready_i``
      - in
+     - CVXIF is FU ready
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``x_off_instr_o``
      - out
+     - CVXIF offloader instruction value
      - EX_STAGE
      - logic[31:0]
-     - TO_BE_COMPLETED
-
-   * - ``issue_instr_o``
-     - out
-     - ACC_DISPATCHER
-     - scoreboard_entry_t
-     - TO_BE_COMPLETED
-
-   * - ``issue_instr_hs_o``
-     - out
-     - ACC_DISPATCHER
-     - logic
-     - TO_BE_COMPLETED
 
    * - ``trans_id_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0]
-     - TO_BE_COMPLETED
 
    * - ``resolved_branch_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - bp_resolve_t
-     - TO_BE_COMPLETED
 
    * - ``wbdata_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0]
-     - TO_BE_COMPLETED
 
    * - ``ex_ex_i``
      - in
+     - exception from execute stage or CVXIF
      - EX_STAGE
      - exception_t[CVA6Cfg.NrWbPorts-1:0]
-     - exception from execute stage or CVXIF offloaded instruction
 
    * - ``wt_valid_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[CVA6Cfg.NrWbPorts-1:0]
-     - TO_BE_COMPLETED
 
    * - ``x_we_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic
-     - TO_BE_COMPLETED
 
    * - ``waddr_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
-     - TO_BE_COMPLETED
 
    * - ``wdata_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0]
-     - TO_BE_COMPLETED
 
    * - ``we_gpr_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0]
-     - TO_BE_COMPLETED
 
    * - ``we_fpr_i``
      - in
+     - TO_BE_COMPLETED
      - EX_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0]
-     - TO_BE_COMPLETED
 
    * - ``commit_instr_o``
      - out
+     - TO_BE_COMPLETED
      - COMMIT_STAGE
      - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
-     - TO_BE_COMPLETED
 
    * - ``commit_ack_i``
      - in
+     - TO_BE_COMPLETED
      - COMMIT_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0]
-     - TO_BE_COMPLETED
 
-   * - ``stall_issue_o``
-     - out
-     - PERF_COUNTERS
-     - logic
-     - Issue stall
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
 
-   * - ``rvfi_issue_pointer_o``
-     - out
-     - SUBSYSTEM
-     - logic[TRANS_ID_BITS-1:0]
-     - Information dedicated to RVFI
-
-   * - ``rvfi_commit_pointer_o``
-     - out
-     - SUBSYSTEM
-     - logic[CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0]
-     - Information dedicated to RVFI
+| As PerfCounterEn = 0,
+|   ``sb_full_o`` output is tied to 0
+|   ``stall_issue_o`` output is tied to 0
+| As EnableAccelerator = 0,
+|   ``stall_i`` input is tied to 0
+|   ``issue_instr_o`` output is tied to 0
+|   ``issue_instr_hs_o`` output is tied to 0
+| As RVF = 0,
+|   ``fpu_valid_o`` output is tied to 0
+|   ``fpu_fmt_o`` output is tied to 0
+|   ``fpu_rm_o`` output is tied to 0
+| As IsRVFI = 0,
+|   ``rvfi_issue_pointer_o`` output is tied to 0
+|   ``rvfi_commit_pointer_o`` output is tied to 0

docs/04_cv32a65x_design/source/port_ras.rst

@@ -14,48 +14,52 @@
 
    * - Signal
      - IO
-     - Connection
-     - Type
      - Description
+     - connexion
+     - Type
 
    * - ``clk_i``
      - in
+     - Subsystem Clock
      - SUBSYSTEM
      - logic
-     - Subsystem Clock
 
    * - ``rst_ni``
      - in
+     - Asynchronous reset active low
      - SUBSYSTEM
      - logic
-     - Asynchronous reset active low
 
    * - ``flush_i``
      - in
+     - Fetch flush request
      - CONTROLLER
      - logic
-     - Fetch flush request
 
    * - ``push_i``
      - in
+     - Push address in RAS
      - FRONTEND
      - logic
-     - Push address in RAS
 
    * - ``pop_i``
      - in
+     - Pop address from RAS
      - FRONTEND
      - logic
-     - Pop address from RAS
 
    * - ``data_i``
      - in
+     - Data to be pushed
      - FRONTEND
      - logic[riscv::VLEN-1:0]
-     - Data to be pushed
 
    * - ``data_o``
      - out
+     - Popped data
      - FRONTEND
      - ariane_pkg::ras_t
-     - Popped data
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+none

docs/04_cv32a65x_design/source/port_scoreboard.rst

@@ -0,0 +1,233 @@
+..
+   Copyright 2024 Thales DIS France SAS
+   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: Jean-Roch COULON - Thales
+
+.. _CVA6_scoreboard_ports:
+
+.. list-table:: scoreboard module IO ports
+   :header-rows: 1
+
+   * - Signal
+     - IO
+     - Description
+     - connexion
+     - Type
+
+   * - ``Clock``
+     - in
+     - none
+     - none
+     - logicclk_i,//
+
+   * - ``low``
+     - in
+     - none
+     - none
+     - logicrst_ni,//Asynchronousresetactive
+
+   * - ``sb_full_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``instructions``
+     - in
+     - none
+     - none
+     - logicflush_unissued_instr_i,//flushonlyun-issued
+
+   * - ``scoreboard``
+     - in
+     - none
+     - none
+     - logicflush_i,//flushwhole
+
+   * - ``branch``
+     - in
+     - none
+     - none
+     - logicunresolved_branch_i,//wehaveanunresolved
+
+   * - ``rd_clobber_gpr_o``
+     - out
+     - none
+     - none
+     - ariane_pkg::fu_t[2**ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rd_clobber_fpr_o``
+     - out
+     - none
+     - none
+     - ariane_pkg::fu_t[2**ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rs1_i``
+     - in
+     - none
+     - none
+     - logic[ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rs1_o``
+     - out
+     - none
+     - none
+     - riscv::xlen_t
+
+   * - ``rs1_valid_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``rs2_i``
+     - in
+     - none
+     - none
+     - logic[ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rs2_o``
+     - out
+     - none
+     - none
+     - riscv::xlen_t
+
+   * - ``rs2_valid_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``rs3_i``
+     - in
+     - none
+     - none
+     - logic[ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rs3_o``
+     - out
+     - none
+     - none
+     - rs3_len_t
+
+   * - ``rs3_valid_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``commit_instr_o``
+     - out
+     - none
+     - none
+     - ariane_pkg::scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
+
+   * - ``commit_ack_i``
+     - in
+     - none
+     - none
+     - logic[CVA6Cfg.NrCommitPorts-1:0]
+
+   * - ``decoded_instr_i``
+     - in
+     - none
+     - none
+     - ariane_pkg::scoreboard_entry_t
+
+   * - ``orig_instr_i``
+     - in
+     - none
+     - none
+     - logic[31:0]
+
+   * - ``decoded_instr_valid_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``decoded_instr_ack_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``issue_instr_o``
+     - out
+     - none
+     - none
+     - ariane_pkg::scoreboard_entry_t
+
+   * - ``orig_instr_o``
+     - out
+     - none
+     - none
+     - logic[31:0]
+
+   * - ``issue_instr_valid_o``
+     - out
+     - none
+     - none
+     - logic
+
+   * - ``issue_ack_i``
+     - in
+     - none
+     - none
+     - logic
+
+   * - ``resolved_branch_i``
+     - in
+     - none
+     - none
+     - ariane_pkg::bp_resolve_t
+
+   * - ``back``
+     - in
+     - none
+     - none
+     - logic[CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0]trans_id_i,//transactionIDatwhichtowritetheresult
+
+   * - ``in``
+     - in
+     - none
+     - none
+     - logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0]wbdata_i,//writedata
+
+   * - ``exception)``
+     - in
+     - none
+     - none
+     - ariane_pkg::exception_t[CVA6Cfg.NrWbPorts-1:0]ex_i,//exceptionfromafunctionalunit(e.g.:ld/st
+
+   * - ``valid``
+     - in
+     - none
+     - none
+     - logic[CVA6Cfg.NrWbPorts-1:0]wt_valid_i,//datainis
+
+   * - ``writeback``
+     - in
+     - none
+     - none
+     - logicx_we_i,//cvxifwefor
+
+   * - ``rvfi_issue_pointer_o``
+     - out
+     - none
+     - none
+     - logic[ariane_pkg::TRANS_ID_BITS-1:0]
+
+   * - ``rvfi_commit_pointer_o``
+     - out
+     - none
+     - none
+     - logic[CVA6Cfg.NrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0]
+
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+none

docs/04_cv32a65x_design/source/port_scoreboard.rst.ori

@@ -0,0 +1,229 @@
+..
+   Copyright 2024 Thales DIS France SAS
+   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: Jean-Roch COULON - Thales
+
+.. _CVA6_scoreboard_ports:
+
+.. list-table:: scoreboard module IO ports
+   :header-rows: 1
+
+   * - Signal
+     - IO
+     - Description
+     - Connection
+     - Type
+
+   * - ``clk_i``
+     - in
+     - Clock
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``rst_ni``
+     - in
+     - Asynchronous reset active low
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``sb_full_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``flush_unissued_instr_i``
+     - in
+     - flush only un-issued instructions
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``flush_i``
+     - in
+     - flush whole scoreboard
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``unresolved_branch_i``
+     - in
+     - we have an unresolved branch
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``rd_clobber_gpr_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - ariane_pkg::fu_t[2**ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rd_clobber_fpr_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - ariane_pkg::fu_t[2**ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rs1_i``
+     - in
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic[ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rs1_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - riscv::xlen_t
+
+   * - ``rs1_valid_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``rs2_i``
+     - in
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic[ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rs2_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - riscv::xlen_t
+
+   * - ``rs2_valid_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``rs3_i``
+     - in
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic[ariane_pkg::REG_ADDR_SIZE-1:0]
+
+   * - ``rs3_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - rs3_len_t
+
+   * - ``rs3_valid_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``commit_instr_o``
+     - out
+     - TO_BE_COMPLETED
+     - COMMIT_STAGE
+     - ariane_pkg::scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
+
+   * - ``commit_ack_i``
+     - in
+     - Advance the commit pointer when acknowledge
+     - COMMIT_STAGE
+     - logic[CVA6Cfg.NrCommitPorts-1:0]
+
+   * - ``decoded_instr_i``
+     - in
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - ariane_pkg::scoreboard_entry_t
+
+   * - ``orig_instr_i``
+     - in
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic[31:0]
+
+   * - ``decoded_instr_valid_i``
+     - in
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``decoded_instr_ack_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``issue_instr_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - ariane_pkg::scoreboard_entry_t
+
+   * - ``orig_instr_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic[31:0]
+
+   * - ``issue_instr_valid_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``issue_ack_i``
+     - in
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``resolved_branch_i``
+     - in
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - ariane_pkg::bp_resolve_t
+
+   * - ``trans_id_i``
+     - in
+     - transaction ID at which to write the result back
+     - TO_BE_COMPLETED
+     - logic[CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0]
+
+   * - ``wbdata_i``
+     - in
+     - write data in
+     - TO_BE_COMPLETED
+     - logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0]
+
+   * - ``ex_i``
+     - in
+     - exception from a functional unit (e.g.: ld/st exception)
+     - TO_BE_COMPLETED
+     - ariane_pkg::exception_t[CVA6Cfg.NrWbPorts-1:0]
+
+   * - ``wt_valid_i``
+     - in
+     - data in is valid
+     - TO_BE_COMPLETED
+     - logic[CVA6Cfg.NrWbPorts-1:0]
+
+   * - ``x_we_i``
+     - in
+     - cvxif we for writeback
+     - TO_BE_COMPLETED
+     - logic
+
+   * - ``rvfi_issue_pointer_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic[ariane_pkg::TRANS_ID_BITS-1:0]
+
+   * - ``rvfi_commit_pointer_o``
+     - out
+     - TO_BE_COMPLETED
+     - TO_BE_COMPLETED
+     - logic[CVA6Cfg.NrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0]

docs/04_cv32a65x_design/source/subsystem.rst

@@ -26,7 +26,12 @@ At least 6 cycles are needed to execute one instruction.
 Connection with other sub-systems
 ---------------------------------
 
-[TO BE COMPLETED]
+The submodule is connected to :
+
+* NOC interconnect provides memory content
+* COPROCESSOR connects through CV-X-IF coprocessor interface protocol
+* TRACER provides support for verification
+* TRAP provides traps inputs
 
 
 Parameter configuration

docs/scripts/classes.py

@@ -0,0 +1,38 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+#!/usr/bin/python3
+
+
+class Parameter:
+    def __init__(
+        self,
+        datatype,
+        description,
+        value,
+    ):
+        self.datatype = datatype
+        self.description = description
+        self.value = value
+
+
+class PortIO:
+    def __init__(
+        self,
+        name,
+        direction,
+        data_type,
+        description,
+        connexion,
+    ):
+        self.name = name
+        self.direction = direction
+        self.data_type = data_type
+        self.description = description
+        self.connexion = connexion

docs/scripts/define_blacklist.py

@@ -0,0 +1,84 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+#!/usr/bin/python3
+
+
+def define_blacklist(parameters):
+
+    black_list = {}
+    black_list["flush_bp_i"] = ["For any HW configuration", "zero"]
+
+    param = "IsRVFI"
+    paramvalue = "0"
+    if paramvalue == "0":
+        black_list["RVFI"] = [f"As {param} = {paramvalue}", "0"]
+
+    param = "DebugEn"
+    paramvalue = parameters[param].value
+    if paramvalue == "0":
+        black_list["set_debug_pc_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["debug_mode_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["debug_req_i"] = [f"As {param} = {paramvalue}", "0"]
+
+    param = "RVV"
+    paramvalue = parameters[param].value
+    if paramvalue == "0":
+        black_list["vs_i"] = [f"As {param} = {paramvalue}", "0"]
+
+    param = "EnableAccelerator"
+    paramvalue = parameters[param].value
+    if paramvalue == "0":
+        black_list["ACC_DISPATCHER"] = [f"As {param} = {paramvalue}", "0"]
+
+    param = "RVF"
+    paramvalue = parameters[param].value
+    if paramvalue == "0":
+        black_list["fs_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["frm_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_valid_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_ready_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_fmt_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_rm_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_valid_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_fmt_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_rm_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_frm_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_prec_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_trans_id_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_result_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["fpu_exception_o"] = [f"As {param} = {paramvalue}", "0"]
+
+    param = "RVA"
+    paramvalue = parameters[param].value
+    if paramvalue == "0":
+        black_list["amo_req_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["amo_resp_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["amo_valid_commit_i"] = [f"As {param} = {paramvalue}", "0"]
+
+    param = "PRIV"
+    paramvalue = "MachineOnly"
+    if paramvalue == "MachineOnly":  # TODO PRIV to be added to RTL parameters
+        black_list["ld_st_priv_lvl_i"] = [f"As {param} = {paramvalue}", "MAchineMode"]
+        black_list["priv_lvl_i"] = [f"As {param} = {paramvalue}", "MachineMode"]
+        # black_list["tvm_i"] = [f"As {param} = {paramvalue}", "0"]
+        # black_list["tw_i"] = [f"As {param} = {paramvalue}", "0"]
+        # black_list["tsr_i"] = [f"As {param} = {paramvalue}", "0"]
+
+    param = "PerfCounterEn"
+    paramvalue = "0"
+    if paramvalue == "0":  # TODO PerfCounterEn to be added to RTL parameters
+        black_list["PERF_COUNTERS"] = [f"As {param} = {paramvalue}", "0"]
+
+    param = "MMUPresent"
+    paramvalue = "0"
+    if paramvalue == "0":  # TODO the MMUPresent to be added to RTL parameters
+        black_list["flush_tlb_i"] = [f"As {param} = {paramvalue}", "0"]
+
+    return black_list

docs/scripts/parameters_extractor.py

@@ -11,57 +11,47 @@
 
 import re
 
-
-class Parameter:
-    def __init__(
-        self,
-        datatype,
-        description,
-        value,
-    ):
-        self.datatype = datatype
-        self.description = description
-        self.value = value
+from classes import Parameter
 
 
-if __name__ == "__main__":
+def parameters_extractor(spec_number, target):
 
     parameters = {}
-    FILE_IN = "../core/include/config_pkg.sv"
+    file_in = "../core/include/config_pkg.sv"
 
-    print("Input file " + FILE_IN)
-    with open(FILE_IN, "r", encoding="utf-8") as fin:
-        PRINT_ENABLE = 0
-        DESCRIPT = "TO_BE_COMPLETED"
+    print("Input file " + file_in)
+    with open(file_in, "r", encoding="utf-8") as fin:
+        print_enable = 0
+        descript = "TO_BE_COMPLETED"
         for line in fin:
             if "typedef struct packed" in line:
-                PRINT_ENABLE = 1
+                print_enable = 1
             if "cva6_cfg_t" in line:
-                PRINT_ENABLE = 0
+                print_enable = 0
             d = re.match(r"^ *(.*) ([\S]*);\n", line)
             h = re.match(r"^ *\/\/ (.*)\n", line)
-            if h and PRINT_ENABLE:
-                DESCRIPT = h.group(1)
-            if d and PRINT_ENABLE:
+            if h and print_enable:
+                descript = h.group(1)
+            if d and print_enable:
                 parameters[d.group(2)] = Parameter(
-                    d.group(1), DESCRIPT, "TO_BE_COMPLETED"
+                    d.group(1), descript, "TO_BE_COMPLETED"
                 )
-                DESCRIPT = "TO_BE_COMPLETED"
+                descript = "TO_BE_COMPLETED"
 
-    FILE_IN = "../core/include/cv32a65x_config_pkg.sv"
-    a = re.match(r".*\/(.*)_config_pkg.sv", FILE_IN)
+    file_in = f"../core/include/{target}_config_pkg.sv"
+    a = re.match(r".*\/(.*)_config_pkg.sv", file_in)
     module = a.group(1)
-    fileout = "./04_cv32a65x_design/source/parameters_" + module + ".rst"
-    print("Input file " + FILE_IN)
+    fileout = f"./{spec_number}_{target}_design/source/parameters_{module}.rst"
+    print("Input file " + file_in)
     print("Output file " + fileout)
 
-    with open(FILE_IN, "r", encoding="utf-8") as fin:
+    with open(file_in, "r", encoding="utf-8") as fin:
         for line in fin:
             e = re.match(r"^ +([\S]*): (.*)(?:,|)\n", line)
             if e:
                 parameters[e.group(1)].value = e.group(2)
 
-    with open(FILE_IN, "r", encoding="utf-8") as fin:
+    with open(file_in, "r", encoding="utf-8") as fin:
         for line in fin:
             c = re.match(r"^ +localparam ([\S]*) = (.*);\n", line)
             if c:
@@ -79,6 +69,11 @@ if __name__ == "__main__":
         variable = variable.replace(",", "")
         parameters[name].value = variable
 
+    return parameters
+
+
+def writeout_parameter_table(fileout, parameters, module):
+
     with open(fileout, "w") as fout:
         fout.write("..\n")
         fout.write("   Copyright 2024 Thales DIS France SAS\n")
@@ -98,7 +93,7 @@ if __name__ == "__main__":
         fout.write("   :header-rows: 1\n")
         fout.write("\n")
         fout.write("   * - Name\n")
-        fout.write("     - Description\n")
+        fout.write("     - description\n")
         fout.write("     - Value\n")
         for name in parameters:
             fout.write("\n")

docs/scripts/spec_builder.py

@@ -0,0 +1,154 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+#!/usr/bin/python3
+
+import re
+
+from classes import Parameter
+from classes import PortIO
+from define_blacklist import define_blacklist
+from parameters_extractor import parameters_extractor
+from parameters_extractor import writeout_parameter_table
+
+
+if __name__ == "__main__":
+
+    PATH = "04_cv32a65x"
+    [spec_number, target] = PATH.split("_")
+
+    print(spec_number, target)
+    parameters = parameters_extractor(spec_number, target)
+
+    fileout = f"./{spec_number}_{target}_design/source/parameters_{target}.rst"
+    writeout_parameter_table(fileout, parameters, target)
+
+    file = []
+    file.append("../core/cva6.sv")
+    file.append("../core/frontend/frontend.sv")
+    file.append("../core/frontend/bht.sv")
+    file.append("../core/frontend/btb.sv")
+    file.append("../core/frontend/ras.sv")
+    file.append("../core/frontend/instr_queue.sv")
+    file.append("../core/frontend/instr_scan.sv")
+    file.append("../core/instr_realign.sv")
+    file.append("../core/id_stage.sv")
+    file.append("../core/issue_stage.sv")
+    file.append("../core/ex_stage.sv")
+    file.append("../core/commit_stage.sv")
+    file.append("../core/controller.sv")
+    file.append("../core/csr_regfile.sv")
+    file.append("../core/decoder.sv")
+    file.append("../core/compressed_decoder.sv")
+    file.append("../core/scoreboard.sv")
+    file.append("../core/issue_read_operands.sv")
+
+    black_list = define_blacklist(parameters)
+
+    for filein in file:
+        comments = []
+        a = re.match(r".*\/(.*).sv", filein)
+        module = a.group(1)
+        fileout = "./04_cv32a65x_design/source/port_" + module + ".rst"
+        print("Input file " + filein)
+        print("Output file " + fileout)
+        ports = []
+        with open(filein, "r", encoding="utf-8") as fin:
+            description = "none"
+            connexion = "none"
+            for line in fin:
+                e = re.match(r"^ +(?:(in|out))put +([\S]*(?: +.* *|)) ([\S]*)\n", line)
+                d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line)
+                if d:
+                    description = d.group(1)
+                    connexion = d.group(2)
+                if e:
+                    name = e.group(3)
+                    name = name.replace(",", "")
+                    data_type = e.group(2)
+                    data_type = data_type.replace(" ", "")
+                    if connexion in black_list:
+                        for i, comment in enumerate(comments):
+                            if black_list[connexion][0] == comment[0]:
+                                comment[1] = (
+                                    comment[1]
+                                    + f"\n|   ``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}"
+                                )
+                                break
+                        else:
+                            comments.append(
+                                [
+                                    black_list[connexion][0],
+                                    f"``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}",
+                                ]
+                            )
+                    else:
+                        if name in black_list:
+                            for i, comment in enumerate(comments):
+                                if black_list[name][0] == comment[0]:
+                                    comment[1] = (
+                                        comment[1]
+                                        + f"\n|   ``{name}`` {e.group(1)}put is tied to {black_list[name][1]}"
+                                    )
+                                    break
+                            else:
+                                comments.append(
+                                    [
+                                        black_list[name][0],
+                                        f"``{name}`` {e.group(1)}put is tied to {black_list[name][1]}",
+                                    ]
+                                )
+                        else:
+                            ports.append(
+                                PortIO(
+                                    name, e.group(1), data_type, description, connexion
+                                )
+                            )
+                    description = "none"
+                    connexion = "none"
+
+        with open(fileout, "w", encoding="utf-8") as fout:
+            fout.write("..\n")
+            fout.write("   Copyright 2024 Thales DIS France SAS\n")
+            fout.write(
+                '   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");\n'
+            )
+            fout.write(
+                "   you may not use this file except in compliance with the License.\n"
+            )
+            fout.write("   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n")
+            fout.write(
+                "   You may obtain a copy of the License at https://solderpad.org/licenses/\n\n"
+            )
+            fout.write("   Original Author: Jean-Roch COULON - Thales\n\n")
+            fout.write(f".. _CVA6_{module}_ports:\n\n")
+            fout.write(f".. list-table:: {module} module IO ports\n")
+            fout.write("   :header-rows: 1\n")
+            fout.write("\n")
+            fout.write("   * - Signal\n")
+            fout.write("     - IO\n")
+            fout.write("     - Description\n")
+            fout.write("     - connexion\n")
+            fout.write("     - Type\n")
+            for i, port in enumerate(ports):
+                fout.write("\n")
+                fout.write(f"   * - ``{port.name}``\n")
+                fout.write(f"     - {port.direction}\n")
+                fout.write(f"     - {port.description}\n")
+                fout.write(f"     - {port.connexion}\n")
+                fout.write(f"     - {port.data_type}\n")
+            fout.write("\n")
+            fout.write(
+                f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
+            )
+            fout.write("\n")
+            for comment in comments:
+                fout.write(f"| {comment[0]},\n|   {comment[1]}\n")
+            if len(comments) == 0:
+                fout.write("none\n")

docs/scripts/table_port_builder.py

@@ -1,104 +0,0 @@
-# Copyright 2024 Thales DIS France SAS
-#
-# Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
-# you may not use this file except in compliance with the License.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-# You may obtain a copy of the License at https://solderpad.org/licenses/
-#
-# Original Author: Jean-Roch COULON - Thales
-
-#!/usr/bin/python3
-
-import re
-
-
-class PortIO:
-    def __init__(
-        self,
-        name,
-        direction,
-        data_type,
-        description,
-        connection,
-    ):
-        self.name = name
-        self.direction = direction
-        self.data_type = data_type
-        self.description = description
-        self.connection = connection
-
-
-if __name__ == "__main__":
-    file = []
-    file.append("../core/cva6.sv")
-    file.append("../core/frontend/frontend.sv")
-    file.append("../core/frontend/bht.sv")
-    file.append("../core/frontend/btb.sv")
-    file.append("../core/frontend/ras.sv")
-    file.append("../core/frontend/instr_queue.sv")
-    file.append("../core/frontend/instr_scan.sv")
-    file.append("../core/instr_realign.sv")
-    file.append("../core/id_stage.sv")
-    file.append("../core/issue_stage.sv")
-    file.append("../core/ex_stage.sv")
-    file.append("../core/commit_stage.sv")
-    file.append("../core/controller.sv")
-    file.append("../core/csr_regfile.sv")
-
-    for filein in file:
-        a = re.match(r".*\/(.*).sv", filein)
-        module = a.group(1)
-        fileout = "./04_cv32a65x_design/source/port_" + module + ".rst"
-        print("Input file " + filein)
-        print("Output file " + fileout)
-        ports = []
-        with open(filein, "r", encoding="utf-8") as fin:
-            description = "none"
-            connection = "none"
-            for line in fin:
-                e = re.match(r"^ +(?:(in|out))put +([\S]*(?: +.* *|)) ([\S]*)\n", line)
-                d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line)
-                if d:
-                    description = d.group(1)
-                    connection = d.group(2)
-                if e:
-                    name = e.group(3)
-                    name = name.replace(",", "")
-                    data_type = e.group(2)
-                    data_type = data_type.replace(" ", "")
-                    ports.append(
-                        PortIO(name, e.group(1), data_type, description, connection)
-                    )
-                    description = "none"
-                    connection = "none"
-
-        with open(fileout, "w", encoding="utf-8") as fout:
-            fout.write("..\n")
-            fout.write("   Copyright 2024 Thales DIS France SAS\n")
-            fout.write(
-                '   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");\n'
-            )
-            fout.write(
-                "   you may not use this file except in compliance with the License.\n"
-            )
-            fout.write("   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n")
-            fout.write(
-                "   You may obtain a copy of the License at https://solderpad.org/licenses/\n\n"
-            )
-            fout.write("   Original Author: Jean-Roch COULON - Thales\n\n")
-            fout.write(f".. _CVA6_{module}_ports:\n\n")
-            fout.write(f".. list-table:: {module} module IO ports\n")
-            fout.write("   :header-rows: 1\n")
-            fout.write("\n")
-            fout.write("   * - Signal\n")
-            fout.write("     - IO\n")
-            fout.write("     - Connection\n")
-            fout.write("     - Type\n")
-            fout.write("     - Description\n")
-            for i, port in enumerate(ports):
-                fout.write("\n")
-                fout.write(f"   * - ``{port.name}``\n")
-                fout.write(f"     - {port.direction}\n")
-                fout.write(f"     - {port.connection}\n")
-                fout.write(f"     - {port.data_type}\n")
-                fout.write(f"     - {port.description}\n")