github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-06-27 17:00:57 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

removing lint warnings.. (#1571)

Browse source
This commit is contained in:
Fatima Saleem 2023-11-20 14:21:04 +05:00 • committed by GitHub
parent b143be15d2
commit b4e5c7fa6a
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
7 changed files with 53 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

6
core/cache_subsystem/cva6_icache.sv
View file

@ -137,7 +137,7 @@ module cva6_icache
// latch this in case we have to stall later on
// make sure this is 32bit aligned
assign vaddr_d = (dreq_o.ready & dreq_i.req) ? dreq_i.vaddr : vaddr_q;
assign areq_o.fetch_vaddr = {vaddr_q >> 2, 2'b0};
assign areq_o.fetch_vaddr = {vaddr_q[riscv::VLEN-1:2], 2'b0};
// split virtual address into index and offset to address cache arrays
assign cl_index = vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH];
@ -145,8 +145,8 @@ module cva6_icache
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
// if we generate a noncacheable access, the word will be at offset 0 or 4 in the cl coming from memory
assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? {dreq_i.vaddr>>2, 2'b0} :
( paddr_is_nc & mem_data_req_o ) ? cl_offset_q[2]<<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case
assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? {dreq_i.vaddr[ICACHE_OFFSET_WIDTH-1:2], 2'b0} :
( paddr_is_nc & mem_data_req_o ) ? {{ICACHE_OFFSET_WIDTH-1{1'b0}}, cl_offset_q[2]}<<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case
cl_offset_q;
// request word address instead of cl address in case of NC access
assign mem_data_o.paddr = (paddr_is_nc) ? {cl_tag_d, vaddr_q[ICACHE_INDEX_WIDTH-1:3], 3'b0} : // align to 64bit

35
core/cache_subsystem/wt_axi_adapter.sv
View file

@ -56,7 +56,9 @@ module wt_axi_adapter
// support up to 512bit cache lines
localparam AxiNumWords = (ariane_pkg::ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (ariane_pkg::ICACHE_LINE_WIDTH > ariane_pkg::DCACHE_LINE_WIDTH) +
(ariane_pkg::DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth) * (ariane_pkg::ICACHE_LINE_WIDTH <= ariane_pkg::DCACHE_LINE_WIDTH) ;
localparam MaxNumWords = $clog2(CVA6Cfg.AxiDataWidth / 8);
localparam AxiRdBlenIcache = ariane_pkg::ICACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
localparam AxiRdBlenDcache = ariane_pkg::DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
///////////////////////////////////////////////////////
// request path
@ -130,11 +132,11 @@ module wt_axi_adapter
// request side
always_comb begin : p_axi_req
// write channel
axi_wr_id_in = arb_idx;
axi_wr_data = {(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.data}};
axi_wr_user = dcache_data.user;
axi_wr_id_in = {{CVA6Cfg.AxiIdWidth-1{1'b0}}, arb_idx};
axi_wr_data[0] = {(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.data}};
axi_wr_user[0] = dcache_data.user;
// Cast to AXI address width
axi_wr_addr = dcache_data.paddr;
axi_wr_addr = {{CVA6Cfg.AxiAddrWidth-riscv::PLEN{1'b0}}, dcache_data.paddr};
axi_wr_size = dcache_data.size;
axi_wr_req = 1'b0;
axi_wr_blen = '0;// single word writes
@ -145,7 +147,7 @@ module wt_axi_adapter
amo_gen_r_d = amo_gen_r_q;
// read channel
axi_rd_id_in = arb_idx;
axi_rd_id_in = {{CVA6Cfg.AxiIdWidth-1{1'b0}}, arb_idx};
axi_rd_req = 1'b0;
axi_rd_lock = '0;
axi_rd_blen = '0;
@ -159,19 +161,18 @@ module wt_axi_adapter
// arbiter mux
if (arb_idx) begin
// Cast to AXI address width
axi_rd_addr = dcache_data.paddr;
axi_rd_addr = {{CVA6Cfg.AxiAddrWidth-riscv::PLEN{1'b0}}, dcache_data.paddr};
// If dcache_data.size MSB is set, we want to read as much as possible
axi_rd_size = dcache_data.size[2] ? $clog2(CVA6Cfg.AxiDataWidth / 8) : dcache_data.size;
axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size;
if (dcache_data.size[2]) begin
axi_rd_blen = ariane_pkg::DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
axi_rd_blen = AxiRdBlenDcache[$clog2(AxiNumWords)-1:0];
end
end else begin
// Cast to AXI address width
axi_rd_addr = icache_data.paddr;
axi_rd_size =
$clog2(CVA6Cfg.AxiDataWidth / 8); // always request max number of words in case of ifill
axi_rd_addr = {{CVA6Cfg.AxiAddrWidth-riscv::PLEN{1'b0}}, icache_data.paddr};
axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill
if (!icache_data.nc) begin
axi_rd_blen = ariane_pkg::ICACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
axi_rd_blen = AxiRdBlenIcache[$clog2(AxiNumWords)-1:0];
end
end
@ -245,11 +246,11 @@ module wt_axi_adapter
amo_off_d = dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] & ~((1 << dcache_data.size[1:0]) - 1);
end
// RISC-V atops have a load semantic
AMO_SWAP: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ATOMICSWAP};
AMO_SWAP: axi_wr_atop = axi_pkg::ATOP_ATOMICSWAP;
AMO_ADD: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD};
AMO_AND: begin
// in this case we need to invert the data to get a "CLR"
axi_wr_data = ~{(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.data}};
axi_wr_data[0] = ~{(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.data}};
axi_wr_user = ~{(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.user}};
axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR};
end
@ -434,7 +435,7 @@ module wt_axi_adapter
if (icache_rtrn_rd_en) begin
icache_first_d = axi_rd_last;
if (ICACHE_LINE_WIDTH == CVA6Cfg.AxiDataWidth) begin
icache_rd_shift_d = axi_rd_data;
icache_rd_shift_d[0] = axi_rd_data;
end else begin
icache_rd_shift_d = {
axi_rd_data, icache_rd_shift_q[ICACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:1]
@ -453,7 +454,7 @@ module wt_axi_adapter
if (dcache_rtrn_rd_en) begin
dcache_first_d = axi_rd_last;
if (DCACHE_LINE_WIDTH == CVA6Cfg.AxiDataWidth) begin
dcache_rd_shift_d = axi_rd_data;
dcache_rd_shift_d[0] = axi_rd_data;
end else begin
dcache_rd_shift_d = {
axi_rd_data, dcache_rd_shift_q[DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:1]

2
core/instr_realign.sv
View file

@ -99,7 +99,7 @@ module instr_realign
unaligned_instr_d = data_i[15:0];
// the instruction isn't compressed but only the lower is ready
end else begin
valid_o = 1'b1;
valid_o = {{INSTR_PER_FETCH-1{1'b0}}, 1'b1};
end
end
end

11
core/scoreboard.sv
View file

@ -195,7 +195,7 @@ module scoreboard #(
// Commit Port
// ------------
// we've got an acknowledge from commit
for (logic [CVA6Cfg.NrCommitPorts-1:0] i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
if (commit_ack_i[i]) begin
// this instruction is no longer in issue e.g.: it is considered finished
mem_n[commit_pointer_q[i]].issued = 1'b0;
@ -217,13 +217,14 @@ module scoreboard #(
end
// FIFO counter updates
if (CVA6Cfg.NrCommitPorts == 2) begin : gen_two_commit_ports
if (CVA6Cfg.NrCommitPorts == 2) begin : gen_commit_ports
assign num_commit = commit_ack_i[1] + commit_ack_i[0];
end else begin : gen_one_commit_port
assign num_commit = commit_ack_i[0];
end
assign issue_cnt_n = (flush_i) ? '0 : issue_cnt_q - num_commit + issue_en;
assign issue_cnt_n = (flush_i) ? '0 : issue_cnt_q - {{BITS_ENTRIES-$clog2(CVA6Cfg.NrCommitPorts){1'b0}}, num_commit}
+ {{BITS_ENTRIES-1{1'b0}}, issue_en};
assign commit_pointer_n[0] = (flush_i) ? '0 : commit_pointer_q[0] + num_commit;
assign issue_pointer_n = (flush_i) ? '0 : issue_pointer_q + issue_en;
@ -445,11 +446,11 @@ module scoreboard #(
assert property (
@(posedge clk_i) disable iff (!rst_ni) commit_ack_i[0] |-> commit_instr_o[0].valid)
else $fatal(1, "Commit acknowledged but instruction is not valid");
if (CVA6Cfg.NrCommitPorts == 2) begin : gen_two_commit_ports
assert property (
@(posedge clk_i) disable iff (!rst_ni) commit_ack_i[1] |-> commit_instr_o[1].valid)
else $fatal(1, "Commit acknowledged but instruction is not valid");
end
// assert that we never give an issue ack signal if the instruction is not valid
assert property (@(posedge clk_i) disable iff (!rst_ni) issue_ack_i |-> issue_instr_valid_o)
else $fatal(1, "Issue acknowledged but instruction is not valid");

2
core/store_unit.sv
View file

@ -188,7 +188,7 @@ module store_unit
st_be_n = lsu_ctrl_i.be;
// don't shift the data if we are going to perform an AMO as we still need to operate on this data
st_data_n = (CVA6Cfg.RVA && instr_is_amo) ? lsu_ctrl_i.data[riscv::XLEN-1:0] :
data_align(lsu_ctrl_i.vaddr[2:0], lsu_ctrl_i.data);
data_align(lsu_ctrl_i.vaddr[2:0], {{64-riscv::XLEN{1'b0}}, lsu_ctrl_i.data});
st_data_size_n = extract_transfer_size(lsu_ctrl_i.operation);
// save AMO op for next cycle
if(CVA6Cfg.RVA) begin

9
corev_apu/tb/common/mock_uart.sv
View file

@ -57,6 +57,10 @@ module mock_uart (
$write("%c", ch);
endfunction : uart_tx
/* verilator lint_off WIDTHTRUNC */
/* verilator lint_off WIDTHEXPAND */
/* verilator lint_off WIDTHCONCAT */
always_ff @(posedge clk_i or negedge rst_ni) begin
if (rst_ni) begin
if (psel_i & penable_i & pwrite_i) begin
@ -108,4 +112,9 @@ module mock_uart (
endcase
end
end
/* verilator lint_on WIDTHTRUNC */
/* verilator lint_on WIDTHEXPAND */
/* verilator lint_on WIDTHCONCAT */
endmodule

21
verilator_config.vlt
View file

@ -6,14 +6,17 @@
`verilator_config
// TODO -> Please update the configuration file according to the warnings resolution
// Timing flag issue CVA6 #1162, waiving it off
lint_off -rule STMTDLY
// waving these warnings since they are in vendor or core_apu
lint_off -rule STMTDLY -file "*/corev_apu/*"
lint_off -rule WIDTHEXPAND -file "*/common/local/util/sram.sv"
lint_off -rule WIDTHTRUNC -file "*/core/include/std_cache_pkg.sv"
lint_off -file "*/corev_apu/*"
lint_off -file "*/vendor/*"
// Big Endian usage issue CVA6 #1176, waiving it off
lint_off -rule LITENDIAN
lint_off -rule WIDTHEXPAND -file "*/core/cache_subsystem/axi_adapter.sv"
lint_off -rule WIDTHEXPAND -file "*/core/axi_shim.sv"
// New Line at the end of file in submodule register_interface, waiving it off
// Commenting this out since CI Verilator does not recognize this rule
// lint_off -rule EOFNEWLINE -file "corev_apu/*.svh"
// lint_off -file "corev_apu/*.svh"
// P2
lint_off -rule WIDTHEXPAND -file "*/core/issue_read_operands.sv"
lint_off -rule WIDTHEXPAND -file "*/core/ariane_regfile_ff.sv"
lint_off -rule SELRANGE -file "*/core/commit_stage.sv"