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https://github.com/openhwgroup/cva6.git
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🐛 Fix re-naming when issued operand is flushed
This commit is contained in:
Florian Zaruba
parent
712de20bdd
commit
b58b63d61e
7 changed files with 80 additions and 67 deletions
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@ -72,8 +72,6 @@ $ riscv64-unknown-elf-gcc hello.c -o hello.elf
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```
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$ make verilate
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$ work-ver/Variane_testharness $RISCV/riscv64-unknown-elf/bin/pk hello.elf
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```
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If you want to use QuestaSim to run it you can use the following command:
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@ -122,7 +120,6 @@ In order to run randomized Torture tests, you first have to generate the randomi
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$ ./ci/get-torture.sh
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$ make torture-gen
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$ make torture-rtest-verilator
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```
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This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file.
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@ -20,15 +20,15 @@ module bootrom (
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input logic [63:0] addr_i,
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output logic [63:0] rdata_o
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);
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localparam int RomSize = 141;
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localparam int RomSize = 143;
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const logic [RomSize-1:0][63:0] mem = {
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64'h0064,
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64'h65646e65_7478652d,
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64'h73747075_72726574,
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64'h6e690073_65676e61,
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64'h7200656c_646e6168,
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64'h70007265_6c6c6f72,
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64'h00646564_6e657478,
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64'h652d7374_70757272,
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64'h65746e69_00736567,
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64'h6e617200_656c646e,
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64'h6168702c_78756e69,
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64'h6c007265_6c6c6f72,
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64'h746e6f63_2d747075,
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64'h72726574_6e690073,
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64'h6c6c6563_2d747075,
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@ -60,7 +60,7 @@ module bootrom (
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64'h4b000000_10000000,
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64'h03000000_07000000,
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64'h01000000_03000000,
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64'h01000000_ae000000,
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64'h01000000_b4000000,
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64'h10000000_03000000,
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64'h00000000_30746e69,
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64'h6c632c76_63736972,
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@ -68,7 +68,7 @@ module bootrom (
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64'h03000000_00000030,
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64'h30303030_30324074,
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64'h6e696c63_01000000,
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64'ha7000000_00000000,
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64'had000000_00000000,
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64'h03000000_00007375,
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64'h622d656c_706d6973,
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64'h00636f73_2d657261,
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@ -91,6 +91,8 @@ module bootrom (
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64'h6f6d656d_01000000,
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64'h02000000_02000000,
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64'h02000000_01000000,
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64'ha5000000_04000000,
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64'h03000000_01000000,
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64'h9f000000_04000000,
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64'h03000000_00006374,
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64'h6e692d75_70632c76,
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@ -143,11 +145,11 @@ module bootrom (
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64'h00000000_01000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'he8020000_c2000000,
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64'hf8020000_c8000000,
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64'h00000000_10000000,
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64'h11000000_28000000,
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64'h20030000_38000000,
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64'he2030000_edfe0dd0,
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64'h30030000_38000000,
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64'hf8030000_edfe0dd0,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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@ -141,7 +141,7 @@ module axi_lite_interface #(
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// Registers
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// ------------------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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if (~rst_ni) begin
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CS <= IDLE;
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address_q <= '0;
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trans_id_q <= '0;
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@ -159,10 +159,10 @@ module axi_lite_interface #(
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`ifndef SYNTHESIS
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`ifndef VERILATOR
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// check that burst length is just one
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assert property (@(posedge clk_i) slave.ar_valid |-> ((slave.ar_len == 8'b0) && (slave.ar_size == $clog2(AXI_ADDR_WIDTH/8))))
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assert property (@(posedge clk_i) slave.ar_valid |-> ((slave.ar_len == 8'b0)))
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else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
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// do the same for the write channel
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assert property (@(posedge clk_i) slave.aw_valid |-> ((slave.aw_len == 8'b0) && (slave.aw_size == $clog2(AXI_ADDR_WIDTH/8))))
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assert property (@(posedge clk_i) slave.aw_valid |-> ((slave.aw_len == 8'b0)))
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else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
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`endif
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`endif
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@ -132,10 +132,11 @@ module clint #(
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always_comb begin : irq_gen
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// check that the mtime cmp register is set to a meaningful value
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for (int unsigned i = 0; i < NR_CORES; i++) begin
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if (mtimecmp_q[i] != 0 && mtime_q >= mtimecmp_q[i])
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if (mtimecmp_q[i] != 0 && mtime_q >= mtimecmp_q[i]) begin
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timer_irq_o[i] = 1'b1;
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else
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end else begin
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timer_irq_o[i] = 1'b0;
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end
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end
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end
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@ -155,7 +156,7 @@ module clint #(
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// Registers
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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if (~rst_ni) begin
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mtime_q <= 64'b0;
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mtimecmp_q <= 'b0;
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msip_q <= '0;
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@ -19,7 +19,7 @@ module issue_stage #(
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parameter int unsigned NR_ENTRIES = 8,
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parameter int unsigned NR_WB_PORTS = 4,
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parameter int unsigned NR_COMMIT_PORTS = 2
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)(
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)(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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@ -98,45 +98,54 @@ module issue_stage #(
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// 1. Re-name
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// ---------------------------------------------------------
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re_name i_re_name (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_i ),
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.issue_instr_i ( decoded_instr_i ),
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.issue_instr_valid_i ( decoded_instr_valid_i ),
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.issue_ack_o ( decoded_instr_ack_o ),
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.issue_instr_o ( issue_instr_rename_sb ),
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.issue_instr_valid_o ( issue_instr_valid_rename_sb ),
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.issue_ack_i ( issue_ack_sb_rename )
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_i ),
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.flush_unissied_instr_i ( flush_unissued_instr_i ),
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.issue_instr_i ( decoded_instr_i ),
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.issue_instr_valid_i ( decoded_instr_valid_i ),
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.issue_ack_o ( decoded_instr_ack_o ),
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.issue_instr_o ( issue_instr_rename_sb ),
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.issue_instr_valid_o ( issue_instr_valid_rename_sb ),
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.issue_ack_i ( issue_ack_sb_rename )
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);
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// ---------------------------------------------------------
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// 2. Manage instructions in a scoreboard
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// ---------------------------------------------------------
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scoreboard #(
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.NR_ENTRIES ( NR_ENTRIES ),
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.NR_WB_PORTS ( NR_WB_PORTS )
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scoreboard #(
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.NR_ENTRIES (NR_ENTRIES ),
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.NR_WB_PORTS(NR_WB_PORTS)
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) i_scoreboard (
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.unresolved_branch_i ( 1'b0 ),
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.rd_clobber_o ( rd_clobber_sb_iro ),
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.rs1_i ( rs1_iro_sb ),
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.rs1_o ( rs1_sb_iro ),
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.rs1_valid_o ( rs1_valid_sb_iro ),
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.rs2_i ( rs2_iro_sb ),
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.rs2_o ( rs2_sb_iro ),
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.rs2_valid_o ( rs2_valid_iro_sb ),
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_unissued_instr_i ( flush_unissued_instr_i ),
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.flush_i ( flush_i ),
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.unresolved_branch_i ( 1'b0 ),
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.decoded_instr_i ( issue_instr_rename_sb ),
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.decoded_instr_valid_i ( issue_instr_valid_rename_sb ),
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.decoded_instr_ack_o ( issue_ack_sb_rename ),
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.issue_instr_o ( issue_instr_sb_iro ),
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.issue_instr_valid_o ( issue_instr_valid_sb_iro ),
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.issue_ack_i ( issue_ack_iro_sb ),
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.rd_clobber_o ( rd_clobber_sb_iro ),
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.rs1_i ( rs1_iro_sb ),
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.rs1_o ( rs1_sb_iro ),
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.rs1_valid_o ( rs1_valid_sb_iro ),
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.rs2_i ( rs2_iro_sb ),
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.rs2_o ( rs2_sb_iro ),
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.rs2_valid_o ( rs2_valid_iro_sb ),
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.resolved_branch_i ( resolved_branch_i ),
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.trans_id_i ( trans_id_i ),
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.wbdata_i ( wbdata_i ),
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.ex_i ( ex_ex_i ),
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.*
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.commit_instr_o ( commit_instr_o ),
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.commit_ack_i ( commit_ack_i ),
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.decoded_instr_i ( issue_instr_rename_sb ),
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.decoded_instr_valid_i ( issue_instr_valid_rename_sb ),
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.decoded_instr_ack_o ( issue_ack_sb_rename ),
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.issue_instr_o ( issue_instr_sb_iro ),
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.issue_instr_valid_o ( issue_instr_valid_sb_iro ),
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.issue_ack_i ( issue_ack_iro_sb ),
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.resolved_branch_i ( resolved_branch_i ),
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.trans_id_i ( trans_id_i ),
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.wbdata_i ( wbdata_i ),
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.ex_i ( ex_ex_i ),
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.wb_valid_i ( wb_valid_i )
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);
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// ---------------------------------------------------------
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@ -24,6 +24,7 @@ module re_name (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i, // Flush renaming state
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input logic flush_unissied_instr_i,
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// from/to scoreboard
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input scoreboard_entry_t issue_instr_i,
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input logic issue_instr_valid_i,
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@ -52,7 +53,7 @@ module re_name (
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re_name_table_gpr_n = re_name_table_gpr_q;
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issue_instr_o = issue_instr_i;
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if (issue_ack_i) begin
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if (issue_ack_i && !flush_unissied_instr_i) begin
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// if we acknowledge the instruction tic the corresponding destination register
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re_name_table_gpr_n[issue_instr_i.rd] = re_name_table_gpr_q[issue_instr_i.rd] ^ 1'b1;
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end
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@ -14,17 +14,17 @@
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// Instantiates an AXI-Bus and memories
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module ariane_testharness #(
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parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
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parameter int unsigned AXI_ID_WIDTH = 10,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_ADDRESS_WIDTH = 64,
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parameter int unsigned AXI_DATA_WIDTH = 64,
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parameter int unsigned NUM_WORDS = 2**24 // memory size
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)(
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input logic clk_i,
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input logic rst_ni,
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output logic [31:0] exit_o
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);
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parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
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parameter int unsigned AXI_ID_WIDTH = 10,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_ADDRESS_WIDTH = 64,
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parameter int unsigned AXI_DATA_WIDTH = 64,
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parameter int unsigned NUM_WORDS = 2**24 // memory size
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)(
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input logic clk_i,
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input logic rst_ni,
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output logic [31:0] exit_o
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);
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// disable test-enable
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logic test_en;
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@ -64,6 +64,9 @@ module ariane_testharness #(
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logic dmi_resp_ready;
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logic dmi_resp_valid;
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logic rtc_i;
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assign rtc_i = 1'b0;
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assign test_en = 1'b0;
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assign ndmreset_n = ~ndmreset ;
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@ -153,7 +156,7 @@ module ariane_testharness #(
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.debug_req_valid ( dmi_req_valid ),
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.debug_req_ready ( debug_req_ready ),
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.debug_req_bits_addr ( dmi_req.addr ),
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.debug_req_bits_op ( debug_req_bits_op ),
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.debug_req_bits_op ( debug_req_bits_op ),
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.debug_req_bits_data ( dmi_req.data ),
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.debug_resp_valid ( dmi_resp_valid ),
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.debug_resp_ready ( dmi_resp_ready ),
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@ -298,7 +301,7 @@ module ariane_testharness #(
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.slave ( master[1] ),
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.rtc_i ( 1'b0 ),
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.rtc_i ( rtc_i ),
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.timer_irq_o ( timer_irq ),
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.ipi_o ( ipi )
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);
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