github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-22 05:07:21 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 5

Merge pull request #1895 from AyoubJalali/decoder/isa

Browse source 
Decoder for some C instructions
This commit is contained in:
André Sintzoff 2023-07-28 16:36:54 +02:00 • committed by GitHub
commit b5ab374695
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 56 additions and 28 deletions
Download patch file Download diff file Expand all files Collapse all files

27
lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv
View file

@ -1155,7 +1155,7 @@ covergroup cg_ciw(
option.per_instance = 1;
option.name = name;
cp_rd: coverpoint instr.c_rdp;
cp_c_rd: coverpoint instr.c_rd;
`ISACOV_CP_BITWISE(cp_rd_toggle, instr.rd_value, 1)
`ISACOV_CP_BITWISE_7_0(cp_imm_toggle, instr.get_field_imm(), 1)
@ -1186,12 +1186,12 @@ covergroup cg_cl(
ignore_bins NON_ZERO_OFF = {NON_ZERO} `WITH (imm_is_signed);
}
cp_rs1: coverpoint instr.c_rs1s;
cp_rd: coverpoint instr.c_rdp;
cp_c_rs1: coverpoint instr.c_rs1;
cp_c_rd: coverpoint instr.c_rd;
cp_rd_rs1_hazard: coverpoint instr.rd {
cp_c_rd_rs1_hazard: coverpoint instr.c_rd {
ignore_bins IGN_RS1_HAZARD_OFF = {[0:$]} `WITH (!reg_hazards_enabled);
bins RD[] = {[0:31]} iff (instr.rd == instr.rs1);
bins RD[] = {[0:7]} iff (instr.c_rd == instr.c_rs1);
}
`ISACOV_CP_BITWISE(cp_rs1_toggle, instr.rs1_value, 1)
@ -1223,8 +1223,8 @@ covergroup cg_cs(
ignore_bins NON_ZERO_OFF = {NON_ZERO} `WITH (rs2_is_signed);
}
cp_rs1: coverpoint instr.c_rs1s;
cp_rs2: coverpoint instr.c_rs2s;
cp_c_rs1: coverpoint instr.c_rs1;
cp_c_rs2: coverpoint instr.c_rs2;
`ISACOV_CP_BITWISE(cp_rs2_toggle, instr.rs2_value, 1)
`ISACOV_CP_BITWISE(cp_rs1_toggle, instr.rs1_value, 1)
@ -1263,11 +1263,10 @@ covergroup cg_ca(
ignore_bins NON_ZERO_OFF = {NON_ZERO} `WITH (rd_is_signed);
}
cp_rs1: coverpoint instr.c_rs1s;
cp_rs2: coverpoint instr.c_rs2s;
cp_rd: coverpoint instr.c_rdp;
cp_c_rs2: coverpoint instr.c_rs2;
cp_c_rdrs1: coverpoint instr.c_rs1;
cross_rs1_rs2: cross cp_rs1, cp_rs2 {
cross_rs1_rs2: cross cp_c_rs2, cp_c_rdrs1 {
ignore_bins IGN_OFF = cross_rs1_rs2 `WITH (!reg_crosses_enabled);
}
@ -1299,7 +1298,7 @@ covergroup cg_cb(
ignore_bins NON_ZERO_OFF = {NON_ZERO} `WITH (imm_is_signed);
}
cp_rs1: coverpoint instr.c_rs1s;
cp_c_rs1: coverpoint instr.c_rs1;
`ISACOV_CP_BITWISE(cp_rs1_toggle, instr.rs1_value, 1)
`ISACOV_CP_BITWISE_7_0(cp_imm_toggle, instr.get_field_imm(), 1)
@ -1328,7 +1327,7 @@ covergroup cg_cb_andi(
ignore_bins NON_ZERO_OFF = {NON_ZERO} `WITH (imm_is_signed);
}
cp_rs1: coverpoint instr.rs1;
cp_c_rdrs1: coverpoint instr.c_rs1;
`ISACOV_CP_BITWISE(cp_rs1_toggle, instr.rs1_value, 1)
`ISACOV_CP_BITWISE_5_0(cp_imm_toggle, instr.get_field_imm(), 1)
@ -1355,7 +1354,7 @@ covergroup cg_cb_shift(
illegal_bins ILLEGAL_SHAMT[] = {[32:63]}; // MSB of the immediate value should be always zero
}
cp_rs1: coverpoint instr.rs1;
cp_c_rdrs1: coverpoint instr.c_rs1;
`ISACOV_CP_BITWISE(cp_rs1_toggle, instr.rs1_value, 1) // No need to toggle imm again because cp_shamt did the job

51
lib/uvm_agents/uvma_isacov/uvma_isacov_instr.sv
View file

@ -48,10 +48,13 @@ class uvma_isacov_instr_c#(int ILEN=DEFAULT_ILEN,
bit rs2_valid;
bit rd_valid;
// rx for compressed instruction (5-bit encoding)
bit [4:0] c_rdrs1;
bit [2:0] c_rs1s;
bit [2:0] c_rs2s;
bit [2:0] c_rdp;
// rx for compressed instruction (3-bit encoding)
bit [2:0] c_rs1;
bit [2:0] c_rs2;
bit [2:0] c_rd;
bit[XLEN-1:0] rs1_value;
instr_value_t rs1_value_type;
@ -93,6 +96,11 @@ class uvma_isacov_instr_c#(int ILEN=DEFAULT_ILEN,
`uvm_field_int(rd_valid, UVM_ALL_ON | UVM_NOPRINT);
`uvm_field_enum(instr_value_t, rd_value_type, UVM_ALL_ON | UVM_NOPRINT);
`uvm_field_int(c_rdrs1, UVM_ALL_ON | UVM_NOPRINT);
`uvm_field_int(c_rs1, UVM_ALL_ON | UVM_NOPRINT);
`uvm_field_int(c_rs2, UVM_ALL_ON | UVM_NOPRINT);
`uvm_field_int(c_rd, UVM_ALL_ON | UVM_NOPRINT);
`uvm_field_int(immi, UVM_ALL_ON | UVM_NOPRINT);
`uvm_field_enum(instr_value_t, immi_value_type, UVM_ALL_ON | UVM_NOPRINT);
`uvm_field_int(imms, UVM_ALL_ON | UVM_NOPRINT);
@ -126,6 +134,10 @@ class uvma_isacov_instr_c#(int ILEN=DEFAULT_ILEN,
extern function int get_addr_rs1();
extern function int get_addr_rs2();
extern function int get_data_imm();
extern function int decode_rd_c(bit[ILEN-1:0] instr);
extern function int decode_rs1_c(bit[ILEN-1:0] instr);
extern function int decode_rs2_c(bit[ILEN-1:0] instr);
endclass : uvma_isacov_instr_c
@ -174,19 +186,19 @@ function string uvma_isacov_instr_c::convert2string();
instr_str = $sformatf("x%0d, %0d(x2)", this.get_addr_rs2(), this.get_data_imm());
end
if (itype == CIW_TYPE) begin
instr_str = $sformatf("x%0d, x2, %0d", this.get_addr_rd(), this.get_data_imm());
instr_str = $sformatf("x%0d, x2, %0d", this.decode_rd_c($signed(this.rvfi.insn)), this.get_data_imm());
end
if (itype == CL_TYPE) begin
instr_str = $sformatf("x%0d, x%0d, %0d", this.get_addr_rd(), this.get_addr_rs1(), get_data_imm());
instr_str = $sformatf("x%0d, %0d(x%0d)", this.decode_rd_c($signed(this.rvfi.insn)), this.get_data_imm(), this.decode_rs1_c($signed(this.rvfi.insn)));
end
if (itype == CS_TYPE) begin
instr_str = $sformatf("x%0d, %0d(x%0d)", this.get_addr_rs2, this.get_data_imm(), this.get_addr_rs1);
instr_str = $sformatf("x%0d, %0d(x%0d)", this.decode_rs2_c($signed(this.rvfi.insn)), this.get_data_imm(), this.decode_rs1_c($signed(this.rvfi.insn)));
end
if (itype == CA_TYPE) begin
instr_str = $sformatf("x%0d, x%0d", this.get_addr_rd(), this.get_addr_rs2());
instr_str = $sformatf("x%0d, x%0d", this.decode_rs1_c($signed(this.rvfi.insn)), this.decode_rs2_c($signed(this.rvfi.insn)));
end
if (itype == CB_TYPE) begin
instr_str = $sformatf("x%0d, %0x", this.get_addr_rs1(), ($signed(rvfi.pc_rdata) + this.get_data_imm()));
instr_str = $sformatf("x%0d, %0x", this.decode_rs1_c($signed(this.rvfi.insn)), ($signed(rvfi.pc_rdata) + this.get_data_imm()));
end
if (itype == CJ_TYPE) begin
instr_str = $sformatf("%0x", ($signed(rvfi.pc_rdata) + this.get_data_imm()));
@ -211,10 +223,10 @@ function string uvma_isacov_instr_c::convert2string();
instr_str = $sformatf("x%0d, 0x%0x", this.get_addr_rd(), this.get_data_imm());
end
if (name inside {C_SRAI, C_SRLI}) begin
instr_str = $sformatf("x%0d, 0x%0x", this.get_addr_rs1(), this.get_data_imm());
instr_str = $sformatf("x%0d, 0x%0x", this.decode_rs1_c($signed(this.rvfi.insn)), this.get_data_imm());
end
if (name == C_ANDI) begin
instr_str = $sformatf("x%0d, %0d", this.get_addr_rd(), $signed(this.get_data_imm()));
instr_str = $sformatf("x%0d, %0d", this.decode_rs1_c($signed(this.rvfi.insn)), $signed(this.get_data_imm()));
end
if (name == FENCE) begin
instr_str = "iorw, iorw"; // Note: If later found necessary, add support for `fence` arguments other than "iorw"
@ -480,7 +492,7 @@ function int uvma_isacov_instr_c::get_data_imm();
bit [63:0] instr = $signed(this.rvfi.insn);
int imm = this.get_field_imm();
if (this.itype inside {CSS_TYPE, CIW_TYPE, CS_TYPE}) begin
if (this.itype inside {CSS_TYPE, CIW_TYPE, CS_TYPE, CL_TYPE}) begin
return {imm, 2'b 00};
end
if (this.itype inside {CJ_TYPE} || this.name inside {C_BEQZ, C_BNEZ}) begin
@ -497,6 +509,23 @@ function int uvma_isacov_instr_c::get_data_imm();
endfunction : get_data_imm
function int uvma_isacov_instr_c::decode_rd_c(bit[ILEN-1:0] instr); //function to extract the rd' (3 bits) address from a compressed instruction
return instr[4:2] + 8;
endfunction : decode_rd_c
function int uvma_isacov_instr_c::decode_rs1_c(bit[ILEN-1:0] instr); //function to extract the rs1' (3 bits) address from a compressed instruction
return instr[9:7] + 8;
endfunction : decode_rs1_c
function int uvma_isacov_instr_c::decode_rs2_c(bit[ILEN-1:0] instr); //function to extract the rs2' (3 bits) address from a compressed instruction
return instr[4:2] + 8;
endfunction : decode_rs2_c
function bit uvma_isacov_instr_c::is_conditional_branch();

6
lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv
View file

@ -167,9 +167,9 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL
mon_trn.instr.rs2 = dasm_rvc_rs2(instr);
mon_trn.instr.rd = dasm_rvc_rd(instr);
mon_trn.instr.c_rdrs1 = dasm_rvc_rd(instr);
mon_trn.instr.c_rdp = dasm_rvc_rs1s(instr);
mon_trn.instr.c_rs1s = dasm_rvc_rs1s(instr);
mon_trn.instr.c_rs2s = dasm_rvc_rs2s(instr);
mon_trn.instr.c_rd = mon_trn.instr.decode_rd_c(instr);
mon_trn.instr.c_rs1 = mon_trn.instr.decode_rs1_c(instr);
mon_trn.instr.c_rs2 = mon_trn.instr.decode_rs2_c(instr);
end
else begin
mon_trn.instr.rs1 = dasm_rs1(instr);