mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-22 13:17:41 -04:00
Add test randomizer and align size of Spike memory
This commit is contained in:
Florian Zaruba
parent
c57d36079c
commit
b75839a5b1
9 changed files with 248 additions and 119 deletions
3
Makefile
3
Makefile
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@ -133,6 +133,7 @@ riscv-torture-bin := java -Xmx1G -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.
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ifdef batch-mode
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questa-flags += -c
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questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
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questa-cmd += -do " log -r /*; run -all;"
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else
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questa-cmd := -do " log -r /*; run -all;"
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endif
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@ -189,7 +190,7 @@ $(dpi-library)/ariane_dpi.so: $(dpi)
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sim: build
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vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log
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$(riscv-asm-tests): build
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Binary file not shown.
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@ -20,45 +20,44 @@ module bootrom (
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input logic [63:0] addr_i,
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output logic [63:0] rdata_o
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);
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localparam int RomSize = 232;
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localparam int RomSize = 224;
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const logic [RomSize-1:0][63:0] mem = {
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64'h006874_6469772d,
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64'h6f692d67_65720074,
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64'h66696873_2d676572,
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64'h00737470_75727265,
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64'h746e6900_746e6572,
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64'h61702d74_70757272,
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64'h65746e69_00646565,
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64'h70732d74_6e657272,
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64'h75630076_65646e2c,
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64'h76637369_72007974,
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64'h69726f69_72702d78,
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64'h616d2c76_63736972,
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64'h0073656d_616e2d67,
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64'h65720064_65646e65,
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64'h7478652d_73747075,
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64'h72726574_6e690073,
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64'h65676e61_7200656c,
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64'h646e6168_702c7875,
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64'h6e696c00_72656c6c,
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64'h6f72746e_6f632d74,
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64'h_006874,
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64'h6469772d_6f692d67,
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64'h65720074_66696873,
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64'h2d676572_00737470,
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64'h75727265_746e6900,
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64'h746e6572_61702d74,
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64'h70757272_65746e69,
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64'h00736c6c_65632d74,
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64'h70757272_65746e69,
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64'h23007469_6c70732d,
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64'h626c7400_65707974,
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64'h2d756d6d_00617369,
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64'h2c766373_69720073,
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64'h75746174_73006765,
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64'h72006570_79745f65,
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64'h63697665_64007963,
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64'h6e657571_6572662d,
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64'h6b636f6c_63007963,
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64'h6e657571_6572662d,
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64'h65736162_656d6974,
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64'h00687461_702d7475,
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64'h6f647473_006c6564,
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64'h00646565_70732d74,
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64'h6e657272_75630076,
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64'h65646e2c_76637369,
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64'h72007974_69726f69,
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64'h72702d78_616d2c76,
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64'h63736972_0073656d,
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64'h616e2d67_65720064,
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64'h65646e65_7478652d,
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64'h73747075_72726574,
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64'h6e690073_65676e61,
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64'h7200656c_646e6168,
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64'h702c7875_6e696c00,
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64'h72656c6c_6f72746e,
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64'h6f632d74_70757272,
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64'h65746e69_00736c6c,
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64'h65632d74_70757272,
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64'h65746e69_23007469,
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64'h6c70732d_626c7400,
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64'h65707974_2d756d6d,
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64'h00617369_2c766373,
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64'h69720073_75746174,
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64'h73006765_72006570,
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64'h79745f65_63697665,
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64'h64007963_6e657571,
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64'h6572662d_6b636f6c,
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64'h63007963_6e657571,
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64'h6572662d_65736162,
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64'h656d6974_006c6564,
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64'h6f6d0065_6c626974,
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64'h61706d6f_6300736c,
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64'h6c65632d_657a6973,
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@ -66,21 +65,21 @@ module bootrom (
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64'h73736572_64646123,
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64'h09000000_02000000,
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64'h02000000_02000000,
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64'h04000000_3a010000,
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64'h04000000_2e010000,
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64'h04000000_03000000,
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64'h02000000_30010000,
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64'h02000000_24010000,
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64'h04000000_03000000,
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64'h01000000_25010000,
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64'h01000000_19010000,
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64'h04000000_03000000,
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64'h02000000_14010000,
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64'h02000000_08010000,
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64'h04000000_03000000,
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64'h00c20100_06010000,
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64'h00c20100_fa000000,
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64'h04000000_03000000,
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64'h80f0fa02_4b000000,
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64'h80f0fa02_3f000000,
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64'h04000000_03000000,
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64'h00100000_00000000,
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64'h00000010_00000000,
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64'h67000000_10000000,
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64'h5b000000_10000000,
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64'h03000000_00303537,
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64'h3631736e_1b000000,
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64'h08000000_03000000,
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@ -88,13 +87,13 @@ module bootrom (
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64'h30303140_74726175,
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64'h01000000_02000000,
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64'h006c6f72_746e6f63,
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64'hde000000_08000000,
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64'hd2000000_08000000,
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64'h03000000_00100000,
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64'h00000000_00000000,
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64'h00000000_67000000,
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64'h00000000_5b000000,
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64'h10000000_03000000,
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64'hffff0000_01000000,
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64'hca000000_08000000,
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64'hbe000000_08000000,
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64'h03000000_00333130,
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64'h2d677562_65642c76,
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64'h63736972_1b000000,
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@ -103,26 +102,26 @@ module bootrom (
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64'h6f72746e_6f632d67,
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64'h75626564_01000000,
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64'h02000000_02000000,
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64'hbb000000_04000000,
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64'haf000000_04000000,
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64'h03000000_02000000,
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64'hb5000000_04000000,
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64'ha9000000_04000000,
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64'h03000000_02000000,
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64'hfb000000_04000000,
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64'hef000000_04000000,
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64'h03000000_07000000,
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64'he8000000_04000000,
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64'hdc000000_04000000,
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64'h03000000_00000004,
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64'h00000000_0000000c,
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64'h00000000_67000000,
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64'h00000000_5b000000,
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64'h10000000_03000000,
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64'h09000000_01000000,
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64'h0b000000_01000000,
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64'hca000000_10000000,
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64'h03000000_a0000000,
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64'hbe000000_10000000,
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64'h03000000_94000000,
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64'h00000000_03000000,
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64'h00306369_6c702c76,
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64'h63736972_1b000000,
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64'h0c000000_03000000,
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64'h01000000_8f000000,
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64'h01000000_83000000,
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64'h04000000_03000000,
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64'h00000000_00000000,
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64'h04000000_03000000,
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@ -132,21 +131,21 @@ module bootrom (
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64'h70757272_65746e69,
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64'h01000000_02000000,
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64'h006c6f72_746e6f63,
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64'hde000000_08000000,
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64'hd2000000_08000000,
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64'h03000000_00000c00,
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64'h00000000_00000002,
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64'h00000000_67000000,
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64'h00000000_5b000000,
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64'h10000000_03000000,
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64'h07000000_01000000,
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64'h03000000_01000000,
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64'hca000000_10000000,
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64'hbe000000_10000000,
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64'h03000000_00000000,
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64'h30746e69_6c632c76,
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64'h63736972_1b000000,
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64'h0d000000_03000000,
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64'h00000030_30303030,
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64'h30324074_6e696c63,
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64'h01000000_c3000000,
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64'h01000000_b7000000,
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64'h00000000_03000000,
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64'h00007375_622d656c,
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64'h706d6973_00636f73,
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@ -161,64 +160,57 @@ module bootrom (
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64'h01000000_02000000,
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64'h00000008_00000000,
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64'h00000080_00000000,
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64'h67000000_10000000,
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64'h5b000000_10000000,
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64'h03000000_00007972,
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64'h6f6d656d_5b000000,
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64'h6f6d656d_4f000000,
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64'h07000000_03000000,
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64'h00303030_30303030,
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64'h38407972_6f6d656d,
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64'h01000000_02000000,
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64'h02000000_02000000,
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64'h01000000_bb000000,
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64'h01000000_af000000,
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64'h04000000_03000000,
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64'h01000000_b5000000,
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64'h01000000_a9000000,
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64'h04000000_03000000,
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64'h00006374_6e692d75,
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64'h70632c76_63736972,
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64'h1b000000_0f000000,
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64'h03000000_a0000000,
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64'h03000000_94000000,
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64'h00000000_03000000,
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64'h01000000_8f000000,
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64'h01000000_83000000,
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64'h04000000_03000000,
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64'h00000000_72656c6c,
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64'h6f72746e_6f632d74,
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64'h70757272_65746e69,
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64'h01000000_85000000,
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64'h01000000_79000000,
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64'h00000000_03000000,
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64'h00003933_76732c76,
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64'h63736972_7c000000,
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64'h63736972_70000000,
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64'h0b000000_03000000,
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64'h00007573_63616d69,
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64'h34367672_72000000,
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64'h34367672_66000000,
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64'h0b000000_03000000,
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64'h00000076_63736972,
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64'h00656e61_69726120,
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64'h2c687465_1b000000,
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64'h12000000_03000000,
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64'h00000000_79616b6f,
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64'h6b000000_05000000,
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64'h5f000000_05000000,
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64'h03000000_00000000,
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64'h67000000_04000000,
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64'h03000000_00757063,
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64'h5b000000_04000000,
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64'h03000000_00757063,
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64'h4f000000_04000000,
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64'h03000000_80f0fa02,
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64'h4b000000_04000000,
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64'h3f000000_04000000,
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64'h03000000_00000030,
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64'h40757063_01000000,
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64'h40787d01_38000000,
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64'h40787d01_2c000000,
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64'h04000000_03000000,
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64'h00000000_0f000000,
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64'h04000000_03000000,
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64'h01000000_00000000,
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64'h04000000_03000000,
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64'h00000000_73757063,
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64'h01000000_02000000,
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64'h00000030_30323531,
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64'h313a3030_30303030,
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64'h30314074_7261752f,
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64'h636f732f_2c000000,
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64'h1a000000_03000000,
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64'h00006e65_736f6863,
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64'h01000000_00657261,
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64'h622d656e_61697261,
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64'h2c687465_26000000,
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@ -234,11 +226,11 @@ module bootrom (
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64'h00000000_01000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h40050000_47010000,
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64'h08050000_3b010000,
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64'h00000000_10000000,
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64'h11000000_28000000,
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64'h78050000_38000000,
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64'hbf060000_edfe0dd0,
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64'h40050000_38000000,
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64'h7b060000_edfe0dd0,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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2
src/axi
2
src/axi
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@ -1 +1 @@
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Subproject commit 50c23985e4ea063dd4aa919101ce16c4e48624ac
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Subproject commit de1af467229315ee6af31fea96664c7aae5638a9
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@ -1 +1 @@
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Subproject commit ef352e68becc9e33c64f5b051ad05c3d86b4d598
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Subproject commit 0a5067404ea76ed3cbaa7e75ccee0b3d76c57689
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36
src/mmu.sv
36
src/mmu.sv
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@ -156,24 +156,24 @@ module mmu #(
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.*
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);
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ila_1 i_ila_1 (
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.clk(clk_i), // input wire clk
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.probe0({req_port_o.address_tag, req_port_o.address_index}),
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.probe1(req_port_o.data_req), // input wire [63:0] probe1
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.probe2(req_port_i.data_gnt), // input wire [0:0] probe2
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.probe3(req_port_i.data_rdata), // input wire [0:0] probe3
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.probe4(req_port_i.data_rvalid), // input wire [0:0] probe4
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.probe5(ptw_error), // input wire [1:0] probe5
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.probe6(update_vaddr), // input wire [0:0] probe6
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.probe7(update_ptw_itlb.valid), // input wire [0:0] probe7
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.probe8(update_ptw_dtlb.valid), // input wire [0:0] probe8
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.probe9(dtlb_lu_access), // input wire [0:0] probe9
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.probe10(lsu_vaddr_i), // input wire [0:0] probe10
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.probe11(dtlb_lu_hit), // input wire [0:0] probe11
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.probe12(itlb_lu_access), // input wire [0:0] probe12
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.probe13(icache_areq_i.fetch_vaddr), // input wire [0:0] probe13
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.probe14(itlb_lu_hit) // input wire [0:0] probe13
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);
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// ila_1 i_ila_1 (
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// .clk(clk_i), // input wire clk
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// .probe0({req_port_o.address_tag, req_port_o.address_index}),
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// .probe1(req_port_o.data_req), // input wire [63:0] probe1
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// .probe2(req_port_i.data_gnt), // input wire [0:0] probe2
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// .probe3(req_port_i.data_rdata), // input wire [0:0] probe3
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// .probe4(req_port_i.data_rvalid), // input wire [0:0] probe4
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// .probe5(ptw_error), // input wire [1:0] probe5
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// .probe6(update_vaddr), // input wire [0:0] probe6
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// .probe7(update_ptw_itlb.valid), // input wire [0:0] probe7
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// .probe8(update_ptw_dtlb.valid), // input wire [0:0] probe8
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// .probe9(dtlb_lu_access), // input wire [0:0] probe9
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// .probe10(lsu_vaddr_i), // input wire [0:0] probe10
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// .probe11(dtlb_lu_hit), // input wire [0:0] probe11
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// .probe12(itlb_lu_access), // input wire [0:0] probe12
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// .probe13(icache_areq_i.fetch_vaddr), // input wire [0:0] probe13
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// .probe14(itlb_lu_hit) // input wire [0:0] probe13
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// );
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//-----------------------
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// Instruction Interface
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@ -56,7 +56,9 @@ module ariane_tb;
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// `ifdef TANDEM
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// initial $display("Tandem defined",);
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spike i_spike (
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spike #(
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.Size ( NUM_WORDS * 8 )
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) i_spike (
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.clk_i,
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.rst_ni,
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.clint_tick_i ( rtc_i ),
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@ -15,7 +15,7 @@
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module ariane_testharness #(
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parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
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parameter int unsigned AXI_ID_WIDTH = 10,
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parameter int unsigned AXI_ID_WIDTH = 2,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_ADDRESS_WIDTH = 64,
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parameter int unsigned AXI_DATA_WIDTH = 64,
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@ -226,6 +226,14 @@ module ariane_testharness #(
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// ---------------
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// Memory
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// ---------------
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||||
|
||||
AXI_BUS #(
|
||||
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
|
||||
.AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ),
|
||||
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
|
||||
) dram();
|
||||
|
||||
logic req;
|
||||
logic we;
|
||||
logic [AXI_ADDRESS_WIDTH-1:0] addr;
|
||||
|
|
@ -233,21 +241,147 @@ module ariane_testharness #(
|
|||
logic [AXI_DATA_WIDTH-1:0] wdata;
|
||||
logic [AXI_DATA_WIDTH-1:0] rdata;
|
||||
|
||||
axi_pkg::aw_chan_t aw_chan_i;
|
||||
axi_pkg::w_chan_t w_chan_i;
|
||||
axi_pkg::b_chan_t b_chan_o;
|
||||
axi_pkg::ar_chan_t ar_chan_i;
|
||||
axi_pkg::r_chan_t r_chan_o;
|
||||
axi_pkg::aw_chan_t aw_chan_o;
|
||||
axi_pkg::w_chan_t w_chan_o;
|
||||
axi_pkg::b_chan_t b_chan_i;
|
||||
axi_pkg::ar_chan_t ar_chan_o;
|
||||
axi_pkg::r_chan_t r_chan_i;
|
||||
|
||||
axi_delayer #(
|
||||
.aw_t ( axi_pkg::aw_chan_t ),
|
||||
.w_t ( axi_pkg::w_chan_t ),
|
||||
.b_t ( axi_pkg::b_chan_t ),
|
||||
.ar_t ( axi_pkg::ar_chan_t ),
|
||||
.r_t ( axi_pkg::r_chan_t ),
|
||||
.StallRandomOutput ( 1 ),
|
||||
.StallRandomInput ( 1 ),
|
||||
.FixedDelayInput ( 0 ),
|
||||
.FixedDelayOutput ( 0 )
|
||||
) i_axi_delayer (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( ndmreset_n ),
|
||||
.aw_valid_i ( master[ariane_soc::DRAM].aw_valid ),
|
||||
.aw_chan_i ( aw_chan_i ),
|
||||
.aw_ready_o ( master[ariane_soc::DRAM].aw_ready ),
|
||||
.w_valid_i ( master[ariane_soc::DRAM].w_valid ),
|
||||
.w_chan_i ( w_chan_i ),
|
||||
.w_ready_o ( master[ariane_soc::DRAM].w_ready ),
|
||||
.b_valid_o ( master[ariane_soc::DRAM].b_valid ),
|
||||
.b_chan_o ( b_chan_o ),
|
||||
.b_ready_i ( master[ariane_soc::DRAM].b_ready ),
|
||||
.ar_valid_i ( master[ariane_soc::DRAM].ar_valid ),
|
||||
.ar_chan_i ( ar_chan_i ),
|
||||
.ar_ready_o ( master[ariane_soc::DRAM].ar_ready ),
|
||||
.r_valid_o ( master[ariane_soc::DRAM].r_valid ),
|
||||
.r_chan_o ( r_chan_o ),
|
||||
.r_ready_i ( master[ariane_soc::DRAM].r_ready ),
|
||||
.aw_valid_o ( dram.aw_valid ),
|
||||
.aw_chan_o ( aw_chan_o ),
|
||||
.aw_ready_i ( dram.aw_ready ),
|
||||
.w_valid_o ( dram.w_valid ),
|
||||
.w_chan_o ( w_chan_o ),
|
||||
.w_ready_i ( dram.w_ready ),
|
||||
.b_valid_i ( dram.b_valid ),
|
||||
.b_chan_i ( b_chan_i ),
|
||||
.b_ready_o ( dram.b_ready ),
|
||||
.ar_valid_o ( dram.ar_valid ),
|
||||
.ar_chan_o ( ar_chan_o ),
|
||||
.ar_ready_i ( dram.ar_ready ),
|
||||
.r_valid_i ( dram.r_valid ),
|
||||
.r_chan_i ( r_chan_i ),
|
||||
.r_ready_o ( dram.r_ready )
|
||||
);
|
||||
|
||||
assign aw_chan_i.id = master[ariane_soc::DRAM].aw_id;
|
||||
assign aw_chan_i.addr = master[ariane_soc::DRAM].aw_addr;
|
||||
assign aw_chan_i.len = master[ariane_soc::DRAM].aw_len;
|
||||
assign aw_chan_i.size = master[ariane_soc::DRAM].aw_size;
|
||||
assign aw_chan_i.burst = master[ariane_soc::DRAM].aw_burst;
|
||||
assign aw_chan_i.lock = master[ariane_soc::DRAM].aw_lock;
|
||||
assign aw_chan_i.cache = master[ariane_soc::DRAM].aw_cache;
|
||||
assign aw_chan_i.prot = master[ariane_soc::DRAM].aw_prot;
|
||||
assign aw_chan_i.qos = master[ariane_soc::DRAM].aw_qos;
|
||||
assign aw_chan_i.region = master[ariane_soc::DRAM].aw_region;
|
||||
|
||||
assign ar_chan_i.id = master[ariane_soc::DRAM].ar_id;
|
||||
assign ar_chan_i.addr = master[ariane_soc::DRAM].ar_addr;
|
||||
assign ar_chan_i.len = master[ariane_soc::DRAM].ar_len;
|
||||
assign ar_chan_i.size = master[ariane_soc::DRAM].ar_size;
|
||||
assign ar_chan_i.burst = master[ariane_soc::DRAM].ar_burst;
|
||||
assign ar_chan_i.lock = master[ariane_soc::DRAM].ar_lock;
|
||||
assign ar_chan_i.cache = master[ariane_soc::DRAM].ar_cache;
|
||||
assign ar_chan_i.prot = master[ariane_soc::DRAM].ar_prot;
|
||||
assign ar_chan_i.qos = master[ariane_soc::DRAM].ar_qos;
|
||||
assign ar_chan_i.region = master[ariane_soc::DRAM].ar_region;
|
||||
|
||||
assign w_chan_i.data = master[ariane_soc::DRAM].w_data;
|
||||
assign w_chan_i.strb = master[ariane_soc::DRAM].w_strb;
|
||||
assign w_chan_i.last = master[ariane_soc::DRAM].w_last;
|
||||
|
||||
assign master[ariane_soc::DRAM].r_id = r_chan_o.id;
|
||||
assign master[ariane_soc::DRAM].r_data = r_chan_o.data;
|
||||
assign master[ariane_soc::DRAM].r_resp = r_chan_o.resp;
|
||||
assign master[ariane_soc::DRAM].r_last = r_chan_o.last;
|
||||
|
||||
assign master[ariane_soc::DRAM].b_id = b_chan_o.id;
|
||||
assign master[ariane_soc::DRAM].b_resp = b_chan_o.resp;
|
||||
|
||||
|
||||
assign dram.aw_id = aw_chan_o.id;
|
||||
assign dram.aw_addr = aw_chan_o.addr;
|
||||
assign dram.aw_len = aw_chan_o.len;
|
||||
assign dram.aw_size = aw_chan_o.size;
|
||||
assign dram.aw_burst = aw_chan_o.burst;
|
||||
assign dram.aw_lock = aw_chan_o.lock;
|
||||
assign dram.aw_cache = aw_chan_o.cache;
|
||||
assign dram.aw_prot = aw_chan_o.prot;
|
||||
assign dram.aw_qos = aw_chan_o.qos;
|
||||
assign dram.aw_region = aw_chan_o.region;
|
||||
|
||||
assign dram.ar_id = ar_chan_o.id;
|
||||
assign dram.ar_addr = ar_chan_o.addr;
|
||||
assign dram.ar_len = ar_chan_o.len;
|
||||
assign dram.ar_size = ar_chan_o.size;
|
||||
assign dram.ar_burst = ar_chan_o.burst;
|
||||
assign dram.ar_lock = ar_chan_o.lock;
|
||||
assign dram.ar_cache = ar_chan_o.cache;
|
||||
assign dram.ar_prot = ar_chan_o.prot;
|
||||
assign dram.ar_qos = ar_chan_o.qos;
|
||||
assign dram.ar_region = ar_chan_o.region;
|
||||
|
||||
assign dram.w_data = w_chan_o.data;
|
||||
assign dram.w_strb = w_chan_o.strb;
|
||||
assign dram.w_last = w_chan_o.last;
|
||||
|
||||
assign r_chan_i.id = dram.r_id;
|
||||
assign r_chan_i.data = dram.r_data;
|
||||
assign r_chan_i.resp = dram.r_resp;
|
||||
assign r_chan_i.last = dram.r_last;
|
||||
|
||||
assign b_chan_i.id = dram.b_id;
|
||||
assign b_chan_i.resp = dram.b_resp;
|
||||
|
||||
|
||||
axi2mem #(
|
||||
.AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ),
|
||||
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
|
||||
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
|
||||
) i_axi2mem (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( ndmreset_n ),
|
||||
.slave ( master[ariane_soc::DRAM] ),
|
||||
.req_o ( req ),
|
||||
.we_o ( we ),
|
||||
.addr_o ( addr ),
|
||||
.be_o ( be ),
|
||||
.data_o ( wdata ),
|
||||
.data_i ( rdata )
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( ndmreset_n ),
|
||||
.slave ( dram ),
|
||||
.req_o ( req ),
|
||||
.we_o ( we ),
|
||||
.addr_o ( addr ),
|
||||
.be_o ( be ),
|
||||
.data_o ( wdata ),
|
||||
.data_i ( rdata )
|
||||
);
|
||||
|
||||
sram #(
|
||||
|
|
|
|||
|
|
@ -28,11 +28,11 @@ module spike #(
|
|||
input logic rst_ni,
|
||||
input logic clint_tick_i,
|
||||
input ariane_pkg::scoreboard_entry_t [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_instr_i,
|
||||
input logic [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_ack_i,
|
||||
input ariane_pkg::exception_t exception_i,
|
||||
input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][4:0] waddr_i,
|
||||
input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][63:0] wdata_i,
|
||||
input riscv::priv_lvl_t priv_lvl_i
|
||||
input logic [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_ack_i,
|
||||
input ariane_pkg::exception_t exception_i,
|
||||
input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][4:0] waddr_i,
|
||||
input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][63:0] wdata_i,
|
||||
input riscv::priv_lvl_t priv_lvl_i
|
||||
);
|
||||
static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue