mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 03:44:46 -04:00
Fix instruction tracer for superscalar mode (#2901)
This PR adapts the instr_tracer module to support superscalar mode.
This commit is contained in:
parent
7b3054156e
commit
b9da1d9e2d
2 changed files with 27 additions and 16 deletions
|
@ -29,11 +29,11 @@ module instr_tracer #(
|
||||||
input logic rstn,
|
input logic rstn,
|
||||||
input logic flush_unissued,
|
input logic flush_unissued,
|
||||||
input logic flush_all,
|
input logic flush_all,
|
||||||
input logic [31:0] instruction,
|
input logic [31:0] instruction [CVA6Cfg.NrIssuePorts-1:0],
|
||||||
input logic fetch_valid,
|
input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_valid,
|
||||||
input logic fetch_ack,
|
input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_ack,
|
||||||
input logic issue_ack, // issue acknowledged
|
input logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack, // issue acknowledged
|
||||||
input scoreboard_entry_t issue_sbe, // issue scoreboard entry
|
input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_sbe, // issue scoreboard entry
|
||||||
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr, // WB stage
|
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr, // WB stage
|
||||||
input logic [CVA6Cfg.NrCommitPorts-1:0][63:0] wdata,
|
input logic [CVA6Cfg.NrCommitPorts-1:0][63:0] wdata,
|
||||||
input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr,
|
input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr,
|
||||||
|
@ -106,20 +106,24 @@ module instr_tracer #(
|
||||||
// Instruction Decode
|
// Instruction Decode
|
||||||
// -------------------
|
// -------------------
|
||||||
// we are decoding an instruction
|
// we are decoding an instruction
|
||||||
if (fetch_valid && fetch_ack) begin
|
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; ++i) begin
|
||||||
decode_instruction = instruction;
|
if (fetch_valid[i] && fetch_ack[i]) begin
|
||||||
decode_queue.push_back(decode_instruction);
|
decode_instruction = instruction[i];
|
||||||
|
decode_queue.push_back(decode_instruction);
|
||||||
|
end
|
||||||
end
|
end
|
||||||
// -------------------
|
// -------------------
|
||||||
// Instruction Issue
|
// Instruction Issue
|
||||||
// -------------------
|
// -------------------
|
||||||
// we got a new issue ack, so put the element from the decode queue to
|
// we got a new issue ack, so put the element from the decode queue to
|
||||||
// the issue queue
|
// the issue queue
|
||||||
if (issue_ack && !flush_unissued) begin
|
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; ++i) begin
|
||||||
issue_instruction = decode_queue.pop_front();
|
if (issue_ack[i] && !flush_unissued) begin
|
||||||
issue_queue.push_back(issue_instruction);
|
issue_instruction = decode_queue.pop_front();
|
||||||
// also save the scoreboard entry to a separate issue queue
|
issue_queue.push_back(issue_instruction);
|
||||||
issue_sbe_queue.push_back(scoreboard_entry_t'(issue_sbe));
|
// also save the scoreboard entry to a separate issue queue
|
||||||
|
issue_sbe_queue.push_back(scoreboard_entry_t'(issue_sbe[i]));
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
// --------------------
|
// --------------------
|
||||||
|
|
13
core/cva6.sv
13
core/cva6.sv
|
@ -1662,6 +1662,13 @@ module cva6
|
||||||
`endif // PITON_ARIANE
|
`endif // PITON_ARIANE
|
||||||
|
|
||||||
`ifndef VERILATOR
|
`ifndef VERILATOR
|
||||||
|
|
||||||
|
logic [31:0] fetch_instructions[CVA6Cfg.NrIssuePorts-1:0];
|
||||||
|
|
||||||
|
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; ++i) begin
|
||||||
|
assign fetch_instructions[i] = fetch_entry_if_id[i].instruction;
|
||||||
|
end
|
||||||
|
|
||||||
instr_tracer #(
|
instr_tracer #(
|
||||||
.CVA6Cfg(CVA6Cfg),
|
.CVA6Cfg(CVA6Cfg),
|
||||||
.bp_resolve_t(bp_resolve_t),
|
.bp_resolve_t(bp_resolve_t),
|
||||||
|
@ -1675,9 +1682,9 @@ module cva6
|
||||||
.rstn(rst_ni),
|
.rstn(rst_ni),
|
||||||
.flush_unissued(flush_unissued_instr_ctrl_id),
|
.flush_unissued(flush_unissued_instr_ctrl_id),
|
||||||
.flush_all(flush_ctrl_ex),
|
.flush_all(flush_ctrl_ex),
|
||||||
.instruction(id_stage_i.fetch_entry_i[0].instruction),
|
.instruction(fetch_instructions),
|
||||||
.fetch_valid(id_stage_i.fetch_entry_valid_i[0]),
|
.fetch_valid(id_stage_i.fetch_entry_valid_i),
|
||||||
.fetch_ack(id_stage_i.fetch_entry_ready_o[0]),
|
.fetch_ack(id_stage_i.fetch_entry_ready_o),
|
||||||
.issue_ack(issue_stage_i.i_scoreboard.issue_ack_i),
|
.issue_ack(issue_stage_i.i_scoreboard.issue_ack_i),
|
||||||
.issue_sbe(issue_stage_i.i_scoreboard.issue_instr_o),
|
.issue_sbe(issue_stage_i.i_scoreboard.issue_instr_o),
|
||||||
.waddr(waddr_commit_id),
|
.waddr(waddr_commit_id),
|
||||||
|
|
Loading…
Add table
Reference in a new issue