Add core test sequence, simply waiting for now

tb/agents/core_if/core_if_driver.svh

@@ -37,6 +37,7 @@ class core_if_driver extends uvm_driver #(core_if_seq_item);
 
         // seq_item_port.item_done();
         m_vif.mck.test_en      <= 1'b0;
+        m_vif.mck.clock_en     <= 1'b1;
         m_vif.mck.boot_addr    <= 64'b0;
         m_vif.mck.core_id      <= 4'b0;
         m_vif.mck.cluster_id   <= 6'b0;
@@ -47,6 +48,7 @@ class core_if_driver extends uvm_driver #(core_if_seq_item);
 
         repeat (20) @(m_vif.mck);
         m_vif.mck.fetch_enable <= 1'b1;
+
     endtask : run_phase
 
     function void build_phase(uvm_phase phase);

tb/core_tb.sv

@@ -34,9 +34,9 @@ module core_tb;
         .cluster_id_i           ( core_if.cluster_id   ),
 
         .instr_if_address_o     ( instr_if.address     ),
-        .instr_if_data_req_o    ( instr_if.data_req & instr_if.data_req   ),
+        .instr_if_data_req_o    ( instr_if.data_req    ),
         .instr_if_data_be_o     ( instr_if.data_be     ),
-        .instr_if_data_gnt_i    ( instr_if.data_gnt    ),
+        .instr_if_data_gnt_i    ( instr_if.data_gnt & instr_if.data_req   ),
         .instr_if_data_rvalid_i ( instr_if.data_rvalid ),
         .instr_if_data_rdata_i  ( instr_if.data_rdata  ),
 
@@ -81,6 +81,10 @@ module core_tb;
     program testbench (core_if core_if, mem_if instr_if);
         initial begin
             uvm_config_db #(virtual core_if)::set(null, "uvm_test_top", "core_if", core_if);
+            // print the topology
+            uvm_top.enable_print_topology = 1;
+            // Start UVM test
+            run_test();
         end
         // logic [7:0] imem [400];
         // logic [63:0] address [$];

tb/test/core/core_sequence.svh

@@ -0,0 +1,40 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 08.05.2017
+// Description: Core test sequence - simply waits for now
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+class core_sequence extends core_if_sequence;
+
+    `uvm_object_utils(core_sequence);
+
+    function new(string name = "core_sequence");
+       super.new(name);
+    endfunction : new
+
+    task body();
+        core_if_seq_item command;
+
+        command = core_if_seq_item::type_id::create("command");
+        `uvm_info("Core Sequence", "Starting Core Test", UVM_LOW)
+
+        for(int i = 0; i <= 100; i++) begin
+            start_item(command);
+
+            void'(command.randomize());
+
+            finish_item(command);
+        end
+        `uvm_info("Core Sequence", "Finished Core Test", UVM_LOW)
+    endtask : body
+endclass : core_sequence

tb/test/core/core_sequence_pkg.sv

@@ -21,5 +21,5 @@ package core_sequence_pkg;
 
     `include "uvm_macros.svh"
     // Include your sequences here e.g.:
-    // `include "fibonacci_sequence.svh"
+    `include "core_sequence.svh"
 endpackage

tb/test/core/core_test_base.svh

@@ -32,7 +32,7 @@ class core_test_base extends uvm_test;
     core_env m_env;
     core_if_sequencer sequencer_h;
 
-    // reset_sequence reset;
+    core_sequence m_core_sequence;
     // ---------------------
     // Agent configuration
     // ---------------------
@@ -75,8 +75,8 @@ class core_test_base extends uvm_test;
     endfunction
 
     task run_phase(uvm_phase phase);
-        // reset = new("reset");
-        // reset.start(sequencer_h);
+        m_core_sequence = new("m_core_sequence");
+        m_core_sequence.start(sequencer_h);
     endtask
 
 endclass : core_test_base