Add core memory stub

Makefile

@@ -24,7 +24,7 @@ sequences =  $(wildcard tb/sequences/*/*.sv)
 test_pkg = $(wildcard tb/test/*/*sequence_pkg.sv) $(wildcard tb/test/*/*_pkg.sv)
 
 # this list contains the standalone components
-src = $(wildcard src/*.sv)
+src = $(wildcard src/*.sv) $(wildcard tb/common/*.sv)
 # look for testbenches
 tbs = $(wildcard tb/*_tb.sv)
 

src/fifo.sv

@@ -78,15 +78,15 @@ module fifo #(
     // sequential process
     always_ff @(posedge clk_i or negedge rst_ni) begin
         if(~rst_ni) begin
-            read_pointer_q  <= '{default: 0};
-            write_pointer_q <= '{default: 0};
-            status_cnt_q    <= '{default: 0};
-            mem_q           <= '{default: 0};
+            read_pointer_q  <= '0;
+            write_pointer_q <= '0;
+            status_cnt_q    <= '0;
+            mem_q           <= '0;
         end else if (flush_i) begin
-            read_pointer_q  <= '{default: 0};
-            write_pointer_q <= '{default: 0};
-            status_cnt_q    <= '{default: 0};
-            mem_q           <= '{default: 0};
+            read_pointer_q  <= '0;
+            write_pointer_q <= '0;
+            status_cnt_q    <= '0;
+            mem_q           <= '0;
         end else begin
             read_pointer_q  <= read_pointer_n;
             write_pointer_q <= write_pointer_n;

tb/common/core_mem.sv

@@ -0,0 +1,43 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 23.05.2017
+// Description: Load Store Unit, handles address calculation and memory interface signals
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+//
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+//
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+//
+
+module core_mem (
+    input logic clk_i,    // Clock
+    input logic rst_ni,  // Asynchronous reset active low
+
+     // Instruction memory/cache
+    input  logic [63:0]              instr_if_address_i,
+    input  logic                     instr_if_data_req_i,
+    input  logic [3:0]               instr_if_data_be_i,
+    output logic                     instr_if_data_gnt_o,
+    output logic                     instr_if_data_rvalid_o,
+    output logic [31:0]              instr_if_data_rdata_o,
+    // Data memory/cache
+    input  logic [63:0]              data_if_address_i,
+    input  logic [63:0]              data_if_data_wdata_i,
+    input  logic                     data_if_data_req_i,
+    input  logic                     data_if_data_we_i,
+    input  logic [7:0]               data_if_data_be_i,
+    input  logic [1:0]               data_if_tag_status_i,
+    output logic                     data_if_data_gnt_o,
+    output logic                     data_if_data_rvalid_o,
+    output logic [63:0]              data_if_data_rdata_o
+);
+
+endmodule

tb/common/dp_ram.sv

@@ -0,0 +1,68 @@
+// Copyright 2015 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the “License”); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+module dp_ram
+  #(
+    parameter ADDR_WIDTH = 8
+  )(
+    // Clock and Reset
+    input  logic clk,
+
+    input  logic                   en_a_i,
+    input  logic [ADDR_WIDTH-1:0]  addr_a_i,
+    input  logic [31:0]            wdata_a_i,
+    output logic [31:0]            rdata_a_o,
+    input  logic                   we_a_i,
+    input  logic [3:0]             be_a_i,
+
+    input  logic                   en_b_i,
+    input  logic [ADDR_WIDTH-1:0]  addr_b_i,
+    input  logic [31:0]            wdata_b_i,
+    output logic [31:0]            rdata_b_o,
+    input  logic                   we_b_i,
+    input  logic [3:0]             be_b_i
+  );
+
+  localparam words = 2**ADDR_WIDTH;
+
+  logic [3:0][7:0] mem[words];
+
+  always @(posedge clk)
+  begin
+    if (en_a_i && we_a_i)
+    begin
+      if (be_a_i[0])
+        mem[addr_a_i][0] <= wdata_a_i[7:0];
+      if (be_a_i[1])
+        mem[addr_a_i][1] <= wdata_a_i[15:8];
+      if (be_a_i[2])
+        mem[addr_a_i][2] <= wdata_a_i[23:16];
+      if (be_a_i[3])
+        mem[addr_a_i][3] <= wdata_a_i[31:24];
+    end
+
+    rdata_a_o <= mem[addr_a_i];
+
+    if (en_b_i && we_b_i)
+    begin
+      if (be_b_i[0])
+        mem[addr_b_i][0] <= wdata_b_i[7:0];
+      if (be_b_i[1])
+        mem[addr_b_i][1] <= wdata_b_i[15:8];
+      if (be_b_i[2])
+        mem[addr_b_i][2] <= wdata_b_i[23:16];
+      if (be_b_i[3])
+        mem[addr_b_i][3] <= wdata_b_i[31:24];
+    end
+
+    rdata_b_o <= mem[addr_b_i];
+  end
+
+endmodule