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tb_*cache: Update source list (#776)

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Luca Colagrande 2021-12-07 15:23:37 +01:00 • committed by GitHub
parent 42aa48affd
commit bb9821d85f
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3 changed files with 59 additions and 56 deletions
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21
corev_apu/tb/tb_cva6_icache/tb.list
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@ -1,13 +1,14 @@
../../include/riscv_pkg.sv
../../src/riscv-dbg/src/dm_pkg.sv
../../include/ariane_pkg.sv
../../include/wt_cache_pkg.sv
../../src/fpga-support/rtl/SyncSpRamBeNx64.sv
../../src/cache_subsystem/cva6_icache.sv
../../src/common_cells/src/lfsr_8bit.sv
../../src/common_cells/src/fifo_v3.sv
../../src/common_cells/src/lzc.sv
../../src/util/sram.sv
../../../core/include/cv64a6_imafdc_sv39_config_pkg.sv
../../../core/include/riscv_pkg.sv
../../riscv-dbg/src/dm_pkg.sv
../../../core/include/ariane_pkg.sv
../../../core/include/wt_cache_pkg.sv
../../fpga-support/rtl/SyncSpRamBeNx64.sv
../../../core/cache_subsystem/cva6_icache.sv
../../../common/submodules/common_cells/src/lfsr.sv
../../../common/submodules/common_cells/src/fifo_v3.sv
../../../common/submodules/common_cells/src/lzc.sv
../../../common/local/util/sram.sv
hdl/mem_emul.sv
hdl/tlb_emul.sv
hdl/tb_pkg.sv

53
corev_apu/tb/tb_wb_dcache/tb.list
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@ -1,4 +1,5 @@
../../include/riscv_pkg.sv
../../../core/include/cv64a6_imafdc_sv39_config_pkg.sv
../../../core/include/riscv_pkg.sv
../common_verification/src/clk_rst_gen.sv
../common_verification/src/rand_id_queue.sv
../common_verification/src/rand_stream_mst.sv
@ -7,33 +8,33 @@
../common_verification/src/sim_timeout.sv
../common_verification/src/rand_synch_driver.sv
../common_verification/src/rand_stream_slv.sv
../../src/riscv-dbg/src/dm_pkg.sv
../../src/axi/src/axi_pkg.sv
../../src/axi/src/axi_intf.sv
../../src/axi/src/axi_test.sv
../../include/ariane_pkg.sv
../../riscv-dbg/src/dm_pkg.sv
../../axi/src/axi_pkg.sv
../../axi/src/axi_intf.sv
../../axi/src/axi_test.sv
../../../core/include/ariane_pkg.sv
../ariane_soc_pkg.sv
../ariane_axi_soc_pkg.sv
../../include/ariane_axi_pkg.sv
../../include/std_cache_pkg.sv
../../src/fpga-support/rtl/SyncSpRamBeNx64.sv
../../src/cache_subsystem/cache_ctrl.sv
../../src/cache_subsystem/miss_handler.sv
../../src/cache_subsystem/std_nbdcache.sv
../../src/cache_subsystem/amo_alu.sv
../../src/cache_subsystem/tag_cmp.sv
../../src/common_cells/src/cf_math_pkg.sv
../../src/common_cells/src/lfsr_8bit.sv
../../src/common_cells/src/fifo_v3.sv
../../src/common_cells/src/lzc.sv
../../src/common_cells/src/rr_arb_tree.sv
../../src/common_cells/src/exp_backoff.sv
../../src/common_cells/src/stream_arbiter.sv
../../src/common_cells/src/stream_arbiter_flushable.sv
../../src/common_cells/src/stream_mux.sv
../../src/common_cells/src/stream_demux.sv
../../src/axi_adapter.sv
../../src/util/sram.sv
../../../core/include/ariane_axi_pkg.sv
../../../core/include/std_cache_pkg.sv
../../fpga-support/rtl/SyncSpRamBeNx64.sv
../../../core/cache_subsystem/cache_ctrl.sv
../../../core/cache_subsystem/miss_handler.sv
../../../core/cache_subsystem/std_nbdcache.sv
../../../core/cache_subsystem/amo_alu.sv
../../../core/cache_subsystem/tag_cmp.sv
../../../common/submodules/common_cells/src/cf_math_pkg.sv
../../../common/submodules/common_cells/src/lfsr_8bit.sv
../../../common/submodules/common_cells/src/fifo_v3.sv
../../../common/submodules/common_cells/src/lzc.sv
../../../common/submodules/common_cells/src/rr_arb_tree.sv
../../../common/submodules/common_cells/src/exp_backoff.sv
../../../common/submodules/common_cells/src/stream_arbiter.sv
../../../common/submodules/common_cells/src/stream_arbiter_flushable.sv
../../../common/submodules/common_cells/src/stream_mux.sv
../../../common/submodules/common_cells/src/stream_demux.sv
../../../core/axi_adapter.sv
../../../common/local/util/sram.sv
../common/tb_dcache_pkg.sv
../common/tb_readport.sv

41
corev_apu/tb/tb_wt_dcache/tb.list
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@ -1,24 +1,25 @@
../../include/riscv_pkg.sv
../../src/riscv-dbg/src/dm_pkg.sv
../../../core/include/cv64a6_imafdc_sv39_config_pkg.sv
../../../core/include/riscv_pkg.sv
../../riscv-dbg/src/dm_pkg.sv
../common_verification/src/rand_id_queue.sv
../../src/axi/src/axi_pkg.sv
../../src/axi/src/axi_intf.sv
../../src/axi/src/axi_test.sv
../../include/ariane_pkg.sv
../../include/wt_cache_pkg.sv
../../src/fpga-support/rtl/SyncSpRamBeNx64.sv
../../src/cache_subsystem/wt_dcache_ctrl.sv
../../src/cache_subsystem/wt_dcache_mem.sv
../../src/cache_subsystem/wt_dcache_missunit.sv
../../src/cache_subsystem/wt_dcache_wbuffer.sv
../../src/cache_subsystem/wt_dcache.sv
../../src/common_cells/src/cf_math_pkg.sv
../../src/common_cells/src/lfsr_8bit.sv
../../src/common_cells/src/fifo_v3.sv
../../src/common_cells/src/lzc.sv
../../src/common_cells/src/rr_arb_tree.sv
../../src/common_cells/src/exp_backoff.sv
../../src/util/sram.sv
../../axi/src/axi_pkg.sv
../../axi/src/axi_intf.sv
../../axi/src/axi_test.sv
../../../core/include/ariane_pkg.sv
../../../core/include/wt_cache_pkg.sv
../../fpga-support/rtl/SyncSpRamBeNx64.sv
../../../core/cache_subsystem/wt_dcache_ctrl.sv
../../../core/cache_subsystem/wt_dcache_mem.sv
../../../core/cache_subsystem/wt_dcache_missunit.sv
../../../core/cache_subsystem/wt_dcache_wbuffer.sv
../../../core/cache_subsystem/wt_dcache.sv
../../../common/submodules/common_cells/src/cf_math_pkg.sv
../../../common/submodules/common_cells/src/lfsr.sv
../../../common/submodules/common_cells/src/fifo_v3.sv
../../../common/submodules/common_cells/src/lzc.sv
../../../common/submodules/common_cells/src/rr_arb_tree.sv
../../../common/submodules/common_cells/src/exp_backoff.sv
../../../common/local/util/sram.sv
../common/tb_dcache_pkg.sv
hdl/tb_mem.sv
../common/tb_readport.sv