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Merge branch 'master' of iis-git.ee.ethz.ch:floce/ariane

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This commit is contained in:
Florian Zaruba 2017-08-28 17:18:36 +02:00
commit bb9a67f8a3
6 changed files with 25 additions and 18 deletions
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5
Makefile
View file

@ -126,7 +126,7 @@ sim: build ariane_tb.dtb
simc: build ariane_tb.dtb
vsim${questa_version} -c -lib ${library} ${top_level}_optimized +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +ASMTEST=$(riscv-test) -coverage -classdebug
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
run-asm-tests: build ariane_tb.dtb
$(foreach test, $(riscv-tests), vsim$(questa_version) +BASEDIR=$(riscv-test-dir) +max-cycles=$(max_cycles) \
@ -175,6 +175,9 @@ lint:
verilator $(ariane_pkg) $(src) --lint-only \
$(list_incdir) --top-module ariane
verify:
qverify vlog -sv src/csr_regfile.sv
clean:
rm -rf work/ *.ucdb

9
src/csr_regfile.sv
View file

@ -467,6 +467,11 @@ module csr_regfile #(
csr_read = 1'b0;
end
endcase
// if we are retiring an exception do not return from exception
if (ex_i.valid) begin
mret = 1'b0;
sret = 1'b0;
end
// ------------------------------
// Debug Multiplexer (Priority)
// ------------------------------
@ -671,8 +676,8 @@ module csr_regfile #(
`ifndef VERILATOR
// check that eret and ex are never valid together
assert property (
@(posedge clk_i) !(eret_i && ex_valid_i))
else $warning("eret and exception should never be valid at the same time");
@(posedge clk_i) !(eret_o && ex_i.valid))
else begin $error("eret and exception should never be valid at the same time"); $stop(); end
`endif
`endif
endmodule

9
src/debug_unit.sv
View file

@ -153,8 +153,6 @@ module debug_unit (
if (debug_halted_o) begin
if (commit_instr_i.valid)
rdata_n = commit_instr_i.pc;
else
rdata_n = 64'hdeadbeefdeadbeef;
if (cause_is_bp_q)
// if the cause is a breakpoint we trick the debugger in assuming the next instruction
@ -163,8 +161,9 @@ module debug_unit (
rdata_n = dbg_ppc_q + 64'h2;
else
rdata_n = dbg_ppc_q + 64'h4;
// TODO: Breakpoint
end
// we are not in debug mode - so just report what we know: the last valid PC
end else
rdata_n = dbg_ppc_q;
// if we came from reset - output the boot address
if (reset_q)
rdata_n = boot_addr_i;
@ -251,7 +250,7 @@ module debug_unit (
// Debugger Signaling
// ------------------------
// if an exception occurred and it is enabled to trigger debug mode, halt the processor and enter debug mode
if (commit_ack_i && ex_i.valid && dbg_ie_q[ex_i.cause[5:0]]) begin
if (commit_ack_i && ex_i.valid && dbg_ie_q[ex_i.cause[5:0]] && (ex_i.cause[63] == dbg_ie_q[63])) begin
halt_req = 1'b1;
// save the cause why we entered the exception
dbg_cause_n = ex_i.cause;

2
src/decoder.sv
View file

@ -507,7 +507,7 @@ module decoder (
// ---------------------
always_comb begin : exception_handling
instruction_o.ex = ex_i;
instruction_o.valid = 1'b0;
instruction_o.valid = ex_i.valid;
// look if we didn't already get an exception in any previous
// stage - we should not overwrite it as we retain order regarding the exception
if (~ex_i.valid) begin

12
src/store_buffer.sv
View file

@ -25,8 +25,8 @@ module store_buffer (
// otherwise we will run in a deadlock with the memory arbiter
output logic no_st_pending_o, // non-speculative queue is empty (e.g.: everything is committed to the memory hierarchy)
input logic [11:0] page_offset_i,
output logic page_offset_matches_o,
input logic [11:0] page_offset_i, // check for the page offset (the last 12 bit if the current load matches them)
output logic page_offset_matches_o, // the above input page offset matches -> let the store buffer drain
input logic commit_i, // commit the instruction which was placed there most recently
output logic commit_ready_o, // commit queue is ready to accept another commit request
@ -119,7 +119,7 @@ module store_buffer (
speculative_status_cnt_n = speculative_status_cnt;
// when we flush evict the speculative stores
if (ready_o && flush_i) begin
if (flush_i) begin
// reset all valid flags
for (int unsigned i = 0; i < DEPTH_SPEC; i++)
speculative_queue_n[i].valid = 1'b0;
@ -260,15 +260,15 @@ module store_buffer (
`ifndef verilator
// assert that commit is never set when we are flushing this would be counter intuitive
// as flush and commit is decided in the same stage
assert property (
commit_and_flush: assert property (
@(posedge clk_i) rst_ni && flush_i |-> !commit_i)
else $error ("[Commit Queue] You are trying to commit and flush in the same cycle");
assert property (
speculative_buffer_overflow: assert property (
@(posedge clk_i) rst_ni && (speculative_status_cnt_q == DEPTH_SPEC) |-> !valid_i)
else $error ("[Speculative Queue] You are trying to push new data although the buffer is not ready");
assert property (
commit_buffer_overflow: assert property (
@(posedge clk_i) rst_ni && (commit_status_cnt_q == DEPTH_SPEC) |-> !commit_i)
else $error("[Commit Queue] You are trying to commit a store although the buffer is full");

6
src/store_unit.sv
View file

@ -19,9 +19,9 @@
import ariane_pkg::*;
module store_unit (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic flush_i,
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic flush_i,
output logic no_st_pending_o,
// store unit input port
input logic valid_i,