Add ID signal to the request interface towards the data cache (#1121)

core/cache_subsystem/cache_ctrl.sv

@@ -115,6 +115,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
         req_port_o.data_gnt    = 1'b0;
         req_port_o.data_rvalid = 1'b0;
         req_port_o.data_rdata  = '0;
+        req_port_o.data_rid    = '0;
         miss_req_o    = '0;
         mshr_addr_o   = '0;
         // Memory array communication

core/cache_subsystem/wt_dcache_ctrl.sv

@@ -78,6 +78,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
 
   assign req_port_o.data_rdata = rd_data_i;
   assign req_port_o.data_ruser = rd_user_i;
+  assign req_port_o.data_rid   = '0;
 
   // to miss unit
   assign miss_vld_bits_o       = vld_data_q;

core/cache_subsystem/wt_dcache_wbuffer.sv

@@ -397,6 +397,7 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
   assign req_port_o.data_rvalid = '0;
   assign req_port_o.data_rdata  = '0;
   assign req_port_o.data_ruser  = '0;
+  assign req_port_o.data_rid    = '0;
 
   assign rd_hit_oh_d = rd_hit_oh_i;
 

core/include/ariane_pkg.sv

@@ -467,6 +467,7 @@ package ariane_pkg;
     localparam int unsigned DCACHE_LINE_WIDTH  = cva6_config_pkg::CVA6ConfigDcacheLineWidth; // in bit
     localparam int unsigned DCACHE_USER_LINE_WIDTH  = (AXI_USER_WIDTH == 1) ? 4 : cva6_config_pkg::CVA6ConfigDcacheLineWidth; // in bit
     localparam int unsigned DCACHE_USER_WIDTH  = DATA_USER_WIDTH;
+    localparam int unsigned DCACHE_TID_WIDTH   = cva6_config_pkg::CVA6ConfigDcacheIdWidth;
 `endif
 
     // ---------------
@@ -803,6 +804,7 @@ package ariane_pkg;
         logic                          data_we;
         logic [(riscv::XLEN/8)-1:0]    data_be;
         logic [1:0]                    data_size;
+        logic [DCACHE_TID_WIDTH-1:0]   data_id;
         logic                          kill_req;
         logic                          tag_valid;
     } dcache_req_i_t;
@@ -810,6 +812,7 @@ package ariane_pkg;
     typedef struct packed {
         logic                          data_gnt;
         logic                          data_rvalid;
+        logic [DCACHE_TID_WIDTH-1:0]   data_rid;
         riscv::xlen_t                  data_rdata;
         logic [DCACHE_USER_WIDTH-1:0]  data_ruser;
     } dcache_req_o_t;

core/include/cv32a60x_config_pkg.sv

@@ -36,6 +36,8 @@ package cva6_config_pkg;
     localparam CVA6ConfigDcacheSetAssoc = 8;
     localparam CVA6ConfigDcacheLineWidth = 128;
 
+    localparam CVA6ConfigDcacheIdWidth = 1;
+
     localparam CVA6ConfigNrCommitPorts = 1;
     localparam CVA6ConfigNrScoreboardEntries = 4;
 

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -36,6 +36,8 @@ package cva6_config_pkg;
     localparam CVA6ConfigDcacheSetAssoc = 2;
     localparam CVA6ConfigDcacheLineWidth = 128;
 
+    localparam CVA6ConfigDcacheIdWidth = 1;
+
     localparam CVA6ConfigNrCommitPorts = 1;
     localparam CVA6ConfigNrScoreboardEntries = 4;
 

core/include/cv32a6_imac_sv0_config_pkg.sv

@@ -36,6 +36,8 @@ package cva6_config_pkg;
     localparam CVA6ConfigDcacheSetAssoc = 8;
     localparam CVA6ConfigDcacheLineWidth = 128;
 
+    localparam CVA6ConfigDcacheIdWidth = 1;
+
     localparam CVA6ConfigNrCommitPorts = 2;
     localparam CVA6ConfigNrScoreboardEntries = 8;
 

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -36,6 +36,8 @@ package cva6_config_pkg;
     localparam CVA6ConfigDcacheSetAssoc = 8;
     localparam CVA6ConfigDcacheLineWidth = 128;
 
+    localparam CVA6ConfigDcacheIdWidth = 1;
+
     localparam CVA6ConfigNrCommitPorts = 2;
     localparam CVA6ConfigNrScoreboardEntries = 8;
 

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -36,6 +36,8 @@ package cva6_config_pkg;
     localparam CVA6ConfigDcacheSetAssoc = 8;
     localparam CVA6ConfigDcacheLineWidth = 128;
 
+    localparam CVA6ConfigDcacheIdWidth = 1;
+
     localparam CVA6ConfigNrCommitPorts = 2;
     localparam CVA6ConfigNrScoreboardEntries = 8;
 

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -36,6 +36,8 @@ package cva6_config_pkg;
     localparam CVA6ConfigDcacheSetAssoc = 8;
     localparam CVA6ConfigDcacheLineWidth = 128;
 
+    localparam CVA6ConfigDcacheIdWidth = 1;
+
     localparam CVA6ConfigNrCommitPorts = 2;
     localparam CVA6ConfigNrScoreboardEntries = 8;
 

core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv

@@ -36,6 +36,8 @@ package cva6_config_pkg;
     localparam CVA6ConfigDcacheSetAssoc = 8;
     localparam CVA6ConfigDcacheLineWidth = 128;
 
+    localparam CVA6ConfigDcacheIdWidth = 1;
+
     localparam CVA6ConfigNrCommitPorts = 2;
     localparam CVA6ConfigNrScoreboardEntries = 8;
 

core/load_unit.sv

@@ -73,6 +73,8 @@ module load_unit import ariane_pkg::*; #(
     assign req_port_o.address_tag   = paddr_i[ariane_pkg::DCACHE_TAG_WIDTH     +
                                               ariane_pkg::DCACHE_INDEX_WIDTH-1 :
                                               ariane_pkg::DCACHE_INDEX_WIDTH];
+    // we only issue one single request at a time
+    assign req_port_o.data_id = '0;
     // directly forward exception fields (valid bit is set below)
     assign ex_o.cause = ex_i.cause;
     assign ex_o.tval  = ex_i.tval;

core/mmu_sv32/cva6_ptw_sv32.sv

@@ -121,7 +121,9 @@ module cva6_ptw_sv32 import ariane_pkg::*; #(
     assign req_port_o.kill_req      = '0;
     // we are never going to write with the HPTW
     assign req_port_o.data_wdata    = '0;
-    
+    // we only issue one single request at a time
+    assign req_port_o.data_id       = '0;
+
     // -----------
     // Shared TLB Update
     // -----------

core/mmu_sv39/ptw.sv

@@ -112,6 +112,8 @@ module ptw import ariane_pkg::*; #(
     assign req_port_o.kill_req      = '0;
     // we are never going to write with the HPTW
     assign req_port_o.data_wdata    = 64'b0;
+    // we only issue one single request at a time
+    assign req_port_o.data_id       = '0;
     // -----------
     // TLB Update
     // -----------

core/store_buffer.sv

@@ -128,6 +128,8 @@ module store_buffer import ariane_pkg::*; (
     assign req_port_o.data_we   = 1'b1; // we will always write in the store queue
     assign req_port_o.tag_valid = 1'b0;
 
+    // we do not require an acknowledgement for writes, thus we do not need to identify uniquely the responses
+    assign req_port_o.data_id       = '0;
     // those signals can directly be output to the memory
     assign req_port_o.address_index = commit_queue_q[commit_read_pointer_q].address[ariane_pkg::DCACHE_INDEX_WIDTH-1:0];
     // if we got a new request we already saved the tag from the previous cycle