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Parametrization step 3 part 3 (last) (#1940)
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64 changed files with 703 additions and 675 deletions
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@ -25,7 +25,7 @@ module instr_tracer #(
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parameter interrupts_t INTERRUPTS = '0
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)(
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instr_tracer_if tracer_if,
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input logic[riscv::XLEN-1:0] hart_id_i
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input logic[CVA6Cfg.XLEN-1:0] hart_id_i
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);
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// keep the decoded instructions in a queue
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@ -27,8 +27,8 @@ module acc_dispatcher
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logic req_valid;
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logic resp_ready;
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riscv::instruction_t insn;
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logic [riscv::XLEN-1:0] rs1;
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logic [riscv::XLEN-1:0] rs2;
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logic [CVA6Cfg.XLEN-1:0] rs1;
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logic [CVA6Cfg.XLEN-1:0] rs2;
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fpnew_pkg::roundmode_e frm;
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logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
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logic store_pending;
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@ -40,7 +40,7 @@ module acc_dispatcher
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parameter type acc_resp_t = struct packed {
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logic req_ready;
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logic resp_valid;
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logic [riscv::XLEN-1:0] result;
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logic [CVA6Cfg.XLEN-1:0] result;
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logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
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logic error;
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// Metadata
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@ -76,7 +76,7 @@ module acc_dispatcher
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input fu_data_t fu_data_i,
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input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
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output logic [CVA6Cfg.TRANS_ID_BITS-1:0] acc_trans_id_o,
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output logic [riscv::XLEN-1:0] acc_result_o,
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output logic [CVA6Cfg.XLEN-1:0] acc_result_o,
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output logic acc_valid_o,
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output exception_t acc_exception_o,
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// Interface with the execute stage
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123
core/alu.sv
123
core/alu.sv
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@ -31,30 +31,30 @@ module alu
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// FU data needed to execute instruction - ISSUE_STAGE
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input fu_data_t fu_data_i,
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// ALU result - ISSUE_STAGE
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output logic [riscv::XLEN-1:0] result_o,
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output logic [CVA6Cfg.XLEN-1:0] result_o,
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// ALU branch compare result - branch_unit
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output logic alu_branch_res_o
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);
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logic [riscv::XLEN-1:0] operand_a_rev;
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logic [ 31:0] operand_a_rev32;
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logic [ riscv::XLEN:0] operand_b_neg;
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logic [riscv::XLEN+1:0] adder_result_ext_o;
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logic less; // handles both signed and unsigned forms
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logic [ 31:0] rolw; // Rotate Left Word
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logic [ 31:0] rorw; // Rotate Right Word
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logic [CVA6Cfg.XLEN-1:0] operand_a_rev;
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logic [ 31:0] operand_a_rev32;
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logic [ CVA6Cfg.XLEN:0] operand_b_neg;
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logic [CVA6Cfg.XLEN+1:0] adder_result_ext_o;
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logic less; // handles both signed and unsigned forms
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logic [ 31:0] rolw; // Rotate Left Word
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logic [ 31:0] rorw; // Rotate Right Word
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logic [31:0] orcbw, rev8w;
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logic [ $clog2(riscv::XLEN) : 0] cpop; // Count Population
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logic [$clog2(riscv::XLEN)-1 : 0] lz_tz_count; // Count Leading Zeros
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logic [ 4:0] lz_tz_wcount; // Count Leading Zeros Word
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logic [ $clog2(CVA6Cfg.XLEN) : 0] cpop; // Count Population
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logic [$clog2(CVA6Cfg.XLEN)-1 : 0] lz_tz_count; // Count Leading Zeros
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logic [ 4:0] lz_tz_wcount; // Count Leading Zeros Word
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logic lz_tz_empty, lz_tz_wempty;
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logic [riscv::XLEN-1:0] orcbw_result, rev8w_result;
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logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result;
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// bit reverse operand_a for left shifts and bit counting
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generate
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genvar k;
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for (k = 0; k < riscv::XLEN; k++)
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assign operand_a_rev[k] = fu_data_i.operand_a[riscv::XLEN-1-k];
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for (k = 0; k < CVA6Cfg.XLEN; k++)
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assign operand_a_rev[k] = fu_data_i.operand_a[CVA6Cfg.XLEN-1-k];
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for (k = 0; k < 32; k++) assign operand_a_rev32[k] = fu_data_i.operand_a[31-k];
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endgenerate
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@ -64,9 +64,9 @@ module alu
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// ------
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logic adder_op_b_negate;
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logic adder_z_flag;
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logic [riscv::XLEN:0] adder_in_a, adder_in_b;
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logic [riscv::XLEN-1:0] adder_result;
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logic [riscv::XLEN-1:0] operand_a_bitmanip, bit_indx;
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logic [CVA6Cfg.XLEN:0] adder_in_a, adder_in_b;
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logic [CVA6Cfg.XLEN-1:0] adder_result;
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logic [CVA6Cfg.XLEN-1:0] operand_a_bitmanip, bit_indx;
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always_comb begin
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adder_op_b_negate = 1'b0;
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@ -106,12 +106,12 @@ module alu
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assign adder_in_a = {operand_a_bitmanip, 1'b1};
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// prepare operand b
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assign operand_b_neg = {fu_data_i.operand_b, 1'b0} ^ {riscv::XLEN + 1{adder_op_b_negate}};
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assign operand_b_neg = {fu_data_i.operand_b, 1'b0} ^ {CVA6Cfg.XLEN + 1{adder_op_b_negate}};
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assign adder_in_b = operand_b_neg;
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// actual adder
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assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
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assign adder_result = adder_result_ext_o[riscv::XLEN:1];
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assign adder_result = adder_result_ext_o[CVA6Cfg.XLEN:1];
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assign adder_z_flag = ~|adder_result;
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// get the right branch comparison result
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@ -132,21 +132,21 @@ module alu
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// ---------
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// TODO: this can probably optimized significantly
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logic shift_left; // should we shift left
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logic shift_arithmetic;
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logic shift_left; // should we shift left
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logic shift_arithmetic;
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logic [riscv::XLEN-1:0] shift_amt; // amount of shift, to the right
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logic [riscv::XLEN-1:0] shift_op_a; // input of the shifter
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logic [ 31:0] shift_op_a32; // input to the 32 bit shift operation
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logic [CVA6Cfg.XLEN-1:0] shift_amt; // amount of shift, to the right
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logic [CVA6Cfg.XLEN-1:0] shift_op_a; // input of the shifter
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logic [ 31:0] shift_op_a32; // input to the 32 bit shift operation
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logic [riscv::XLEN-1:0] shift_result;
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logic [ 31:0] shift_result32;
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logic [CVA6Cfg.XLEN-1:0] shift_result;
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logic [ 31:0] shift_result32;
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logic [ riscv::XLEN:0] shift_right_result;
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logic [ 32:0] shift_right_result32;
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logic [ CVA6Cfg.XLEN:0] shift_right_result;
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logic [ 32:0] shift_right_result32;
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logic [riscv::XLEN-1:0] shift_left_result;
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logic [ 31:0] shift_left_result32;
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logic [CVA6Cfg.XLEN-1:0] shift_left_result;
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logic [ 31:0] shift_left_result32;
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assign shift_amt = fu_data_i.operand_b;
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@ -155,14 +155,14 @@ module alu
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assign shift_arithmetic = (fu_data_i.operation == SRA) | (fu_data_i.operation == SRAW);
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// right shifts, we let the synthesizer optimize this
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logic [riscv::XLEN:0] shift_op_a_64;
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logic [CVA6Cfg.XLEN:0] shift_op_a_64;
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logic [32:0] shift_op_a_32;
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// choose the bit reversed or the normal input for shift operand a
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assign shift_op_a = shift_left ? operand_a_rev : fu_data_i.operand_a;
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assign shift_op_a32 = shift_left ? operand_a_rev32 : fu_data_i.operand_a[31:0];
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assign shift_op_a_64 = {shift_arithmetic & shift_op_a[riscv::XLEN-1], shift_op_a};
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assign shift_op_a_64 = {shift_arithmetic & shift_op_a[CVA6Cfg.XLEN-1], shift_op_a};
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assign shift_op_a_32 = {shift_arithmetic & shift_op_a[31], shift_op_a32};
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assign shift_right_result = $unsigned($signed(shift_op_a_64) >>> shift_amt[5:0]);
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@ -171,14 +171,14 @@ module alu
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// bit reverse the shift_right_result for left shifts
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genvar j;
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generate
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for (j = 0; j < riscv::XLEN; j++)
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assign shift_left_result[j] = shift_right_result[riscv::XLEN-1-j];
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for (j = 0; j < CVA6Cfg.XLEN; j++)
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assign shift_left_result[j] = shift_right_result[CVA6Cfg.XLEN-1-j];
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for (j = 0; j < 32; j++) assign shift_left_result32[j] = shift_right_result32[31-j];
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endgenerate
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assign shift_result = shift_left ? shift_left_result : shift_right_result[riscv::XLEN-1:0];
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assign shift_result = shift_left ? shift_left_result : shift_right_result[CVA6Cfg.XLEN-1:0];
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assign shift_result32 = shift_left ? shift_left_result32 : shift_right_result32[31:0];
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// ------------
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@ -196,15 +196,15 @@ module alu
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(fu_data_i.operation == MIN))
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sgn = 1'b1;
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less = ($signed({sgn & fu_data_i.operand_a[riscv::XLEN-1], fu_data_i.operand_a}) <
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$signed({sgn & fu_data_i.operand_b[riscv::XLEN-1], fu_data_i.operand_b}));
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less = ($signed({sgn & fu_data_i.operand_a[CVA6Cfg.XLEN-1], fu_data_i.operand_a}) <
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$signed({sgn & fu_data_i.operand_b[CVA6Cfg.XLEN-1], fu_data_i.operand_b}));
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end
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if (CVA6Cfg.RVB) begin : gen_bitmanip
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// Count Population + Count population Word
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popcount #(
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.INPUT_WIDTH(riscv::XLEN)
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.INPUT_WIDTH(CVA6Cfg.XLEN)
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) i_cpop_count (
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.data_i (operand_a_bitmanip),
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.popcount_o(cpop)
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@ -213,7 +213,7 @@ module alu
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// Count Leading/Trailing Zeros
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// 64b
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lzc #(
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.WIDTH(riscv::XLEN),
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.WIDTH(CVA6Cfg.XLEN),
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.MODE (1)
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) i_clz_64b (
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.in_i(operand_a_bitmanip),
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@ -275,39 +275,40 @@ module alu
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if (CVA6Cfg.IS_XLEN64) begin
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unique case (fu_data_i.operation)
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// Add word: Ignore the upper bits and sign extend to 64 bit
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ADDW, SUBW: result_o = {{riscv::XLEN - 32{adder_result[31]}}, adder_result[31:0]};
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ADDW, SUBW: result_o = {{CVA6Cfg.XLEN - 32{adder_result[31]}}, adder_result[31:0]};
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SH1ADDUW, SH2ADDUW, SH3ADDUW: result_o = adder_result;
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// Shifts 32 bit
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SLLW, SRLW, SRAW: result_o = {{riscv::XLEN - 32{shift_result32[31]}}, shift_result32[31:0]};
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SLLW, SRLW, SRAW:
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result_o = {{CVA6Cfg.XLEN - 32{shift_result32[31]}}, shift_result32[31:0]};
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default: ;
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endcase
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end
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unique case (fu_data_i.operation)
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// Standard Operations
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ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[riscv::XLEN:1];
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ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[riscv::XLEN:1];
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XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[riscv::XLEN:1];
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ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[CVA6Cfg.XLEN:1];
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ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[CVA6Cfg.XLEN:1];
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XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[CVA6Cfg.XLEN:1];
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// Adder Operations
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ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD: result_o = adder_result;
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// Shift Operations
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SLL, SRL, SRA: result_o = (CVA6Cfg.IS_XLEN64) ? shift_result : shift_result32;
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// Comparison Operations
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SLTS, SLTU: result_o = {{riscv::XLEN - 1{1'b0}}, less};
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SLTS, SLTU: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, less};
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default: ; // default case to suppress unique warning
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endcase
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if (CVA6Cfg.RVB) begin
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// Index for Bitwise Rotation
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bit_indx = 1 << (fu_data_i.operand_b & (riscv::XLEN - 1));
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bit_indx = 1 << (fu_data_i.operand_b & (CVA6Cfg.XLEN - 1));
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// rolw, roriw, rorw
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rolw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
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rorw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
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rolw = ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (CVA6Cfg.XLEN-32-fu_data_i.operand_b[4:0]));
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rorw = ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (CVA6Cfg.XLEN-32-fu_data_i.operand_b[4:0]));
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if (CVA6Cfg.IS_XLEN64) begin
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unique case (fu_data_i.operation)
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CLZW, CTZW:
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result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount}; // change
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ROLW: result_o = {{riscv::XLEN - 32{rolw[31]}}, rolw};
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RORW, RORIW: result_o = {{riscv::XLEN - 32{rorw[31]}}, rorw};
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result_o = (lz_tz_wempty) ? 32 : {{CVA6Cfg.XLEN - 5{1'b0}}, lz_tz_wcount}; // change
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ROLW: result_o = {{CVA6Cfg.XLEN - 32{rolw[31]}}, rolw};
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RORW, RORIW: result_o = {{CVA6Cfg.XLEN - 32{rorw[31]}}, rorw};
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default: ;
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endcase
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end
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@ -320,36 +321,36 @@ module alu
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// Single bit instructions operations
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BCLR, BCLRI: result_o = fu_data_i.operand_a & ~bit_indx;
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BEXT, BEXTI: result_o = {{riscv::XLEN - 1{1'b0}}, |(fu_data_i.operand_a & bit_indx)};
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BEXT, BEXTI: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, |(fu_data_i.operand_a & bit_indx)};
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BINV, BINVI: result_o = fu_data_i.operand_a ^ bit_indx;
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BSET, BSETI: result_o = fu_data_i.operand_a | bit_indx;
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// Count Leading/Trailing Zeros
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CLZ, CTZ:
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result_o = (lz_tz_empty) ? ({{riscv::XLEN - $clog2(riscv::XLEN) {1'b0}}, lz_tz_count} + 1) :
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{{riscv::XLEN - $clog2(riscv::XLEN) {1'b0}}, lz_tz_count};
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result_o = (lz_tz_empty) ? ({{CVA6Cfg.XLEN - $clog2(CVA6Cfg.XLEN) {1'b0}}, lz_tz_count} + 1)
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: {{CVA6Cfg.XLEN - $clog2(CVA6Cfg.XLEN) {1'b0}}, lz_tz_count};
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// Count population
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CPOP, CPOPW: result_o = {{(riscv::XLEN - ($clog2(riscv::XLEN) + 1)) {1'b0}}, cpop};
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CPOP, CPOPW: result_o = {{(CVA6Cfg.XLEN - ($clog2(CVA6Cfg.XLEN) + 1)) {1'b0}}, cpop};
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// Sign and Zero Extend
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SEXTB: result_o = {{riscv::XLEN - 8{fu_data_i.operand_a[7]}}, fu_data_i.operand_a[7:0]};
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SEXTH: result_o = {{riscv::XLEN - 16{fu_data_i.operand_a[15]}}, fu_data_i.operand_a[15:0]};
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ZEXTH: result_o = {{riscv::XLEN - 16{1'b0}}, fu_data_i.operand_a[15:0]};
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SEXTB: result_o = {{CVA6Cfg.XLEN - 8{fu_data_i.operand_a[7]}}, fu_data_i.operand_a[7:0]};
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SEXTH: result_o = {{CVA6Cfg.XLEN - 16{fu_data_i.operand_a[15]}}, fu_data_i.operand_a[15:0]};
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ZEXTH: result_o = {{CVA6Cfg.XLEN - 16{1'b0}}, fu_data_i.operand_a[15:0]};
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// Bitwise Rotation
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ROL:
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result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (riscv::XLEN-fu_data_i.operand_b[4:0])));
|
||||
result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (CVA6Cfg.XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (CVA6Cfg.XLEN-fu_data_i.operand_b[4:0])));
|
||||
|
||||
ROR, RORI:
|
||||
result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));
|
||||
result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (CVA6Cfg.XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (CVA6Cfg.XLEN-fu_data_i.operand_b[4:0])));
|
||||
|
||||
ORCB: result_o = orcbw_result;
|
||||
REV8: result_o = rev8w_result;
|
||||
|
||||
default:
|
||||
if (fu_data_i.operation == SLLIUW && CVA6Cfg.IS_XLEN64)
|
||||
result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned
|
||||
result_o = {{CVA6Cfg.XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned
|
||||
endcase
|
||||
end
|
||||
if (CVA6Cfg.ZiCondExtEn) begin
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ module amo_buffer #(
|
|||
output logic ready_o, // AMO unit is ready
|
||||
input ariane_pkg::amo_t amo_op_i, // AMO Operation
|
||||
input logic [CVA6Cfg.PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue
|
||||
input logic [riscv::XLEN-1:0] data_i, // data which is placed in the queue
|
||||
input logic [CVA6Cfg.XLEN-1:0] data_i, // data which is placed in the queue
|
||||
input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write)
|
||||
// D$
|
||||
output ariane_pkg::amo_req_t amo_req_o, // request to cache subsytem
|
||||
|
|
@ -40,7 +40,7 @@ module amo_buffer #(
|
|||
typedef struct packed {
|
||||
ariane_pkg::amo_t op;
|
||||
logic [CVA6Cfg.PLEN-1:0] paddr;
|
||||
logic [riscv::XLEN-1:0] data;
|
||||
logic [CVA6Cfg.XLEN-1:0] data;
|
||||
logic [1:0] size;
|
||||
} amo_op_t;
|
||||
|
||||
|
|
@ -51,7 +51,7 @@ module amo_buffer #(
|
|||
assign amo_req_o.amo_op = amo_data_out.op;
|
||||
assign amo_req_o.size = amo_data_out.size;
|
||||
assign amo_req_o.operand_a = {{64 - CVA6Cfg.PLEN{1'b0}}, amo_data_out.paddr};
|
||||
assign amo_req_o.operand_b = {{64 - riscv::XLEN{1'b0}}, amo_data_out.data};
|
||||
assign amo_req_o.operand_b = {{64 - CVA6Cfg.XLEN{1'b0}}, amo_data_out.data};
|
||||
|
||||
assign amo_data_in.op = amo_op_i;
|
||||
assign amo_data_in.data = data_i;
|
||||
|
|
|
|||
|
|
@ -113,7 +113,7 @@ module branch_unit #(
|
|||
branch_exception_o.cause = riscv::INSTR_ADDR_MISALIGNED;
|
||||
branch_exception_o.valid = 1'b0;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
branch_exception_o.tval = {{riscv::XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
branch_exception_o.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
else branch_exception_o.tval = '0;
|
||||
// Only throw instruction address misaligned exception if this is indeed a `taken` conditional branch or
|
||||
// an unconditional jump
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ module axi_adapter #(
|
|||
input ariane_pkg::ad_req_t type_i,
|
||||
input ariane_pkg::amo_t amo_i,
|
||||
output logic gnt_o,
|
||||
input logic [riscv::XLEN-1:0] addr_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] addr_i,
|
||||
input logic we_i,
|
||||
input logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][CVA6Cfg.AxiDataWidth-1:0] wdata_i,
|
||||
input logic [(DATA_WIDTH/CVA6Cfg.AxiDataWidth)-1:0][(CVA6Cfg.AxiDataWidth/8)-1:0] be_i,
|
||||
|
|
|
|||
|
|
@ -148,7 +148,7 @@ module cva6_hpdcache_if_adapter
|
|||
|
||||
assign amo_is_word = (cva6_amo_req_i.size == 2'b10);
|
||||
assign amo_is_word_hi = cva6_amo_req_i.operand_a[2];
|
||||
if (riscv::XLEN == 64) begin : amo_data_64_gen
|
||||
if (CVA6Cfg.XLEN == 64) begin : amo_data_64_gen
|
||||
assign amo_data = amo_is_word ? {2{cva6_amo_req_i.operand_b[0+:32]}} : cva6_amo_req_i.operand_b;
|
||||
assign amo_data_be = amo_is_word_hi ? 8'hf0 : amo_is_word ? 8'h0f : 8'hff;
|
||||
end else begin : amo_data_32_gen
|
||||
|
|
@ -179,7 +179,7 @@ module cva6_hpdcache_if_adapter
|
|||
|
||||
// Response forwarding
|
||||
// {{{
|
||||
if (riscv::XLEN == 64) begin : amo_resp_64_gen
|
||||
if (CVA6Cfg.XLEN == 64) begin : amo_resp_64_gen
|
||||
assign amo_resp_word = amo_is_word_hi
|
||||
? hpdcache_rsp_i.rdata[0][32 +: 32]
|
||||
: hpdcache_rsp_i.rdata[0][0 +: 32];
|
||||
|
|
|
|||
|
|
@ -592,7 +592,7 @@ module miss_handler
|
|||
// Bypass AXI Interface
|
||||
// ----------------------
|
||||
// Cast bypass_adapter_req.addr to axi_adapter port size
|
||||
logic [riscv::XLEN-1:0] bypass_addr;
|
||||
logic [CVA6Cfg.XLEN-1:0] bypass_addr;
|
||||
assign bypass_addr = bypass_adapter_req.addr;
|
||||
|
||||
axi_adapter #(
|
||||
|
|
@ -627,7 +627,7 @@ module miss_handler
|
|||
// Cache Line AXI Refill
|
||||
// ----------------------
|
||||
// Cast req_fsm_miss_addr to axi_adapter port size
|
||||
logic [riscv::XLEN-1:0] miss_addr;
|
||||
logic [CVA6Cfg.XLEN-1:0] miss_addr;
|
||||
assign miss_addr = req_fsm_miss_addr;
|
||||
|
||||
axi_adapter #(
|
||||
|
|
|
|||
|
|
@ -138,7 +138,7 @@ module wt_axi_adapter
|
|||
always_comb begin : p_axi_req
|
||||
// write channel
|
||||
axi_wr_id_in = {{CVA6Cfg.AxiIdWidth-1{1'b0}}, arb_idx};
|
||||
axi_wr_data[0] = {(CVA6Cfg.AxiDataWidth/riscv::XLEN){dcache_data.data}};
|
||||
axi_wr_data[0] = {(CVA6Cfg.AxiDataWidth/CVA6Cfg.XLEN){dcache_data.data}};
|
||||
axi_wr_user[0] = dcache_data.user;
|
||||
// Cast to AXI address width
|
||||
axi_wr_addr = {{CVA6Cfg.AxiAddrWidth-CVA6Cfg.PLEN{1'b0}}, dcache_data.paddr};
|
||||
|
|
@ -269,8 +269,8 @@ module wt_axi_adapter
|
|||
};
|
||||
AMO_AND: begin
|
||||
// in this case we need to invert the data to get a "CLR"
|
||||
axi_wr_data[0] = ~{(CVA6Cfg.AxiDataWidth / riscv::XLEN) {dcache_data.data}};
|
||||
axi_wr_user = ~{(CVA6Cfg.AxiDataWidth / riscv::XLEN) {dcache_data.user}};
|
||||
axi_wr_data[0] = ~{(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN) {dcache_data.data}};
|
||||
axi_wr_user = ~{(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN) {dcache_data.user}};
|
||||
axi_wr_atop = {
|
||||
axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR
|
||||
};
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ module wt_cache_subsystem
|
|||
logic [2:0] size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
|
||||
logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] way; // way to replace
|
||||
logic [CVA6Cfg.PLEN-1:0] paddr; // physical address
|
||||
logic [riscv::XLEN-1:0] data; // word width of processor (no block stores at the moment)
|
||||
logic [CVA6Cfg.XLEN-1:0] data; // word width of processor (no block stores at the moment)
|
||||
logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment)
|
||||
logic nc; // noncacheable
|
||||
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
|
||||
|
|
@ -251,7 +251,7 @@ module wt_cache_subsystem
|
|||
icache_dreq_o.data
|
||||
);
|
||||
|
||||
for (genvar j = 0; j < riscv::XLEN / 8; j++) begin : gen_invalid_write_assertion
|
||||
for (genvar j = 0; j < CVA6Cfg.XLEN / 8; j++) begin : gen_invalid_write_assertion
|
||||
a_invalid_write_data :
|
||||
assert property (
|
||||
@(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> dcache_req_ports_i[NumPorts-1].data_be[j] |-> (|dcache_req_ports_i[NumPorts-1].data_wdata[j*8+:8] !== 1'hX))
|
||||
|
|
|
|||
|
|
@ -59,11 +59,11 @@ module wt_dcache
|
|||
|
||||
localparam type wbuffer_t = struct packed {
|
||||
logic [CVA6Cfg.DCACHE_TAG_WIDTH+(CVA6Cfg.DCACHE_INDEX_WIDTH-CVA6Cfg.XLEN_ALIGN_BYTES)-1:0] wtag;
|
||||
logic [riscv::XLEN-1:0] data;
|
||||
logic [CVA6Cfg.XLEN-1:0] data;
|
||||
logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] user;
|
||||
logic [(riscv::XLEN/8)-1:0] dirty; // byte is dirty
|
||||
logic [(riscv::XLEN/8)-1:0] valid; // byte is valid
|
||||
logic [(riscv::XLEN/8)-1:0] txblock; // byte is part of transaction in-flight
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] dirty; // byte is dirty
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] valid; // byte is valid
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] txblock; // byte is part of transaction in-flight
|
||||
logic checked; // if cache state of this word has been checked
|
||||
logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] hit_oh; // valid way in the cache
|
||||
};
|
||||
|
|
@ -86,8 +86,8 @@ module wt_dcache
|
|||
logic wr_ack;
|
||||
logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_idx;
|
||||
logic [ CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_off;
|
||||
logic [ riscv::XLEN-1:0] wr_data;
|
||||
logic [ (riscv::XLEN/8)-1:0] wr_data_be;
|
||||
logic [ CVA6Cfg.XLEN-1:0] wr_data;
|
||||
logic [ (CVA6Cfg.XLEN/8)-1:0] wr_data_be;
|
||||
logic [ CVA6Cfg.DCACHE_USER_WIDTH-1:0] wr_user;
|
||||
|
||||
// miss unit <-> controllers/wbuffer
|
||||
|
|
@ -95,7 +95,7 @@ module wt_dcache
|
|||
logic [ NumPorts-1:0] miss_ack;
|
||||
logic [ NumPorts-1:0] miss_nc;
|
||||
logic [ NumPorts-1:0] miss_we;
|
||||
logic [ NumPorts-1:0][ riscv::XLEN-1:0] miss_wdata;
|
||||
logic [ NumPorts-1:0][ CVA6Cfg.XLEN-1:0] miss_wdata;
|
||||
logic [ NumPorts-1:0][ CVA6Cfg.DCACHE_USER_WIDTH-1:0] miss_wuser;
|
||||
logic [ NumPorts-1:0][ CVA6Cfg.PLEN-1:0] miss_paddr;
|
||||
logic [ NumPorts-1:0][ 2:0] miss_size;
|
||||
|
|
@ -112,7 +112,7 @@ module wt_dcache
|
|||
logic [ NumPorts-1:0][ CVA6Cfg.DCACHE_TAG_WIDTH-1:0] rd_tag;
|
||||
logic [ NumPorts-1:0][ DCACHE_CL_IDX_WIDTH-1:0] rd_idx;
|
||||
logic [ NumPorts-1:0][CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] rd_off;
|
||||
logic [ riscv::XLEN-1:0] rd_data;
|
||||
logic [ CVA6Cfg.XLEN-1:0] rd_data;
|
||||
logic [ CVA6Cfg.DCACHE_USER_WIDTH-1:0] rd_user;
|
||||
logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_vld_bits;
|
||||
logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh;
|
||||
|
|
@ -238,7 +238,7 @@ module wt_dcache
|
|||
assign req_ports_o[k] = '0;
|
||||
assign miss_req[k] = 1'b0;
|
||||
assign miss_we[k] = 1'b0;
|
||||
assign miss_wdata[k] = {{riscv::XLEN} {1'b0}};
|
||||
assign miss_wdata[k] = {{CVA6Cfg.XLEN} {1'b0}};
|
||||
assign miss_wuser[k] = {{CVA6Cfg.DCACHE_USER_WIDTH} {1'b0}};
|
||||
assign miss_vld_bits_o[k] = {{CVA6Cfg.DCACHE_SET_ASSOC} {1'b0}};
|
||||
assign miss_paddr[k] = {{CVA6Cfg.PLEN} {1'b0}};
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ module wt_dcache_ctrl
|
|||
output logic miss_req_o,
|
||||
input logic miss_ack_i,
|
||||
output logic miss_we_o, // unused (set to 0)
|
||||
output logic [riscv::XLEN-1:0] miss_wdata_o, // unused (set to 0)
|
||||
output logic [CVA6Cfg.XLEN-1:0] miss_wdata_o, // unused (set to 0)
|
||||
output logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] miss_wuser_o, // unused (set to 0)
|
||||
output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, // valid bits at the missed index
|
||||
output logic [CVA6Cfg.PLEN-1:0] miss_paddr_o,
|
||||
|
|
@ -51,7 +51,7 @@ module wt_dcache_ctrl
|
|||
output logic rd_req_o, // read the word at offset off_i[:3] in all ways
|
||||
output logic rd_tag_only_o, // set to zero here
|
||||
input logic rd_ack_i,
|
||||
input logic [riscv::XLEN-1:0] rd_data_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] rd_data_i,
|
||||
input logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] rd_user_i,
|
||||
input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_vld_bits_i,
|
||||
input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh_i
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ module wt_dcache_mem
|
|||
output logic [NumPorts-1:0] rd_ack_o,
|
||||
output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_vld_bits_o,
|
||||
output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh_o,
|
||||
output logic [riscv::XLEN-1:0] rd_data_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] rd_data_o,
|
||||
output logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] rd_user_o,
|
||||
|
||||
// only available on port 0, uses address signals of port 0
|
||||
|
|
@ -68,15 +68,15 @@ module wt_dcache_mem
|
|||
output logic wr_ack_o,
|
||||
input logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx_i,
|
||||
input logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_off_i,
|
||||
input logic [riscv::XLEN-1:0] wr_data_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] wr_data_i,
|
||||
input logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] wr_user_i,
|
||||
input logic [(riscv::XLEN/8)-1:0] wr_data_be_i,
|
||||
input logic [(CVA6Cfg.XLEN/8)-1:0] wr_data_be_i,
|
||||
|
||||
// forwarded wbuffer
|
||||
input wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_data_i
|
||||
);
|
||||
|
||||
localparam DCACHE_NUM_BANKS = CVA6Cfg.DCACHE_LINE_WIDTH / riscv::XLEN;
|
||||
localparam DCACHE_NUM_BANKS = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.XLEN;
|
||||
localparam DCACHE_NUM_BANKS_WIDTH = $clog2(DCACHE_NUM_BANKS);
|
||||
|
||||
// functions
|
||||
|
|
@ -88,24 +88,24 @@ module wt_dcache_mem
|
|||
return out;
|
||||
endfunction
|
||||
|
||||
// number of bits needed to address AXI data. If AxiDataWidth equals XLEN this parameter
|
||||
// number of bits needed to address AXI data. If AxiDataWidth equals CVA6Cfg.XLEN this parameter
|
||||
// is not needed. Therefore, increment it by one to avoid reverse range select during elaboration.
|
||||
localparam AXI_OFFSET_WIDTH = CVA6Cfg.AxiDataWidth == riscv::XLEN ? $clog2(
|
||||
localparam AXI_OFFSET_WIDTH = CVA6Cfg.AxiDataWidth == CVA6Cfg.XLEN ? $clog2(
|
||||
CVA6Cfg.AxiDataWidth / 8
|
||||
) + 1 : $clog2(
|
||||
CVA6Cfg.AxiDataWidth / 8
|
||||
);
|
||||
|
||||
logic [DCACHE_NUM_BANKS-1:0] bank_req;
|
||||
logic [DCACHE_NUM_BANKS-1:0] bank_we;
|
||||
logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][(riscv::XLEN/8)-1:0] bank_be;
|
||||
logic [DCACHE_NUM_BANKS-1:0][ DCACHE_CL_IDX_WIDTH-1:0] bank_idx;
|
||||
logic [DCACHE_NUM_BANKS-1:0] bank_req;
|
||||
logic [DCACHE_NUM_BANKS-1:0] bank_we;
|
||||
logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][(CVA6Cfg.XLEN/8)-1:0] bank_be;
|
||||
logic [DCACHE_NUM_BANKS-1:0][ DCACHE_CL_IDX_WIDTH-1:0] bank_idx;
|
||||
logic [DCACHE_CL_IDX_WIDTH-1:0] bank_idx_d, bank_idx_q;
|
||||
logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] bank_off_d, bank_off_q;
|
||||
|
||||
logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][riscv::XLEN-1:0] bank_wdata; //
|
||||
logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][riscv::XLEN-1:0] bank_rdata; //
|
||||
logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0][riscv::XLEN-1:0] rdata_cl; // selected word from each cacheline
|
||||
logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.XLEN-1:0] bank_wdata; //
|
||||
logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.XLEN-1:0] bank_rdata; //
|
||||
logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.XLEN-1:0] rdata_cl; // selected word from each cacheline
|
||||
logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.DCACHE_USER_WIDTH-1:0] bank_wuser; //
|
||||
logic [DCACHE_NUM_BANKS-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.DCACHE_USER_WIDTH-1:0] bank_ruser; //
|
||||
logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0][CVA6Cfg.DCACHE_USER_WIDTH-1:0] ruser_cl; // selected word from each cacheline
|
||||
|
|
@ -120,8 +120,8 @@ module wt_dcache_mem
|
|||
logic [$clog2(NumPorts)-1:0] vld_sel_d, vld_sel_q;
|
||||
|
||||
logic [DCACHE_WBUF_DEPTH-1:0] wbuffer_hit_oh;
|
||||
logic [ (riscv::XLEN/8)-1:0] wbuffer_be;
|
||||
logic [riscv::XLEN-1:0] wbuffer_rdata, rdata;
|
||||
logic [ (CVA6Cfg.XLEN/8)-1:0] wbuffer_be;
|
||||
logic [CVA6Cfg.XLEN-1:0] wbuffer_rdata, rdata;
|
||||
logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] wbuffer_ruser, ruser;
|
||||
logic [CVA6Cfg.PLEN-1:0] wbuffer_cmp_addr;
|
||||
|
||||
|
|
@ -143,10 +143,10 @@ module wt_dcache_mem
|
|||
// byte enable mapping
|
||||
for (genvar k = 0; k < DCACHE_NUM_BANKS; k++) begin : gen_bank
|
||||
for (genvar j = 0; j < CVA6Cfg.DCACHE_SET_ASSOC; j++) begin : gen_bank_way
|
||||
assign bank_be[k][j] = (wr_cl_we_i[j] & wr_cl_vld_i) ? wr_cl_data_be_i[k*(riscv::XLEN/8) +: (riscv::XLEN/8)] :
|
||||
assign bank_be[k][j] = (wr_cl_we_i[j] & wr_cl_vld_i) ? wr_cl_data_be_i[k*(CVA6Cfg.XLEN/8) +: (CVA6Cfg.XLEN/8)] :
|
||||
(wr_req_i[j] & wr_ack_o) ? wr_data_be_i :
|
||||
'0;
|
||||
assign bank_wdata[k][j] = (wr_cl_we_i[j] & wr_cl_vld_i) ? wr_cl_data_i[k*riscv::XLEN +: riscv::XLEN] :
|
||||
assign bank_wdata[k][j] = (wr_cl_we_i[j] & wr_cl_vld_i) ? wr_cl_data_i[k*CVA6Cfg.XLEN +: CVA6Cfg.XLEN] :
|
||||
wr_data_i;
|
||||
assign bank_wuser[k][j] = (wr_cl_we_i[j] & wr_cl_vld_i) ? wr_cl_user_i[k*CVA6Cfg.DCACHE_USER_WIDTH +: CVA6Cfg.DCACHE_USER_WIDTH] :
|
||||
wr_user_i;
|
||||
|
|
@ -271,8 +271,8 @@ module wt_dcache_mem
|
|||
assign wbuffer_be = (|wbuffer_hit_oh) ? wbuffer_data_i[wbuffer_hit_idx].valid : '0;
|
||||
|
||||
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
|
||||
// In case of an uncached read, return the desired XLEN-bit segment of the most recent AXI read
|
||||
assign wr_cl_off = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == riscv::XLEN) ? '0 :
|
||||
// In case of an uncached read, return the desired CVA6Cfg.XLEN-bit segment of the most recent AXI read
|
||||
assign wr_cl_off = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == CVA6Cfg.XLEN) ? '0 :
|
||||
{{CVA6Cfg.DCACHE_OFFSET_WIDTH-AXI_OFFSET_WIDTH{1'b0}}, wr_cl_off_i[AXI_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES]} :
|
||||
wr_cl_off_i[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:CVA6Cfg.XLEN_ALIGN_BYTES];
|
||||
end else begin : gen_piton_offset
|
||||
|
|
@ -281,7 +281,7 @@ module wt_dcache_mem
|
|||
|
||||
always_comb begin
|
||||
if (wr_cl_vld_i) begin
|
||||
rdata = wr_cl_data_i[wr_cl_off*riscv::XLEN+:riscv::XLEN];
|
||||
rdata = wr_cl_data_i[wr_cl_off*CVA6Cfg.XLEN+:CVA6Cfg.XLEN];
|
||||
ruser = wr_cl_user_i[wr_cl_off*CVA6Cfg.DCACHE_USER_WIDTH+:CVA6Cfg.DCACHE_USER_WIDTH];
|
||||
end else begin
|
||||
rdata = rdata_cl[rd_hit_idx];
|
||||
|
|
@ -290,7 +290,7 @@ module wt_dcache_mem
|
|||
end
|
||||
|
||||
// overlay bytes that hit in the write buffer
|
||||
for (genvar k = 0; k < (riscv::XLEN / 8); k++) begin : gen_rd_data
|
||||
for (genvar k = 0; k < (CVA6Cfg.XLEN / 8); k++) begin : gen_rd_data
|
||||
assign rd_data_o[8*k+:8] = (wbuffer_be[k]) ? wbuffer_rdata[8*k+:8] : rdata[8*k+:8];
|
||||
end
|
||||
for (genvar k = 0; k < CVA6Cfg.DCACHE_USER_WIDTH / 8; k++) begin : gen_rd_user
|
||||
|
|
@ -307,7 +307,7 @@ module wt_dcache_mem
|
|||
// Data RAM
|
||||
sram #(
|
||||
.USER_WIDTH(CVA6Cfg.DCACHE_SET_ASSOC * CVA6Cfg.DCACHE_USER_WIDTH),
|
||||
.DATA_WIDTH(CVA6Cfg.DCACHE_SET_ASSOC * riscv::XLEN),
|
||||
.DATA_WIDTH(CVA6Cfg.DCACHE_SET_ASSOC * CVA6Cfg.XLEN),
|
||||
.USER_EN (CVA6Cfg.DATA_USER_EN),
|
||||
.NUM_WORDS (CVA6Cfg.DCACHE_NUM_WORDS)
|
||||
) i_data_sram (
|
||||
|
|
@ -376,14 +376,14 @@ module wt_dcache_mem
|
|||
|
||||
initial begin
|
||||
axi_xlen :
|
||||
assert (CVA6Cfg.AxiDataWidth >= riscv::XLEN)
|
||||
else $fatal(1, "[l1 dcache] AXI data width needs to be greater or equal XLEN");
|
||||
assert (CVA6Cfg.AxiDataWidth >= CVA6Cfg.XLEN)
|
||||
else $fatal(1, "[l1 dcache] AXI data width needs to be greater or equal CVA6Cfg.XLEN");
|
||||
end
|
||||
|
||||
initial begin
|
||||
cach_line_width_xlen :
|
||||
assert (CVA6Cfg.DCACHE_LINE_WIDTH > riscv::XLEN)
|
||||
else $fatal(1, "[l1 dcache] cache_line_size needs to be greater than XLEN");
|
||||
assert (CVA6Cfg.DCACHE_LINE_WIDTH > CVA6Cfg.XLEN)
|
||||
else $fatal(1, "[l1 dcache] cache_line_size needs to be greater than CVA6Cfg.XLEN");
|
||||
end
|
||||
|
||||
hit_hot1 :
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ module wt_dcache_missunit
|
|||
output logic [NumPorts-1:0] miss_ack_o,
|
||||
input logic [NumPorts-1:0] miss_nc_i,
|
||||
input logic [NumPorts-1:0] miss_we_i,
|
||||
input logic [NumPorts-1:0][riscv::XLEN-1:0] miss_wdata_i,
|
||||
input logic [NumPorts-1:0][CVA6Cfg.XLEN-1:0] miss_wdata_i,
|
||||
input logic [NumPorts-1:0][CVA6Cfg.DCACHE_USER_WIDTH-1:0] miss_wuser_i,
|
||||
input logic [NumPorts-1:0][CVA6Cfg.PLEN-1:0] miss_paddr_i,
|
||||
input logic [NumPorts-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits_i,
|
||||
|
|
@ -141,8 +141,8 @@ module wt_dcache_missunit
|
|||
logic amo_sel, miss_is_write;
|
||||
logic amo_req_d, amo_req_q;
|
||||
logic [63:0] amo_rtrn_mux;
|
||||
logic [riscv::XLEN-1:0] amo_data, amo_data_a, amo_data_b;
|
||||
logic [riscv::XLEN-1:0] amo_user; //DCACHE USER ? CVA6Cfg.DCACHE_USER_WIDTH
|
||||
logic [CVA6Cfg.XLEN-1:0] amo_data, amo_data_a, amo_data_b;
|
||||
logic [CVA6Cfg.XLEN-1:0] amo_user; //DCACHE USER ? CVA6Cfg.DCACHE_USER_WIDTH
|
||||
logic [CVA6Cfg.PLEN-1:0] tmp_paddr;
|
||||
logic [$clog2(NumPorts)-1:0] miss_port_idx;
|
||||
logic [DCACHE_CL_IDX_WIDTH-1:0] cnt_d, cnt_q;
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ module wt_dcache_wbuffer
|
|||
output logic [CVA6Cfg.PLEN-1:0] miss_paddr_o,
|
||||
output logic miss_req_o,
|
||||
output logic miss_we_o, // always 1 here
|
||||
output logic [riscv::XLEN-1:0] miss_wdata_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] miss_wdata_o,
|
||||
output logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] miss_wuser_o,
|
||||
output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, // unused here (set to 0)
|
||||
output logic miss_nc_o, // request to I/O space
|
||||
|
|
@ -89,7 +89,7 @@ module wt_dcache_wbuffer
|
|||
output logic rd_req_o, // read the word at offset off_i[:3] in all ways
|
||||
output logic rd_tag_only_o, // set to 1 here as we do not have to read the data arrays
|
||||
input logic rd_ack_i,
|
||||
input logic [riscv::XLEN-1:0] rd_data_i, // unused
|
||||
input logic [CVA6Cfg.XLEN-1:0] rd_data_i, // unused
|
||||
input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_vld_bits_i, // unused
|
||||
input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh_i,
|
||||
// cacheline writes
|
||||
|
|
@ -100,8 +100,8 @@ module wt_dcache_wbuffer
|
|||
input logic wr_ack_i,
|
||||
output logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx_o,
|
||||
output logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_off_o,
|
||||
output logic [riscv::XLEN-1:0] wr_data_o,
|
||||
output logic [(riscv::XLEN/8)-1:0] wr_data_be_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] wr_data_o,
|
||||
output logic [(CVA6Cfg.XLEN/8)-1:0] wr_data_be_o,
|
||||
output logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] wr_user_o,
|
||||
// to forwarding logic and miss unit
|
||||
output wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_data_o,
|
||||
|
|
@ -109,9 +109,9 @@ module wt_dcache_wbuffer
|
|||
output logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_o
|
||||
);
|
||||
|
||||
function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable8(
|
||||
function automatic logic [(CVA6Cfg.XLEN/8)-1:0] to_byte_enable8(
|
||||
input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
|
||||
logic [(riscv::XLEN/8)-1:0] be;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] be;
|
||||
be = '0;
|
||||
unique case (size)
|
||||
2'b00: be[offset] = '1; // byte
|
||||
|
|
@ -122,7 +122,7 @@ module wt_dcache_wbuffer
|
|||
return be;
|
||||
endfunction : to_byte_enable8
|
||||
|
||||
function automatic logic [(riscv::XLEN/8)-1:0] to_byte_enable4(
|
||||
function automatic logic [(CVA6Cfg.XLEN/8)-1:0] to_byte_enable4(
|
||||
input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size);
|
||||
logic [3:0] be;
|
||||
be = '0;
|
||||
|
|
@ -135,10 +135,10 @@ module wt_dcache_wbuffer
|
|||
endfunction : to_byte_enable4
|
||||
|
||||
// openpiton requires the data to be replicated in case of smaller sizes than dwords
|
||||
function automatic logic [riscv::XLEN-1:0] repData64(
|
||||
input logic [riscv::XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset,
|
||||
function automatic logic [CVA6Cfg.XLEN-1:0] repData64(
|
||||
input logic [CVA6Cfg.XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset,
|
||||
input logic [1:0] size);
|
||||
logic [riscv::XLEN-1:0] out;
|
||||
logic [CVA6Cfg.XLEN-1:0] out;
|
||||
unique case (size)
|
||||
2'b00: for (int k = 0; k < 8; k++) out[k*8+:8] = data[offset*8+:8]; // byte
|
||||
2'b01: for (int k = 0; k < 4; k++) out[k*16+:16] = data[offset*8+:16]; // hword
|
||||
|
|
@ -148,10 +148,10 @@ module wt_dcache_wbuffer
|
|||
return out;
|
||||
endfunction : repData64
|
||||
|
||||
function automatic logic [riscv::XLEN-1:0] repData32(
|
||||
input logic [riscv::XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset,
|
||||
function automatic logic [CVA6Cfg.XLEN-1:0] repData32(
|
||||
input logic [CVA6Cfg.XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset,
|
||||
input logic [1:0] size);
|
||||
logic [riscv::XLEN-1:0] out;
|
||||
logic [CVA6Cfg.XLEN-1:0] out;
|
||||
unique case (size)
|
||||
2'b00: for (int k = 0; k < 4; k++) out[k*8+:8] = data[offset*8+:8]; // byte
|
||||
2'b01: for (int k = 0; k < 2; k++) out[k*16+:16] = data[offset*8+:16]; // hword
|
||||
|
|
@ -162,7 +162,7 @@ module wt_dcache_wbuffer
|
|||
|
||||
typedef struct packed {
|
||||
logic vld;
|
||||
logic [(riscv::XLEN/8)-1:0] be;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] be;
|
||||
logic [$clog2(DCACHE_WBUF_DEPTH)-1:0] ptr;
|
||||
} tx_stat_t;
|
||||
|
||||
|
|
@ -173,14 +173,14 @@ module wt_dcache_wbuffer
|
|||
logic [DCACHE_WBUF_DEPTH-1:0] tocheck;
|
||||
logic [DCACHE_WBUF_DEPTH-1:0] wbuffer_hit_oh, inval_hit;
|
||||
//logic [DCACHE_WBUF_DEPTH-1:0][7:0] bdirty;
|
||||
logic [DCACHE_WBUF_DEPTH-1:0][(riscv::XLEN/8)-1:0] bdirty;
|
||||
logic [DCACHE_WBUF_DEPTH-1:0][(CVA6Cfg.XLEN/8)-1:0] bdirty;
|
||||
|
||||
logic [$clog2(DCACHE_WBUF_DEPTH)-1:0]
|
||||
next_ptr, dirty_ptr, hit_ptr, wr_ptr, check_ptr_d, check_ptr_q, check_ptr_q1, rtrn_ptr;
|
||||
logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tx_id, rtrn_id;
|
||||
|
||||
logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] bdirty_off;
|
||||
logic [(riscv::XLEN/8)-1:0] tx_be;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] tx_be;
|
||||
logic [CVA6Cfg.PLEN-1:0] wr_paddr, rd_paddr, extract_tag;
|
||||
logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] rd_tag_d, rd_tag_q;
|
||||
logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] rd_hit_oh_d, rd_hit_oh_q;
|
||||
|
|
@ -248,7 +248,7 @@ module wt_dcache_wbuffer
|
|||
|
||||
// get byte offset
|
||||
lzc #(
|
||||
.WIDTH(riscv::XLEN / 8)
|
||||
.WIDTH(CVA6Cfg.XLEN / 8)
|
||||
) i_vld_bdirty (
|
||||
.in_i (bdirty[dirty_ptr]),
|
||||
.cnt_o (bdirty_off),
|
||||
|
|
@ -540,7 +540,7 @@ module wt_dcache_wbuffer
|
|||
// once TX write response came back, we can clear the TX block. if it was not dirty, we
|
||||
// can completely evict it - otherwise we have to leave it there for retransmission
|
||||
if (evict) begin
|
||||
for (int k = 0; k < (riscv::XLEN / 8); k++) begin
|
||||
for (int k = 0; k < (CVA6Cfg.XLEN / 8); k++) begin
|
||||
if (tx_stat_q[rtrn_id].be[k]) begin
|
||||
wbuffer_d[rtrn_ptr].txblock[k] = 1'b0;
|
||||
if (!wbuffer_q[rtrn_ptr].dirty[k]) begin
|
||||
|
|
@ -562,7 +562,7 @@ module wt_dcache_wbuffer
|
|||
// mark bytes sent out to the memory system
|
||||
if (miss_req_o && miss_ack_i) begin
|
||||
dirty_rd_en = 1'b1;
|
||||
for (int k = 0; k < (riscv::XLEN / 8); k++) begin
|
||||
for (int k = 0; k < (CVA6Cfg.XLEN / 8); k++) begin
|
||||
if (tx_be[k]) begin
|
||||
wbuffer_d[dirty_ptr].dirty[k] = 1'b0;
|
||||
wbuffer_d[dirty_ptr].txblock[k] = 1'b1;
|
||||
|
|
@ -587,7 +587,7 @@ module wt_dcache_wbuffer
|
|||
};
|
||||
|
||||
// mark bytes as dirty
|
||||
for (int k = 0; k < (riscv::XLEN / 8); k++) begin
|
||||
for (int k = 0; k < (CVA6Cfg.XLEN / 8); k++) begin
|
||||
if (req_port_i.data_be[k]) begin
|
||||
wbuffer_d[wr_ptr].valid[k] = 1'b1;
|
||||
wbuffer_d[wr_ptr].dirty[k] = 1'b1;
|
||||
|
|
@ -677,7 +677,7 @@ module wt_dcache_wbuffer
|
|||
else $fatal(1, "[l1 dcache wbuffer] req_port_i.kill_req should not be asserted");
|
||||
|
||||
for (genvar k = 0; k < DCACHE_WBUF_DEPTH; k++) begin : gen_assert1
|
||||
for (genvar j = 0; j < (riscv::XLEN / 8); j++) begin : gen_assert2
|
||||
for (genvar j = 0; j < (CVA6Cfg.XLEN / 8); j++) begin : gen_assert2
|
||||
byteStates :
|
||||
assert property (
|
||||
@(posedge clk_i) disable iff (!rst_ni) {wbuffer_q[k].valid[j], wbuffer_q[k].dirty[j], wbuffer_q[k].txblock[j]} inside {3'b000, 3'b110, 3'b101, 3'b111} )
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ module commit_stage
|
|||
// Register file write address - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_o,
|
||||
// Register file write data - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_o,
|
||||
output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_o,
|
||||
// Register file write enable - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_o,
|
||||
// Floating point register enable - ISSUE_STAGE
|
||||
|
|
@ -55,9 +55,9 @@ module commit_stage
|
|||
// Decoded CSR operation - CSR_REGFILE
|
||||
output fu_op csr_op_o,
|
||||
// Data to write to CSR - CSR_REGFILE
|
||||
output logic [riscv::XLEN-1:0] csr_wdata_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] csr_wdata_o,
|
||||
// Data to read from CSR - CSR_REGFILE
|
||||
input logic [riscv::XLEN-1:0] csr_rdata_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] csr_rdata_i,
|
||||
// Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE
|
||||
input exception_t csr_exception_i,
|
||||
// Write the fflags CSR - CSR_REGFILE
|
||||
|
|
@ -136,9 +136,9 @@ module commit_stage
|
|||
commit_lsu_o = 1'b0;
|
||||
commit_csr_o = 1'b0;
|
||||
// amos will commit on port 0
|
||||
wdata_o[0] = (CVA6Cfg.RVA && amo_resp_i.ack) ? amo_resp_i.result[riscv::XLEN-1:0] : commit_instr_i[0].result;
|
||||
wdata_o[0] = (CVA6Cfg.RVA && amo_resp_i.ack) ? amo_resp_i.result[CVA6Cfg.XLEN-1:0] : commit_instr_i[0].result;
|
||||
csr_op_o = ADD; // this corresponds to a CSR NOP
|
||||
csr_wdata_o = {riscv::XLEN{1'b0}};
|
||||
csr_wdata_o = {CVA6Cfg.XLEN{1'b0}};
|
||||
fence_i_o = 1'b0;
|
||||
fence_o = 1'b0;
|
||||
sfence_vma_o = 1'b0;
|
||||
|
|
@ -176,7 +176,7 @@ module commit_stage
|
|||
if (CVA6Cfg.FpPresent) begin
|
||||
if (commit_instr_i[0].fu inside {FPU, FPU_VEC}) begin
|
||||
// write the CSR with potential exception flags from retiring floating point instruction
|
||||
csr_wdata_o = {{riscv::XLEN - 5{1'b0}}, commit_instr_i[0].ex.cause[4:0]};
|
||||
csr_wdata_o = {{CVA6Cfg.XLEN - 5{1'b0}}, commit_instr_i[0].ex.cause[4:0]};
|
||||
csr_write_fflags_o = 1'b1;
|
||||
commit_ack_o[0] = 1'b1;
|
||||
end
|
||||
|
|
@ -282,10 +282,10 @@ module commit_stage
|
|||
if (CVA6Cfg.FpPresent && commit_instr_i[1].fu inside {FPU, FPU_VEC}) begin
|
||||
if (csr_write_fflags_o)
|
||||
csr_wdata_o = {
|
||||
{riscv::XLEN - 5{1'b0}},
|
||||
{CVA6Cfg.XLEN - 5{1'b0}},
|
||||
(commit_instr_i[0].ex.cause[4:0] | commit_instr_i[1].ex.cause[4:0])
|
||||
};
|
||||
else csr_wdata_o = {{riscv::XLEN - 5{1'b0}}, commit_instr_i[1].ex.cause[4:0]};
|
||||
else csr_wdata_o = {{CVA6Cfg.XLEN - 5{1'b0}}, commit_instr_i[1].ex.cause[4:0]};
|
||||
|
||||
csr_write_fflags_o = 1'b1;
|
||||
end
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ module csr_buffer
|
|||
// CSR instruction is valid - ISSUE_STAGE
|
||||
input logic csr_valid_i,
|
||||
// CSR buffer result - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] csr_result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] csr_result_o,
|
||||
// commit the pending CSR OP - TO_BE_COMPLETED
|
||||
input logic csr_commit_i,
|
||||
// CSR address to write - COMMIT_STAGE
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ module csr_regfile
|
|||
// Address from which to start booting, mtvec is set to the same address - SUBSYSTEM
|
||||
input logic [CVA6Cfg.VLEN-1:0] boot_addr_i,
|
||||
// Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM
|
||||
input logic [riscv::XLEN-1:0] hart_id_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] hart_id_i,
|
||||
// we are taking an exception
|
||||
// We've got an exception from the commit stage, take it - COMMIT_STAGE
|
||||
input exception_t ex_i,
|
||||
|
|
@ -50,9 +50,9 @@ module csr_regfile
|
|||
// Address of the register to read/write - EX_STAGE
|
||||
input logic [11:0] csr_addr_i,
|
||||
// Write data in - COMMIT_STAGE
|
||||
input logic [riscv::XLEN-1:0] csr_wdata_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] csr_wdata_i,
|
||||
// Read data out - COMMIT_STAGE
|
||||
output logic [riscv::XLEN-1:0] csr_rdata_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] csr_rdata_o,
|
||||
// Mark the FP sate as dirty - COMMIT_STAGE
|
||||
input logic dirty_fp_state_i,
|
||||
// Write fflags register e.g.: we are retiring a floating point instruction - COMMIT_STAGE
|
||||
|
|
@ -129,9 +129,9 @@ module csr_regfile
|
|||
// read/write address to performance counter module - PERF_COUNTERS
|
||||
output logic [11:0] perf_addr_o,
|
||||
// write data to performance counter module - PERF_COUNTERS
|
||||
output logic [riscv::XLEN-1:0] perf_data_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] perf_data_o,
|
||||
// read data from performance counter module - PERF_COUNTERS
|
||||
input logic [riscv::XLEN-1:0] perf_data_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] perf_data_i,
|
||||
// TO_BE_COMPLETED - PERF_COUNTERS
|
||||
output logic perf_we_o,
|
||||
// PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER
|
||||
|
|
@ -155,7 +155,7 @@ module csr_regfile
|
|||
// internal signal to keep track of access exceptions
|
||||
logic read_access_exception, update_access_exception, privilege_violation;
|
||||
logic csr_we, csr_read;
|
||||
logic [riscv::XLEN-1:0] csr_wdata, csr_rdata;
|
||||
logic [CVA6Cfg.XLEN-1:0] csr_wdata, csr_rdata;
|
||||
riscv::priv_lvl_t trap_to_priv_lvl;
|
||||
// register for enabling load store address translation, this is critical, hence the register
|
||||
logic en_ld_st_translation_d, en_ld_st_translation_q;
|
||||
|
|
@ -166,7 +166,7 @@ module csr_regfile
|
|||
// CSR write causes us to mark the FPU state as dirty
|
||||
logic dirty_fp_state_csr;
|
||||
riscv::mstatus_rv_t mstatus_q, mstatus_d;
|
||||
logic [riscv::XLEN-1:0] mstatus_extended;
|
||||
logic [CVA6Cfg.XLEN-1:0] mstatus_extended;
|
||||
satp_t satp_q, satp_d;
|
||||
riscv::dcsr_t dcsr_q, dcsr_d;
|
||||
riscv::csr_t csr_addr;
|
||||
|
|
@ -176,30 +176,30 @@ module csr_regfile
|
|||
logic debug_mode_q, debug_mode_d;
|
||||
logic mtvec_rst_load_q; // used to determine whether we came out of reset
|
||||
|
||||
logic [riscv::XLEN-1:0] dpc_q, dpc_d;
|
||||
logic [riscv::XLEN-1:0] dscratch0_q, dscratch0_d;
|
||||
logic [riscv::XLEN-1:0] dscratch1_q, dscratch1_d;
|
||||
logic [riscv::XLEN-1:0] mtvec_q, mtvec_d;
|
||||
logic [riscv::XLEN-1:0] medeleg_q, medeleg_d;
|
||||
logic [riscv::XLEN-1:0] mideleg_q, mideleg_d;
|
||||
logic [riscv::XLEN-1:0] mip_q, mip_d;
|
||||
logic [riscv::XLEN-1:0] mie_q, mie_d;
|
||||
logic [riscv::XLEN-1:0] mcounteren_q, mcounteren_d;
|
||||
logic [riscv::XLEN-1:0] mscratch_q, mscratch_d;
|
||||
logic [riscv::XLEN-1:0] mepc_q, mepc_d;
|
||||
logic [riscv::XLEN-1:0] mcause_q, mcause_d;
|
||||
logic [riscv::XLEN-1:0] mtval_q, mtval_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] dpc_q, dpc_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] dscratch0_q, dscratch0_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] dscratch1_q, dscratch1_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mtvec_q, mtvec_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] medeleg_q, medeleg_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mideleg_q, mideleg_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mip_q, mip_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mie_q, mie_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mcounteren_q, mcounteren_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mscratch_q, mscratch_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mepc_q, mepc_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mcause_q, mcause_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] mtval_q, mtval_d;
|
||||
logic fiom_d, fiom_q;
|
||||
|
||||
logic [riscv::XLEN-1:0] stvec_q, stvec_d;
|
||||
logic [riscv::XLEN-1:0] scounteren_q, scounteren_d;
|
||||
logic [riscv::XLEN-1:0] sscratch_q, sscratch_d;
|
||||
logic [riscv::XLEN-1:0] sepc_q, sepc_d;
|
||||
logic [riscv::XLEN-1:0] scause_q, scause_d;
|
||||
logic [riscv::XLEN-1:0] stval_q, stval_d;
|
||||
logic [riscv::XLEN-1:0] dcache_q, dcache_d;
|
||||
logic [riscv::XLEN-1:0] icache_q, icache_d;
|
||||
logic [riscv::XLEN-1:0] acc_cons_q, acc_cons_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] stvec_q, stvec_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] scounteren_q, scounteren_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] sscratch_q, sscratch_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] sepc_q, sepc_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] scause_q, scause_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] stval_q, stval_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] dcache_q, dcache_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] icache_q, icache_d;
|
||||
logic [CVA6Cfg.XLEN-1:0] acc_cons_q, acc_cons_d;
|
||||
|
||||
logic wfi_d, wfi_q;
|
||||
|
||||
|
|
@ -211,19 +211,19 @@ module csr_regfile
|
|||
logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q;
|
||||
logic [3:0] index;
|
||||
|
||||
localparam logic [riscv::XLEN-1:0] IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
|
||||
| (riscv::XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
|
||||
| (riscv::XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
|
||||
| (riscv::XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension
|
||||
| (riscv::XLEN'(CVA6Cfg.RVF) << 5) // F - Single precision floating-point extension
|
||||
| (riscv::XLEN'(1) << 8) // I - RV32I/64I/128I base ISA
|
||||
| (riscv::XLEN'(1) << 12) // M - Integer Multiply/Divide extension
|
||||
| (riscv::XLEN'(0) << 13) // N - User level interrupts supported
|
||||
| (riscv::XLEN'(CVA6Cfg.RVS) << 18) // S - Supervisor mode implemented
|
||||
| (riscv::XLEN'(CVA6Cfg.RVU) << 20) // U - User mode implemented
|
||||
| (riscv::XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension
|
||||
| (riscv::XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present
|
||||
| ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN - 2); // MXL
|
||||
localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVF) << 5) // F - Single precision floating-point extension
|
||||
| (CVA6Cfg.XLEN'(1) << 8) // I - RV32I/64I/128I base ISA
|
||||
| (CVA6Cfg.XLEN'(1) << 12) // M - Integer Multiply/Divide extension
|
||||
| (CVA6Cfg.XLEN'(0) << 13) // N - User level interrupts supported
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVS) << 18) // S - Supervisor mode implemented
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVU) << 20) // U - User mode implemented
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present
|
||||
| ((CVA6Cfg.XLEN == 64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL
|
||||
|
||||
assign pmpcfg_o = pmpcfg_q[15:0];
|
||||
assign pmpaddr_o = pmpaddr_q;
|
||||
|
|
@ -238,7 +238,7 @@ module csr_regfile
|
|||
// ----------------
|
||||
// CSR Read logic
|
||||
// ----------------
|
||||
assign mstatus_extended = CVA6Cfg.IS_XLEN64 ? mstatus_q[riscv::XLEN-1:0] :
|
||||
assign mstatus_extended = CVA6Cfg.IS_XLEN64 ? mstatus_q[CVA6Cfg.XLEN-1:0] :
|
||||
{mstatus_q.sd, mstatus_q.wpri3[7:0], mstatus_q[22:0]};
|
||||
|
||||
|
||||
|
|
@ -253,21 +253,21 @@ module csr_regfile
|
|||
unique case (csr_addr.address)
|
||||
riscv::CSR_FFLAGS: begin
|
||||
if (CVA6Cfg.FpPresent) begin
|
||||
csr_rdata = {{riscv::XLEN - 5{1'b0}}, fcsr_q.fflags};
|
||||
csr_rdata = {{CVA6Cfg.XLEN - 5{1'b0}}, fcsr_q.fflags};
|
||||
end else begin
|
||||
read_access_exception = 1'b1;
|
||||
end
|
||||
end
|
||||
riscv::CSR_FRM: begin
|
||||
if (CVA6Cfg.FpPresent) begin
|
||||
csr_rdata = {{riscv::XLEN - 3{1'b0}}, fcsr_q.frm};
|
||||
csr_rdata = {{CVA6Cfg.XLEN - 3{1'b0}}, fcsr_q.frm};
|
||||
end else begin
|
||||
read_access_exception = 1'b1;
|
||||
end
|
||||
end
|
||||
riscv::CSR_FCSR: begin
|
||||
if (CVA6Cfg.FpPresent) begin
|
||||
csr_rdata = {{riscv::XLEN - 8{1'b0}}, fcsr_q.frm, fcsr_q.fflags};
|
||||
csr_rdata = {{CVA6Cfg.XLEN - 8{1'b0}}, fcsr_q.frm, fcsr_q.fflags};
|
||||
end else begin
|
||||
read_access_exception = 1'b1;
|
||||
end
|
||||
|
|
@ -275,14 +275,14 @@ module csr_regfile
|
|||
// non-standard extension
|
||||
riscv::CSR_FTRAN: begin
|
||||
if (CVA6Cfg.FpPresent) begin
|
||||
csr_rdata = {{riscv::XLEN - 7{1'b0}}, fcsr_q.fprec};
|
||||
csr_rdata = {{CVA6Cfg.XLEN - 7{1'b0}}, fcsr_q.fprec};
|
||||
end else begin
|
||||
read_access_exception = 1'b1;
|
||||
end
|
||||
end
|
||||
// debug registers
|
||||
riscv::CSR_DCSR:
|
||||
if (CVA6Cfg.DebugEn) csr_rdata = {{riscv::XLEN - 32{1'b0}}, dcsr_q};
|
||||
if (CVA6Cfg.DebugEn) csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, dcsr_q};
|
||||
else read_access_exception = 1'b1;
|
||||
riscv::CSR_DPC:
|
||||
if (CVA6Cfg.DebugEn) csr_rdata = dpc_q;
|
||||
|
|
@ -300,7 +300,7 @@ module csr_regfile
|
|||
riscv::CSR_TDATA3: read_access_exception = 1'b1; // not implemented
|
||||
// supervisor registers
|
||||
riscv::CSR_SSTATUS: begin
|
||||
if (CVA6Cfg.RVS) csr_rdata = mstatus_extended & SMODE_STATUS_READ_MASK[riscv::XLEN-1:0];
|
||||
if (CVA6Cfg.RVS) csr_rdata = mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0];
|
||||
else read_access_exception = 1'b1;
|
||||
end
|
||||
riscv::CSR_SIE:
|
||||
|
|
@ -342,7 +342,7 @@ module csr_regfile
|
|||
// machine mode registers
|
||||
riscv::CSR_MSTATUS: csr_rdata = mstatus_extended;
|
||||
riscv::CSR_MSTATUSH:
|
||||
if (riscv::XLEN == 32) csr_rdata = '0;
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = '0;
|
||||
else read_access_exception = 1'b1;
|
||||
riscv::CSR_MISA: csr_rdata = IsaCode;
|
||||
riscv::CSR_MEDELEG:
|
||||
|
|
@ -364,34 +364,34 @@ module csr_regfile
|
|||
else read_access_exception = 1'b1;
|
||||
end
|
||||
riscv::CSR_MENVCFGH: begin
|
||||
if (CVA6Cfg.RVU && riscv::XLEN == 32) csr_rdata = '0;
|
||||
if (CVA6Cfg.RVU && CVA6Cfg.XLEN == 32) csr_rdata = '0;
|
||||
else read_access_exception = 1'b1;
|
||||
end
|
||||
riscv::CSR_MVENDORID: csr_rdata = {{riscv::XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID};
|
||||
riscv::CSR_MARCHID: csr_rdata = {{riscv::XLEN - 32{1'b0}}, ARIANE_MARCHID};
|
||||
riscv::CSR_MVENDORID: csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID};
|
||||
riscv::CSR_MARCHID: csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID};
|
||||
riscv::CSR_MIMPID: csr_rdata = '0; // not implemented
|
||||
riscv::CSR_MHARTID: csr_rdata = hart_id_i;
|
||||
riscv::CSR_MCONFIGPTR: csr_rdata = '0; // not implemented
|
||||
riscv::CSR_MCOUNTINHIBIT:
|
||||
if (PERF_COUNTER_EN)
|
||||
csr_rdata = {{(riscv::XLEN - (MHPMCounterNum + 3)) {1'b0}}, mcountinhibit_q};
|
||||
csr_rdata = {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, mcountinhibit_q};
|
||||
else read_access_exception = 1'b1;
|
||||
// Counters and Timers
|
||||
riscv::CSR_MCYCLE: csr_rdata = cycle_q[riscv::XLEN-1:0];
|
||||
riscv::CSR_MCYCLE: csr_rdata = cycle_q[CVA6Cfg.XLEN-1:0];
|
||||
riscv::CSR_MCYCLEH:
|
||||
if (riscv::XLEN == 32) csr_rdata = cycle_q[63:32];
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = cycle_q[63:32];
|
||||
else read_access_exception = 1'b1;
|
||||
riscv::CSR_MINSTRET: csr_rdata = instret_q[riscv::XLEN-1:0];
|
||||
riscv::CSR_MINSTRET: csr_rdata = instret_q[CVA6Cfg.XLEN-1:0];
|
||||
riscv::CSR_MINSTRETH:
|
||||
if (riscv::XLEN == 32) csr_rdata = instret_q[63:32];
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = instret_q[63:32];
|
||||
else read_access_exception = 1'b1;
|
||||
riscv::CSR_CYCLE: csr_rdata = cycle_q[riscv::XLEN-1:0];
|
||||
riscv::CSR_CYCLE: csr_rdata = cycle_q[CVA6Cfg.XLEN-1:0];
|
||||
riscv::CSR_CYCLEH:
|
||||
if (riscv::XLEN == 32) csr_rdata = cycle_q[63:32];
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = cycle_q[63:32];
|
||||
else read_access_exception = 1'b1;
|
||||
riscv::CSR_INSTRET: csr_rdata = instret_q[riscv::XLEN-1:0];
|
||||
riscv::CSR_INSTRET: csr_rdata = instret_q[CVA6Cfg.XLEN-1:0];
|
||||
riscv::CSR_INSTRETH:
|
||||
if (riscv::XLEN == 32) csr_rdata = instret_q[63:32];
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = instret_q[63:32];
|
||||
else read_access_exception = 1'b1;
|
||||
//Event Selector
|
||||
riscv::CSR_MHPM_EVENT_3,
|
||||
|
|
@ -485,7 +485,7 @@ module csr_regfile
|
|||
riscv::CSR_MHPM_COUNTER_29H,
|
||||
riscv::CSR_MHPM_COUNTER_30H,
|
||||
riscv::CSR_MHPM_COUNTER_31H :
|
||||
if (riscv::XLEN == 32) csr_rdata = perf_data_i;
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = perf_data_i;
|
||||
else read_access_exception = 1'b1;
|
||||
|
||||
// Performance counters (User Mode - R/O Shadows)
|
||||
|
|
@ -549,7 +549,7 @@ module csr_regfile
|
|||
riscv::CSR_HPM_COUNTER_29H,
|
||||
riscv::CSR_HPM_COUNTER_30H,
|
||||
riscv::CSR_HPM_COUNTER_31H :
|
||||
if (riscv::XLEN == 32) csr_rdata = perf_data_i;
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = perf_data_i;
|
||||
else read_access_exception = 1'b1;
|
||||
|
||||
// custom (non RISC-V) cache control
|
||||
|
|
@ -564,13 +564,13 @@ module csr_regfile
|
|||
end
|
||||
end
|
||||
// PMPs
|
||||
riscv::CSR_PMPCFG0: csr_rdata = pmpcfg_q[riscv::XLEN/8-1:0];
|
||||
riscv::CSR_PMPCFG0: csr_rdata = pmpcfg_q[CVA6Cfg.XLEN/8-1:0];
|
||||
riscv::CSR_PMPCFG1:
|
||||
if (riscv::XLEN == 32) csr_rdata = pmpcfg_q[7:4];
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = pmpcfg_q[7:4];
|
||||
else read_access_exception = 1'b1;
|
||||
riscv::CSR_PMPCFG2: csr_rdata = pmpcfg_q[8+:riscv::XLEN/8];
|
||||
riscv::CSR_PMPCFG2: csr_rdata = pmpcfg_q[8+:CVA6Cfg.XLEN/8];
|
||||
riscv::CSR_PMPCFG3:
|
||||
if (riscv::XLEN == 32) csr_rdata = pmpcfg_q[15:12];
|
||||
if (CVA6Cfg.XLEN == 32) csr_rdata = pmpcfg_q[15:12];
|
||||
else read_access_exception = 1'b1;
|
||||
// PMPADDR
|
||||
riscv::CSR_PMPADDR0,
|
||||
|
|
@ -605,7 +605,7 @@ module csr_regfile
|
|||
// ---------------------------
|
||||
// CSR Write and update logic
|
||||
// ---------------------------
|
||||
logic [riscv::XLEN-1:0] mask;
|
||||
logic [CVA6Cfg.XLEN-1:0] mask;
|
||||
always_comb begin : csr_update
|
||||
automatic satp_t satp;
|
||||
automatic logic [63:0] instret;
|
||||
|
|
@ -659,7 +659,7 @@ module csr_regfile
|
|||
// boot_addr_i will be assigned a constant
|
||||
// on the top-level.
|
||||
if (mtvec_rst_load_q) begin
|
||||
mtvec_d = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, boot_addr_i} + 'h40;
|
||||
mtvec_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, boot_addr_i} + 'h40;
|
||||
end else begin
|
||||
mtvec_d = mtvec_q;
|
||||
end
|
||||
|
|
@ -767,8 +767,8 @@ module csr_regfile
|
|||
// sstatus is a subset of mstatus - mask it accordingly
|
||||
riscv::CSR_SSTATUS: begin
|
||||
if (CVA6Cfg.RVS) begin
|
||||
mask = ariane_pkg::SMODE_STATUS_WRITE_MASK[riscv::XLEN-1:0];
|
||||
mstatus_d = (mstatus_q & ~{{64-riscv::XLEN{1'b0}}, mask}) | {{64-riscv::XLEN{1'b0}}, (csr_wdata & mask)};
|
||||
mask = ariane_pkg::SMODE_STATUS_WRITE_MASK[CVA6Cfg.XLEN-1:0];
|
||||
mstatus_d = (mstatus_q & ~{{64-CVA6Cfg.XLEN{1'b0}}, mask}) | {{64-CVA6Cfg.XLEN{1'b0}}, (csr_wdata & mask)};
|
||||
// hardwire to zero if floating point extension is not present
|
||||
if (!CVA6Cfg.FpPresent) begin
|
||||
mstatus_d.fs = riscv::Off;
|
||||
|
|
@ -805,16 +805,16 @@ module csr_regfile
|
|||
end
|
||||
|
||||
riscv::CSR_STVEC:
|
||||
if (CVA6Cfg.RVS) stvec_d = {csr_wdata[riscv::XLEN-1:2], 1'b0, csr_wdata[0]};
|
||||
if (CVA6Cfg.RVS) stvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, csr_wdata[0]};
|
||||
else update_access_exception = 1'b1;
|
||||
riscv::CSR_SCOUNTEREN:
|
||||
if (CVA6Cfg.RVS) scounteren_d = {{riscv::XLEN - 32{1'b0}}, csr_wdata[31:0]};
|
||||
if (CVA6Cfg.RVS) scounteren_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]};
|
||||
else update_access_exception = 1'b1;
|
||||
riscv::CSR_SSCRATCH:
|
||||
if (CVA6Cfg.RVS) sscratch_d = csr_wdata;
|
||||
else update_access_exception = 1'b1;
|
||||
riscv::CSR_SEPC:
|
||||
if (CVA6Cfg.RVS) sepc_d = {csr_wdata[riscv::XLEN-1:1], 1'b0};
|
||||
if (CVA6Cfg.RVS) sepc_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0};
|
||||
else update_access_exception = 1'b1;
|
||||
riscv::CSR_SCAUSE:
|
||||
if (CVA6Cfg.RVS) scause_d = csr_wdata;
|
||||
|
|
@ -845,7 +845,7 @@ module csr_regfile
|
|||
end
|
||||
|
||||
riscv::CSR_MSTATUS: begin
|
||||
mstatus_d = {{64 - riscv::XLEN{1'b0}}, csr_wdata};
|
||||
mstatus_d = {{64 - CVA6Cfg.XLEN{1'b0}}, csr_wdata};
|
||||
mstatus_d.xs = riscv::Off;
|
||||
if (!CVA6Cfg.FpPresent) begin
|
||||
mstatus_d.fs = riscv::Off;
|
||||
|
|
@ -861,7 +861,7 @@ module csr_regfile
|
|||
// this register has side-effects on other registers, flush the pipeline
|
||||
flush_o = 1'b1;
|
||||
end
|
||||
riscv::CSR_MSTATUSH: if (riscv::XLEN != 32) update_access_exception = 1'b1;
|
||||
riscv::CSR_MSTATUSH: if (CVA6Cfg.XLEN != 32) update_access_exception = 1'b1;
|
||||
// MISA is WARL (Write Any Value, Reads Legal Value)
|
||||
riscv::CSR_MISA: ;
|
||||
// machine exception delegation register
|
||||
|
|
@ -896,18 +896,18 @@ module csr_regfile
|
|||
end
|
||||
|
||||
riscv::CSR_MTVEC: begin
|
||||
mtvec_d = {csr_wdata[riscv::XLEN-1:2], 1'b0, csr_wdata[0]};
|
||||
mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:2], 1'b0, csr_wdata[0]};
|
||||
// we are in vector mode, this implementation requires the additional
|
||||
// alignment constraint of 64 * 4 bytes
|
||||
if (csr_wdata[0]) mtvec_d = {csr_wdata[riscv::XLEN-1:8], 7'b0, csr_wdata[0]};
|
||||
if (csr_wdata[0]) mtvec_d = {csr_wdata[CVA6Cfg.XLEN-1:8], 7'b0, csr_wdata[0]};
|
||||
end
|
||||
riscv::CSR_MCOUNTEREN: begin
|
||||
if (CVA6Cfg.RVU) mcounteren_d = {{riscv::XLEN - 32{1'b0}}, csr_wdata[31:0]};
|
||||
if (CVA6Cfg.RVU) mcounteren_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]};
|
||||
else update_access_exception = 1'b1;
|
||||
end
|
||||
|
||||
riscv::CSR_MSCRATCH: mscratch_d = csr_wdata;
|
||||
riscv::CSR_MEPC: mepc_d = {csr_wdata[riscv::XLEN-1:1], 1'b0};
|
||||
riscv::CSR_MEPC: mepc_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0};
|
||||
riscv::CSR_MCAUSE: mcause_d = csr_wdata;
|
||||
riscv::CSR_MTVAL: begin
|
||||
if (CVA6Cfg.TvalEn) mtval_d = csr_wdata;
|
||||
|
|
@ -919,19 +919,19 @@ module csr_regfile
|
|||
end
|
||||
riscv::CSR_MENVCFG: if (CVA6Cfg.RVU) fiom_d = csr_wdata[0];
|
||||
riscv::CSR_MENVCFGH: begin
|
||||
if (!CVA6Cfg.RVU || riscv::XLEN != 32) update_access_exception = 1'b1;
|
||||
if (!CVA6Cfg.RVU || CVA6Cfg.XLEN != 32) update_access_exception = 1'b1;
|
||||
end
|
||||
riscv::CSR_MCOUNTINHIBIT:
|
||||
if (PERF_COUNTER_EN) mcountinhibit_d = {csr_wdata[MHPMCounterNum+2:2], 1'b0, csr_wdata[0]};
|
||||
else update_access_exception = 1'b1;
|
||||
// performance counters
|
||||
riscv::CSR_MCYCLE: cycle_d[riscv::XLEN-1:0] = csr_wdata;
|
||||
riscv::CSR_MCYCLE: cycle_d[CVA6Cfg.XLEN-1:0] = csr_wdata;
|
||||
riscv::CSR_MCYCLEH:
|
||||
if (riscv::XLEN == 32) cycle_d[63:32] = csr_wdata;
|
||||
if (CVA6Cfg.XLEN == 32) cycle_d[63:32] = csr_wdata;
|
||||
else update_access_exception = 1'b1;
|
||||
riscv::CSR_MINSTRET: instret_d[riscv::XLEN-1:0] = csr_wdata;
|
||||
riscv::CSR_MINSTRET: instret_d[CVA6Cfg.XLEN-1:0] = csr_wdata;
|
||||
riscv::CSR_MINSTRETH:
|
||||
if (riscv::XLEN == 32) instret_d[63:32] = csr_wdata;
|
||||
if (CVA6Cfg.XLEN == 32) instret_d[63:32] = csr_wdata;
|
||||
else update_access_exception = 1'b1;
|
||||
//Event Selector
|
||||
riscv::CSR_MHPM_EVENT_3,
|
||||
|
|
@ -1030,15 +1030,15 @@ module csr_regfile
|
|||
riscv::CSR_MHPM_COUNTER_30H,
|
||||
riscv::CSR_MHPM_COUNTER_31H : begin
|
||||
perf_we_o = 1'b1;
|
||||
if (riscv::XLEN == 32) perf_data_o = csr_wdata;
|
||||
if (CVA6Cfg.XLEN == 32) perf_data_o = csr_wdata;
|
||||
else update_access_exception = 1'b1;
|
||||
end
|
||||
|
||||
riscv::CSR_DCACHE: dcache_d = {{riscv::XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
|
||||
riscv::CSR_ICACHE: icache_d = {{riscv::XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
|
||||
riscv::CSR_DCACHE: dcache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
|
||||
riscv::CSR_ICACHE: icache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
|
||||
riscv::CSR_ACC_CONS: begin
|
||||
if (CVA6Cfg.EnableAccelerator) begin
|
||||
acc_cons_d = {{riscv::XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
|
||||
acc_cons_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit
|
||||
end else begin
|
||||
update_access_exception = 1'b1;
|
||||
end
|
||||
|
|
@ -1048,10 +1048,10 @@ module csr_regfile
|
|||
// 2. also refuse to update the entry below a locked TOR entry
|
||||
// Note that writes to pmpcfg below a locked TOR entry are valid
|
||||
riscv::CSR_PMPCFG0:
|
||||
for (int i = 0; i < (riscv::XLEN / 8); i++)
|
||||
for (int i = 0; i < (CVA6Cfg.XLEN / 8); i++)
|
||||
if (!pmpcfg_q[i].locked) pmpcfg_d[i] = csr_wdata[i*8+:8];
|
||||
riscv::CSR_PMPCFG1: begin
|
||||
if (riscv::XLEN == 32) begin
|
||||
if (CVA6Cfg.XLEN == 32) begin
|
||||
for (int i = 0; i < 4; i++)
|
||||
if (!pmpcfg_q[i+4].locked) pmpcfg_d[i+4] = csr_wdata[i*8+:8];
|
||||
end else begin
|
||||
|
|
@ -1059,10 +1059,10 @@ module csr_regfile
|
|||
end
|
||||
end
|
||||
riscv::CSR_PMPCFG2:
|
||||
for (int i = 0; i < (riscv::XLEN / 8); i++)
|
||||
for (int i = 0; i < (CVA6Cfg.XLEN / 8); i++)
|
||||
if (!pmpcfg_q[i+8].locked) pmpcfg_d[i+8] = csr_wdata[i*8+:8];
|
||||
riscv::CSR_PMPCFG3: begin
|
||||
if (riscv::XLEN == 32) begin
|
||||
if (CVA6Cfg.XLEN == 32) begin
|
||||
for (int i = 0; i < 4; i++)
|
||||
if (!pmpcfg_q[i+12].locked) pmpcfg_d[i+12] = csr_wdata[i*8+:8];
|
||||
end else begin
|
||||
|
|
@ -1153,12 +1153,12 @@ module csr_regfile
|
|||
flush_o = 1'b0;
|
||||
// figure out where to trap to
|
||||
// a m-mode trap might be delegated if we are taking it in S mode
|
||||
// first figure out if this was an exception or an interrupt e.g.: look at bit (XLEN-1)
|
||||
// the cause register can only be $clog2(riscv::XLEN) bits long (as we only support XLEN exceptions)
|
||||
if (CVA6Cfg.RVS && ((ex_i.cause[riscv::XLEN-1] && mideleg_q[ex_i.cause[$clog2(
|
||||
riscv::XLEN
|
||||
)-1:0]]) || (~ex_i.cause[riscv::XLEN-1] && medeleg_q[ex_i.cause[$clog2(
|
||||
riscv::XLEN
|
||||
// first figure out if this was an exception or an interrupt e.g.: look at bit (CVA6Cfg.XLEN-1)
|
||||
// the cause register can only be $clog2(CVA6Cfg.XLEN) bits long (as we only support CVA6Cfg.XLEN exceptions)
|
||||
if (CVA6Cfg.RVS && ((ex_i.cause[CVA6Cfg.XLEN-1] && mideleg_q[ex_i.cause[$clog2(
|
||||
CVA6Cfg.XLEN
|
||||
)-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && medeleg_q[ex_i.cause[$clog2(
|
||||
CVA6Cfg.XLEN
|
||||
)-1:0]]))) begin
|
||||
// traps never transition from a more-privileged mode to a less privileged mode
|
||||
// so if we are already in M mode, stay there
|
||||
|
|
@ -1176,7 +1176,7 @@ module csr_regfile
|
|||
// set cause
|
||||
scause_d = ex_i.cause;
|
||||
// set epc
|
||||
sepc_d = {{riscv::XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
sepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
// set mtval or stval
|
||||
stval_d = (ariane_pkg::ZERO_TVAL
|
||||
&& (ex_i.cause inside {
|
||||
|
|
@ -1185,7 +1185,7 @@ module csr_regfile
|
|||
riscv::ENV_CALL_UMODE,
|
||||
riscv::ENV_CALL_SMODE,
|
||||
riscv::ENV_CALL_MMODE
|
||||
} || ex_i.cause[riscv::XLEN-1])) ? '0 : ex_i.tval;
|
||||
} || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : ex_i.tval;
|
||||
// trap to machine mode
|
||||
end else begin
|
||||
// update mstatus
|
||||
|
|
@ -1195,7 +1195,7 @@ module csr_regfile
|
|||
mstatus_d.mpp = priv_lvl_q;
|
||||
mcause_d = ex_i.cause;
|
||||
// set epc
|
||||
mepc_d = {{riscv::XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
mepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
// set mtval or stval
|
||||
if (CVA6Cfg.TvalEn) begin
|
||||
mtval_d = (ariane_pkg::ZERO_TVAL
|
||||
|
|
@ -1205,7 +1205,7 @@ module csr_regfile
|
|||
riscv::ENV_CALL_UMODE,
|
||||
riscv::ENV_CALL_SMODE,
|
||||
riscv::ENV_CALL_MMODE
|
||||
} || ex_i.cause[riscv::XLEN-1])) ? '0 : ex_i.tval;
|
||||
} || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : ex_i.tval;
|
||||
end else begin
|
||||
mtval_d = '0;
|
||||
end
|
||||
|
|
@ -1252,7 +1252,7 @@ module csr_regfile
|
|||
default: ;
|
||||
endcase
|
||||
// save PC of next this instruction e.g.: the next one to be executed
|
||||
dpc_d = {{riscv::XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
dpc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
dcsr_d.cause = ariane_pkg::CauseBreakpoint;
|
||||
end
|
||||
|
||||
|
|
@ -1260,7 +1260,7 @@ module csr_regfile
|
|||
if (CVA6Cfg.DebugEn && ex_i.valid && ex_i.cause == riscv::DEBUG_REQUEST) begin
|
||||
dcsr_d.prv = priv_lvl_o;
|
||||
// save the PC
|
||||
dpc_d = {{riscv::XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
dpc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
|
||||
// enter debug mode
|
||||
debug_mode_d = 1'b1;
|
||||
// jump to the base address
|
||||
|
|
@ -1276,19 +1276,19 @@ module csr_regfile
|
|||
if (commit_instr_i[0].fu == CTRL_FLOW) begin
|
||||
// we saved the correct target address during execute
|
||||
dpc_d = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{commit_instr_i[0].bp.predict_address[CVA6Cfg.VLEN-1]}},
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i[0].bp.predict_address[CVA6Cfg.VLEN-1]}},
|
||||
commit_instr_i[0].bp.predict_address
|
||||
};
|
||||
// exception valid
|
||||
end else if (ex_i.valid) begin
|
||||
dpc_d = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, trap_vector_base_o};
|
||||
dpc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, trap_vector_base_o};
|
||||
// return from environment
|
||||
end else if (eret_o) begin
|
||||
dpc_d = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, epc_o};
|
||||
dpc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, epc_o};
|
||||
// consecutive PC
|
||||
end else begin
|
||||
dpc_d = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{commit_instr_i[0].pc[CVA6Cfg.VLEN-1]}},
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i[0].pc[CVA6Cfg.VLEN-1]}},
|
||||
commit_instr_i[0].pc + (commit_instr_i[0].is_compressed ? 'h2 : 'h4)
|
||||
};
|
||||
end
|
||||
|
|
@ -1449,7 +1449,7 @@ module csr_regfile
|
|||
// CSR Exception Control
|
||||
// ----------------------
|
||||
always_comb begin : exception_ctrl
|
||||
csr_exception_o = {{riscv::XLEN{1'b0}}, {riscv::XLEN{1'b0}}, 1'b0};
|
||||
csr_exception_o = {{CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.XLEN{1'b0}}, 1'b0};
|
||||
// ----------------------------------
|
||||
// Illegal Access (decode exception)
|
||||
// ----------------------------------
|
||||
|
|
@ -1503,7 +1503,7 @@ module csr_regfile
|
|||
// we want to spare the costly addition. Furthermore check to which
|
||||
// privilege level we are jumping and whether the vectored mode is
|
||||
// activated for _that_ privilege level.
|
||||
if (ex_i.cause[riscv::XLEN-1] &&
|
||||
if (ex_i.cause[CVA6Cfg.XLEN-1] &&
|
||||
((((CVA6Cfg.RVS || CVA6Cfg.RVU) && trap_to_priv_lvl == riscv::PRIV_LVL_M && mtvec_q[0]) || (!CVA6Cfg.RVS && !CVA6Cfg.RVU && mtvec_q[0]))
|
||||
|| (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S && stvec_q[0]))) begin
|
||||
trap_vector_base_o[7:2] = ex_i.cause[5:0];
|
||||
|
|
@ -1531,12 +1531,12 @@ module csr_regfile
|
|||
|
||||
unique case (csr_addr.address)
|
||||
riscv::CSR_MIP:
|
||||
csr_rdata_o = csr_rdata | ({{riscv::XLEN - 1{1'b0}}, irq_i[1]} << riscv::IRQ_S_EXT);
|
||||
csr_rdata_o = csr_rdata | ({{CVA6Cfg.XLEN - 1{1'b0}}, irq_i[1]} << riscv::IRQ_S_EXT);
|
||||
// in supervisor mode we also need to check whether we delegated this bit
|
||||
riscv::CSR_SIP: begin
|
||||
if (CVA6Cfg.RVS) begin
|
||||
csr_rdata_o = csr_rdata
|
||||
| ({{riscv::XLEN-1{1'b0}}, (irq_i[1] & mideleg_q[riscv::IRQ_S_EXT])} << riscv::IRQ_S_EXT);
|
||||
| ({{CVA6Cfg.XLEN-1{1'b0}}, (irq_i[1] & mideleg_q[riscv::IRQ_S_EXT])} << riscv::IRQ_S_EXT);
|
||||
end
|
||||
end
|
||||
default: ;
|
||||
|
|
@ -1590,37 +1590,37 @@ module csr_regfile
|
|||
dcsr_q.prv <= riscv::PRIV_LVL_M;
|
||||
dcsr_q.xdebugver <= 4'h4;
|
||||
dpc_q <= '0;
|
||||
dscratch0_q <= {riscv::XLEN{1'b0}};
|
||||
dscratch1_q <= {riscv::XLEN{1'b0}};
|
||||
dscratch0_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
dscratch1_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
end
|
||||
// machine mode registers
|
||||
mstatus_q <= 64'b0;
|
||||
// set to boot address + direct mode + 4 byte offset which is the initial trap
|
||||
mtvec_rst_load_q <= 1'b1;
|
||||
mtvec_q <= '0;
|
||||
mip_q <= {riscv::XLEN{1'b0}};
|
||||
mie_q <= {riscv::XLEN{1'b0}};
|
||||
mepc_q <= {riscv::XLEN{1'b0}};
|
||||
mcause_q <= {riscv::XLEN{1'b0}};
|
||||
mcounteren_q <= {riscv::XLEN{1'b0}};
|
||||
mscratch_q <= {riscv::XLEN{1'b0}};
|
||||
mtval_q <= {riscv::XLEN{1'b0}};
|
||||
mip_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
mie_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
mepc_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
mcause_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
mcounteren_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
mscratch_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
mtval_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
fiom_q <= '0;
|
||||
dcache_q <= {{riscv::XLEN - 1{1'b0}}, 1'b1};
|
||||
icache_q <= {{riscv::XLEN - 1{1'b0}}, 1'b1};
|
||||
dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1};
|
||||
icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1};
|
||||
mcountinhibit_q <= '0;
|
||||
acc_cons_q <= {{riscv::XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator};
|
||||
acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator};
|
||||
// supervisor mode registers
|
||||
if (CVA6Cfg.RVS) begin
|
||||
medeleg_q <= {riscv::XLEN{1'b0}};
|
||||
mideleg_q <= {riscv::XLEN{1'b0}};
|
||||
sepc_q <= {riscv::XLEN{1'b0}};
|
||||
scause_q <= {riscv::XLEN{1'b0}};
|
||||
stvec_q <= {riscv::XLEN{1'b0}};
|
||||
scounteren_q <= {riscv::XLEN{1'b0}};
|
||||
sscratch_q <= {riscv::XLEN{1'b0}};
|
||||
stval_q <= {riscv::XLEN{1'b0}};
|
||||
satp_q <= {riscv::XLEN{1'b0}};
|
||||
medeleg_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
mideleg_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
sepc_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
scause_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
stvec_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
scounteren_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
sscratch_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
stval_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
satp_q <= {CVA6Cfg.XLEN{1'b0}};
|
||||
end
|
||||
// timer and counters
|
||||
cycle_q <= 64'b0;
|
||||
|
|
|
|||
82
core/cva6.sv
82
core/cva6.sv
|
|
@ -39,8 +39,8 @@ module cva6
|
|||
},
|
||||
|
||||
localparam type exception_t = struct packed {
|
||||
logic [riscv::XLEN-1:0] cause; // cause of exception
|
||||
logic [riscv::XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it),
|
||||
logic [CVA6Cfg.XLEN-1:0] cause; // cause of exception
|
||||
logic [CVA6Cfg.XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it),
|
||||
// address of LD/ST fault
|
||||
logic valid;
|
||||
},
|
||||
|
|
@ -93,7 +93,7 @@ module cva6
|
|||
logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1
|
||||
logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2
|
||||
logic [REG_ADDR_SIZE-1:0] rd; // register destination address
|
||||
logic [riscv::XLEN-1:0] result; // for unfinished instructions this field also holds the immediate,
|
||||
logic [CVA6Cfg.XLEN-1:0] result; // for unfinished instructions this field also holds the immediate,
|
||||
// for unfinished floating-point that are partly encoded in rs2, this field also holds rs2
|
||||
// for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB)
|
||||
// this field holds the address of the third operand from the floating-point register file
|
||||
|
|
@ -127,19 +127,19 @@ module cva6
|
|||
// All information needed to determine whether we need to associate an interrupt
|
||||
// with the corresponding instruction or not.
|
||||
localparam type irq_ctrl_t = struct packed {
|
||||
logic [riscv::XLEN-1:0] mie;
|
||||
logic [riscv::XLEN-1:0] mip;
|
||||
logic [riscv::XLEN-1:0] mideleg;
|
||||
logic sie;
|
||||
logic global_enable;
|
||||
logic [CVA6Cfg.XLEN-1:0] mie;
|
||||
logic [CVA6Cfg.XLEN-1:0] mip;
|
||||
logic [CVA6Cfg.XLEN-1:0] mideleg;
|
||||
logic sie;
|
||||
logic global_enable;
|
||||
},
|
||||
|
||||
localparam type lsu_ctrl_t = struct packed {
|
||||
logic valid;
|
||||
logic [CVA6Cfg.VLEN-1:0] vaddr;
|
||||
logic overflow;
|
||||
logic [riscv::XLEN-1:0] data;
|
||||
logic [(riscv::XLEN/8)-1:0] be;
|
||||
logic [CVA6Cfg.XLEN-1:0] data;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] be;
|
||||
fu_t fu;
|
||||
fu_op operation;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
|
||||
|
|
@ -148,9 +148,9 @@ module cva6
|
|||
localparam type fu_data_t = struct packed {
|
||||
fu_t fu;
|
||||
fu_op operation;
|
||||
logic [riscv::XLEN-1:0] operand_a;
|
||||
logic [riscv::XLEN-1:0] operand_b;
|
||||
logic [riscv::XLEN-1:0] imm;
|
||||
logic [CVA6Cfg.XLEN-1:0] operand_a;
|
||||
logic [CVA6Cfg.XLEN-1:0] operand_b;
|
||||
logic [CVA6Cfg.XLEN-1:0] imm;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
|
||||
},
|
||||
|
||||
|
|
@ -177,11 +177,11 @@ module cva6
|
|||
localparam type dcache_req_i_t = struct packed {
|
||||
logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] address_index;
|
||||
logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] address_tag;
|
||||
logic [riscv::XLEN-1:0] data_wdata;
|
||||
logic [CVA6Cfg.XLEN-1:0] data_wdata;
|
||||
logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_wuser;
|
||||
logic data_req;
|
||||
logic data_we;
|
||||
logic [(riscv::XLEN/8)-1:0] data_be;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] data_be;
|
||||
logic [1:0] data_size;
|
||||
logic [DCACHE_TID_WIDTH-1:0] data_id;
|
||||
logic kill_req;
|
||||
|
|
@ -192,7 +192,7 @@ module cva6
|
|||
logic data_gnt;
|
||||
logic data_rvalid;
|
||||
logic [DCACHE_TID_WIDTH-1:0] data_rid;
|
||||
logic [riscv::XLEN-1:0] data_rdata;
|
||||
logic [CVA6Cfg.XLEN-1:0] data_rdata;
|
||||
logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_ruser;
|
||||
},
|
||||
|
||||
|
|
@ -274,7 +274,7 @@ module cva6
|
|||
// Reset boot address - SUBSYSTEM
|
||||
input logic [CVA6Cfg.VLEN-1:0] boot_addr_i,
|
||||
// Hard ID reflected as CSR - SUBSYSTEM
|
||||
input logic [riscv::XLEN-1:0] hart_id_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] hart_id_i,
|
||||
// Level sensitive (async) interrupts - SUBSYSTEM
|
||||
input logic [1:0] irq_i,
|
||||
// Inter-processor (async) interrupt - SUBSYSTEM
|
||||
|
|
@ -296,21 +296,21 @@ module cva6
|
|||
);
|
||||
|
||||
localparam type interrupts_t = struct packed {
|
||||
logic [riscv::XLEN-1:0] S_SW;
|
||||
logic [riscv::XLEN-1:0] M_SW;
|
||||
logic [riscv::XLEN-1:0] S_TIMER;
|
||||
logic [riscv::XLEN-1:0] M_TIMER;
|
||||
logic [riscv::XLEN-1:0] S_EXT;
|
||||
logic [riscv::XLEN-1:0] M_EXT;
|
||||
logic [CVA6Cfg.XLEN-1:0] S_SW;
|
||||
logic [CVA6Cfg.XLEN-1:0] M_SW;
|
||||
logic [CVA6Cfg.XLEN-1:0] S_TIMER;
|
||||
logic [CVA6Cfg.XLEN-1:0] M_TIMER;
|
||||
logic [CVA6Cfg.XLEN-1:0] S_EXT;
|
||||
logic [CVA6Cfg.XLEN-1:0] M_EXT;
|
||||
};
|
||||
|
||||
localparam interrupts_t INTERRUPTS = '{
|
||||
S_SW: (1 << (riscv::XLEN - 1)) | riscv::XLEN'(riscv::IRQ_S_SOFT),
|
||||
M_SW: (1 << (riscv::XLEN - 1)) | riscv::XLEN'(riscv::IRQ_M_SOFT),
|
||||
S_TIMER: (1 << (riscv::XLEN - 1)) | riscv::XLEN'(riscv::IRQ_S_TIMER),
|
||||
M_TIMER: (1 << (riscv::XLEN - 1)) | riscv::XLEN'(riscv::IRQ_M_TIMER),
|
||||
S_EXT: (1 << (riscv::XLEN - 1)) | riscv::XLEN'(riscv::IRQ_S_EXT),
|
||||
M_EXT: (1 << (riscv::XLEN - 1)) | riscv::XLEN'(riscv::IRQ_M_EXT)
|
||||
S_SW: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_SOFT),
|
||||
M_SW: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_SOFT),
|
||||
S_TIMER: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_TIMER),
|
||||
M_TIMER: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_TIMER),
|
||||
S_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_EXT),
|
||||
M_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_EXT)
|
||||
};
|
||||
|
||||
// ------------------------------------------
|
||||
|
|
@ -363,7 +363,7 @@ module cva6
|
|||
logic flu_ready_ex_id;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] flu_trans_id_ex_id;
|
||||
logic flu_valid_ex_id;
|
||||
logic [riscv::XLEN-1:0] flu_result_ex_id;
|
||||
logic [CVA6Cfg.XLEN-1:0] flu_result_ex_id;
|
||||
exception_t flu_exception_ex_id;
|
||||
// ALU
|
||||
logic alu_valid_id_ex;
|
||||
|
|
@ -377,11 +377,11 @@ module cva6
|
|||
logic lsu_ready_ex_id;
|
||||
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_ex_id;
|
||||
logic [riscv::XLEN-1:0] load_result_ex_id;
|
||||
logic [CVA6Cfg.XLEN-1:0] load_result_ex_id;
|
||||
logic load_valid_ex_id;
|
||||
exception_t load_exception_ex_id;
|
||||
|
||||
logic [riscv::XLEN-1:0] store_result_ex_id;
|
||||
logic [CVA6Cfg.XLEN-1:0] store_result_ex_id;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] store_trans_id_ex_id;
|
||||
logic store_valid_ex_id;
|
||||
exception_t store_exception_ex_id;
|
||||
|
|
@ -393,7 +393,7 @@ module cva6
|
|||
logic [1:0] fpu_fmt_id_ex;
|
||||
logic [2:0] fpu_rm_id_ex;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id_ex_id;
|
||||
logic [riscv::XLEN-1:0] fpu_result_ex_id;
|
||||
logic [CVA6Cfg.XLEN-1:0] fpu_result_ex_id;
|
||||
logic fpu_valid_ex_id;
|
||||
exception_t fpu_exception_ex_id;
|
||||
// Accelerator
|
||||
|
|
@ -401,7 +401,7 @@ module cva6
|
|||
scoreboard_entry_t issue_instr_id_acc;
|
||||
logic issue_instr_hs_id_acc;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] acc_trans_id_ex_id;
|
||||
logic [riscv::XLEN-1:0] acc_result_ex_id;
|
||||
logic [CVA6Cfg.XLEN-1:0] acc_result_ex_id;
|
||||
logic acc_valid_ex_id;
|
||||
exception_t acc_exception_ex_id;
|
||||
logic halt_acc_ctrl;
|
||||
|
|
@ -412,7 +412,7 @@ module cva6
|
|||
logic csr_valid_id_ex;
|
||||
// CVXIF
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_ex_id;
|
||||
logic [riscv::XLEN-1:0] x_result_ex_id;
|
||||
logic [CVA6Cfg.XLEN-1:0] x_result_ex_id;
|
||||
logic x_valid_ex_id;
|
||||
exception_t x_exception_ex_id;
|
||||
logic x_we_ex_id;
|
||||
|
|
@ -449,7 +449,7 @@ module cva6
|
|||
// COMMIT <-> ID
|
||||
// --------------
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_commit_id;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_commit_id;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_commit_id;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_commit_id;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_commit_id;
|
||||
// --------------
|
||||
|
|
@ -469,8 +469,8 @@ module cva6
|
|||
logic [CVA6Cfg.ASID_WIDTH-1:0] asid_csr_ex;
|
||||
logic [11:0] csr_addr_ex_csr;
|
||||
fu_op csr_op_commit_csr;
|
||||
logic [riscv::XLEN-1:0] csr_wdata_commit_csr;
|
||||
logic [riscv::XLEN-1:0] csr_rdata_csr_commit;
|
||||
logic [CVA6Cfg.XLEN-1:0] csr_wdata_commit_csr;
|
||||
logic [CVA6Cfg.XLEN-1:0] csr_rdata_csr_commit;
|
||||
exception_t csr_exception_csr_commit;
|
||||
logic tvm_csr_id;
|
||||
logic tw_csr_id;
|
||||
|
|
@ -489,7 +489,7 @@ module cva6
|
|||
// Performance Counters <-> *
|
||||
// ----------------------------
|
||||
logic [11:0] addr_csr_perf;
|
||||
logic [riscv::XLEN-1:0] data_csr_perf, data_perf_csr;
|
||||
logic [CVA6Cfg.XLEN-1:0] data_csr_perf, data_perf_csr;
|
||||
logic we_csr_perf;
|
||||
|
||||
logic icache_flush_ctrl_cache;
|
||||
|
|
@ -625,7 +625,7 @@ module cva6
|
|||
);
|
||||
|
||||
logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_ex_id;
|
||||
logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_ex_id;
|
||||
logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_ex_id;
|
||||
exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_ex_id; // exception from execute, ex_stage to id_stage
|
||||
logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_ex_id;
|
||||
|
||||
|
|
@ -948,7 +948,7 @@ module cva6
|
|||
.commit_instr_i (commit_instr_id_commit),
|
||||
.commit_ack_i (commit_macro_ack),
|
||||
.boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]),
|
||||
.hart_id_i (hart_id_i[riscv::XLEN-1:0]),
|
||||
.hart_id_i (hart_id_i[CVA6Cfg.XLEN-1:0]),
|
||||
.ex_i (ex_commit),
|
||||
.csr_op_i (csr_op_commit_csr),
|
||||
.csr_write_fflags_i (csr_write_fflags_commit_cs),
|
||||
|
|
|
|||
|
|
@ -39,21 +39,21 @@ module cva6_rvfi
|
|||
localparam bit RVD = (CVA6Cfg.IS_XLEN64 ? 1 : 0) & CVA6Cfg.FpuEn;
|
||||
localparam bit FpPresent = RVF | RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8;
|
||||
|
||||
localparam logic [riscv::XLEN-1:0] IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
|
||||
| (riscv::XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
|
||||
| (riscv::XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
|
||||
| (riscv::XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension
|
||||
| (riscv::XLEN'(CVA6Cfg.RVF) << 5) // F - Single precision floating-point extension
|
||||
| (riscv::XLEN'(1) << 8) // I - RV32I/64I/128I base ISA
|
||||
| (riscv::XLEN'(1) << 12) // M - Integer Multiply/Divide extension
|
||||
| (riscv::XLEN'(0) << 13) // N - User level interrupts supported
|
||||
| (riscv::XLEN'(CVA6Cfg.RVS) << 18) // S - Supervisor mode implemented
|
||||
| (riscv::XLEN'(CVA6Cfg.RVU) << 20) // U - User mode implemented
|
||||
| (riscv::XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension
|
||||
| (riscv::XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present
|
||||
| ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN - 2); // MXL
|
||||
localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVD) << 3) // D - Double precision floating-point extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVF) << 5) // F - Single precision floating-point extension
|
||||
| (CVA6Cfg.XLEN'(1) << 8) // I - RV32I/64I/128I base ISA
|
||||
| (CVA6Cfg.XLEN'(1) << 12) // M - Integer Multiply/Divide extension
|
||||
| (CVA6Cfg.XLEN'(0) << 13) // N - User level interrupts supported
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVS) << 18) // S - Supervisor mode implemented
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVU) << 20) // U - User mode implemented
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension
|
||||
| (CVA6Cfg.XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present
|
||||
| ((CVA6Cfg.XLEN == 64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL
|
||||
|
||||
localparam logic [riscv::XLEN-1:0] hart_id_i = '0;
|
||||
localparam logic [CVA6Cfg.XLEN-1:0] hart_id_i = '0;
|
||||
|
||||
localparam logic [63:0] SMODE_STATUS_READ_MASK = ariane_pkg::smode_status_read_mask(CVA6Cfg);
|
||||
|
||||
|
|
@ -70,36 +70,36 @@ module cva6_rvfi
|
|||
logic decoded_instr_valid;
|
||||
logic decoded_instr_ack;
|
||||
|
||||
logic [riscv::XLEN-1:0] rs1_forwarding;
|
||||
logic [riscv::XLEN-1:0] rs2_forwarding;
|
||||
logic [CVA6Cfg.XLEN-1:0] rs1_forwarding;
|
||||
logic [CVA6Cfg.XLEN-1:0] rs2_forwarding;
|
||||
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] commit_instr_pc;
|
||||
fu_op [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_instr_op;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs1;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs2;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rd;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] commit_instr_result;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] commit_instr_result;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] commit_instr_valid;
|
||||
|
||||
logic [riscv::XLEN-1:0] ex_commit_cause;
|
||||
logic [CVA6Cfg.XLEN-1:0] ex_commit_cause;
|
||||
logic ex_commit_valid;
|
||||
|
||||
riscv::priv_lvl_t priv_lvl;
|
||||
|
||||
logic [CVA6Cfg.VLEN-1:0] lsu_ctrl_vaddr;
|
||||
fu_t lsu_ctrl_fu;
|
||||
logic [(riscv::XLEN/8)-1:0] lsu_ctrl_be;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] lsu_ctrl_be;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] lsu_ctrl_trans_id;
|
||||
|
||||
logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata;
|
||||
logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][CVA6Cfg.XLEN-1:0] wbdata;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack;
|
||||
logic [CVA6Cfg.PLEN-1:0] mem_paddr;
|
||||
logic debug_mode;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata;
|
||||
|
||||
logic [CVA6Cfg.VLEN-1:0] lsu_addr;
|
||||
logic [(riscv::XLEN/8)-1:0] lsu_rmask;
|
||||
logic [(riscv::XLEN/8)-1:0] lsu_wmask;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] lsu_rmask;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] lsu_wmask;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] lsu_addr_trans_id;
|
||||
|
||||
riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d;
|
||||
|
|
@ -196,12 +196,12 @@ module cva6_rvfi
|
|||
|
||||
// this is the FIFO struct of the issue queue
|
||||
typedef struct packed {
|
||||
logic [riscv::XLEN-1:0] rs1_rdata;
|
||||
logic [riscv::XLEN-1:0] rs2_rdata;
|
||||
logic [CVA6Cfg.XLEN-1:0] rs1_rdata;
|
||||
logic [CVA6Cfg.XLEN-1:0] rs2_rdata;
|
||||
logic [CVA6Cfg.VLEN-1:0] lsu_addr;
|
||||
logic [(riscv::XLEN/8)-1:0] lsu_rmask;
|
||||
logic [(riscv::XLEN/8)-1:0] lsu_wmask;
|
||||
logic [riscv::XLEN-1:0] lsu_wdata;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] lsu_rmask;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] lsu_wmask;
|
||||
logic [CVA6Cfg.XLEN-1:0] lsu_wdata;
|
||||
logic [31:0] instr;
|
||||
} sb_mem_t;
|
||||
sb_mem_t [CVA6Cfg.NR_SB_ENTRIES-1:0] mem_q, mem_n;
|
||||
|
|
@ -256,7 +256,7 @@ module cva6_rvfi
|
|||
rvfi_instr_o[i].trap = exception;
|
||||
rvfi_instr_o[i].cause = ex_commit_cause;
|
||||
rvfi_instr_o[i].mode = (CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl;
|
||||
rvfi_instr_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
|
||||
rvfi_instr_o[i].ixl = CVA6Cfg.XLEN == 64 ? 2 : 1;
|
||||
rvfi_instr_o[i].rs1_addr = commit_instr_rs1[i][4:0];
|
||||
rvfi_instr_o[i].rs2_addr = commit_instr_rs2[i][4:0];
|
||||
rvfi_instr_o[i].rd_addr = commit_instr_rd[i][4:0];
|
||||
|
|
@ -314,8 +314,8 @@ module cva6_rvfi
|
|||
: '0;
|
||||
rvfi_csr_o.sstatus = CVA6Cfg.RVS ?
|
||||
'{
|
||||
rdata: csr.mstatus_extended & SMODE_STATUS_READ_MASK[riscv::XLEN-1:0],
|
||||
wdata: csr.mstatus_extended & SMODE_STATUS_READ_MASK[riscv::XLEN-1:0],
|
||||
rdata: csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0],
|
||||
wdata: csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0],
|
||||
rmask: '1,
|
||||
wmask: '1
|
||||
}
|
||||
|
|
@ -353,7 +353,7 @@ module cva6_rvfi
|
|||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.mstatush = riscv::XLEN == 32 ?
|
||||
rvfi_csr_o.mstatush = CVA6Cfg.XLEN == 32 ?
|
||||
'{rdata: '0, wdata: '0, rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
rvfi_csr_o.misa = '{rdata: IsaCode, wdata: IsaCode, rmask: '1, wmask: '1};
|
||||
|
|
@ -382,7 +382,7 @@ module cva6_rvfi
|
|||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.menvcfgh = riscv::XLEN == 32 ?
|
||||
rvfi_csr_o.menvcfgh = CVA6Cfg.XLEN == 32 ?
|
||||
'{rdata: '0, wdata: '0, rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
rvfi_csr_o.mvendorid = '{
|
||||
|
|
@ -400,39 +400,39 @@ module cva6_rvfi
|
|||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.mcycle = '{
|
||||
rdata: csr.cycle_q[riscv::XLEN-1:0],
|
||||
wdata: csr.cycle_q[riscv::XLEN-1:0],
|
||||
rdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
|
||||
wdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
|
||||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.mcycleh = riscv::XLEN == 32 ?
|
||||
rvfi_csr_o.mcycleh = CVA6Cfg.XLEN == 32 ?
|
||||
'{rdata: csr.cycle_q[63:32], wdata: csr.cycle_q[63:32], rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
rvfi_csr_o.minstret = '{
|
||||
rdata: csr.instret_q[riscv::XLEN-1:0],
|
||||
wdata: csr.instret_q[riscv::XLEN-1:0],
|
||||
rdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
|
||||
wdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
|
||||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.minstreth = riscv::XLEN == 32 ?
|
||||
rvfi_csr_o.minstreth = CVA6Cfg.XLEN == 32 ?
|
||||
'{rdata: csr.instret_q[63:32], wdata: csr.instret_q[63:32], rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
rvfi_csr_o.cycle = '{
|
||||
rdata: csr.cycle_q[riscv::XLEN-1:0],
|
||||
wdata: csr.cycle_q[riscv::XLEN-1:0],
|
||||
rdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
|
||||
wdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
|
||||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.cycleh = riscv::XLEN == 32 ?
|
||||
rvfi_csr_o.cycleh = CVA6Cfg.XLEN == 32 ?
|
||||
'{rdata: csr.cycle_q[63:32], wdata: csr.cycle_q[63:32], rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
rvfi_csr_o.instret = '{
|
||||
rdata: csr.instret_q[riscv::XLEN-1:0],
|
||||
wdata: csr.instret_q[riscv::XLEN-1:0],
|
||||
rdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
|
||||
wdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
|
||||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.instreth = riscv::XLEN == 32 ?
|
||||
rvfi_csr_o.instreth = CVA6Cfg.XLEN == 32 ?
|
||||
'{rdata: csr.instret_q[63:32], wdata: csr.instret_q[63:32], rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
rvfi_csr_o.dcache = '{rdata: csr.dcache_q, wdata: csr.dcache_q, rmask: '1, wmask: '1};
|
||||
|
|
@ -441,21 +441,21 @@ module cva6_rvfi
|
|||
'{rdata: csr.acc_cons_q, wdata: csr.acc_cons_q, rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
rvfi_csr_o.pmpcfg0 = '{
|
||||
rdata: csr.pmpcfg_q[riscv::XLEN/8-1:0],
|
||||
wdata: csr.pmpcfg_q[riscv::XLEN/8-1:0],
|
||||
rdata: csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0],
|
||||
wdata: csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0],
|
||||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.pmpcfg1 = riscv::XLEN == 32 ?
|
||||
rvfi_csr_o.pmpcfg1 = CVA6Cfg.XLEN == 32 ?
|
||||
'{rdata: csr.pmpcfg_q[7:4], wdata: csr.pmpcfg_q[7:4], rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
rvfi_csr_o.pmpcfg2 = '{
|
||||
rdata: csr.pmpcfg_q[8+:riscv::XLEN/8],
|
||||
wdata: csr.pmpcfg_q[8+:riscv::XLEN/8],
|
||||
rdata: csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8],
|
||||
wdata: csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8],
|
||||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
rvfi_csr_o.pmpcfg3 = riscv::XLEN == 32 ?
|
||||
rvfi_csr_o.pmpcfg3 = CVA6Cfg.XLEN == 32 ?
|
||||
'{rdata: csr.pmpcfg_q[15:12], wdata: csr.pmpcfg_q[15:12], rmask: '1, wmask: '1}
|
||||
: '0;
|
||||
|
||||
|
|
|
|||
|
|
@ -35,19 +35,19 @@ module cva6_rvfi_probes
|
|||
input logic decoded_instr_valid_i,
|
||||
input logic decoded_instr_ack_i,
|
||||
|
||||
input logic [riscv::XLEN-1:0] rs1_forwarding_i,
|
||||
input logic [riscv::XLEN-1:0] rs2_forwarding_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] rs1_forwarding_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] rs2_forwarding_i,
|
||||
|
||||
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
|
||||
input exception_t ex_commit_i,
|
||||
input riscv::priv_lvl_t priv_lvl_i,
|
||||
|
||||
input lsu_ctrl_t lsu_ctrl_i,
|
||||
input logic [ CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i,
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
|
||||
input logic [ CVA6Cfg.PLEN-1:0] mem_paddr_i,
|
||||
input logic debug_mode_i,
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i,
|
||||
input lsu_ctrl_t lsu_ctrl_i,
|
||||
input logic [ CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_i,
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
|
||||
input logic [ CVA6Cfg.PLEN-1:0] mem_paddr_i,
|
||||
input logic debug_mode_i,
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i,
|
||||
|
||||
input rvfi_probes_csr_t csr_i,
|
||||
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ module cvxif_fu
|
|||
// CVXIF exception - ISSUE_STAGE
|
||||
output exception_t x_exception_o,
|
||||
// CVXIF FU result - ISSUE_STAGE
|
||||
output logic [ riscv::XLEN-1:0] x_result_o,
|
||||
output logic [ CVA6Cfg.XLEN-1:0] x_result_o,
|
||||
// CVXIF result valid - ISSUE_STAGE
|
||||
output logic x_valid_o,
|
||||
// CVXIF write enable - ISSUE_STAGE
|
||||
|
|
@ -92,7 +92,7 @@ module cvxif_fu
|
|||
x_valid_o = cvxif_resp_i.x_result_valid; //Read result only when CVXIF is enabled
|
||||
x_trans_id_o = x_valid_o ? cvxif_resp_i.x_result.id : '0;
|
||||
x_result_o = x_valid_o ? cvxif_resp_i.x_result.data : '0;
|
||||
x_exception_o.cause = x_valid_o ? {{(riscv::XLEN-6){1'b0}}, cvxif_resp_i.x_result.exccode} : '0;
|
||||
x_exception_o.cause = x_valid_o ? {{(CVA6Cfg.XLEN-6){1'b0}}, cvxif_resp_i.x_result.exccode} : '0;
|
||||
x_exception_o.valid = x_valid_o ? cvxif_resp_i.x_result.exc : '0;
|
||||
x_exception_o.tval = '0;
|
||||
x_we_o = x_valid_o ? cvxif_resp_i.x_result.we : '0;
|
||||
|
|
|
|||
|
|
@ -104,12 +104,12 @@ module decoder
|
|||
RS3
|
||||
} imm_select;
|
||||
|
||||
logic [riscv::XLEN-1:0] imm_i_type;
|
||||
logic [riscv::XLEN-1:0] imm_s_type;
|
||||
logic [riscv::XLEN-1:0] imm_sb_type;
|
||||
logic [riscv::XLEN-1:0] imm_u_type;
|
||||
logic [riscv::XLEN-1:0] imm_uj_type;
|
||||
logic [riscv::XLEN-1:0] imm_bi_type;
|
||||
logic [CVA6Cfg.XLEN-1:0] imm_i_type;
|
||||
logic [CVA6Cfg.XLEN-1:0] imm_s_type;
|
||||
logic [CVA6Cfg.XLEN-1:0] imm_sb_type;
|
||||
logic [CVA6Cfg.XLEN-1:0] imm_u_type;
|
||||
logic [CVA6Cfg.XLEN-1:0] imm_uj_type;
|
||||
logic [CVA6Cfg.XLEN-1:0] imm_bi_type;
|
||||
|
||||
// ---------------------------------------
|
||||
// Accelerator instructions' first-pass decoder
|
||||
|
|
@ -741,7 +741,7 @@ module decoder
|
|||
3'b001: begin
|
||||
instruction_o.op = ariane_pkg::SLL; // Shift Left Logical by Immediate
|
||||
if (instr.instr[31:26] != 6'b0) illegal_instr_non_bm = 1'b1;
|
||||
if (instr.instr[25] != 1'b0 && riscv::XLEN == 32) illegal_instr_non_bm = 1'b1;
|
||||
if (instr.instr[25] != 1'b0 && CVA6Cfg.XLEN == 32) illegal_instr_non_bm = 1'b1;
|
||||
end
|
||||
|
||||
3'b101: begin
|
||||
|
|
@ -750,7 +750,7 @@ module decoder
|
|||
else if (instr.instr[31:26] == 6'b010_000)
|
||||
instruction_o.op = ariane_pkg::SRA; // Shift Right Arithmetically by Immediate
|
||||
else illegal_instr_non_bm = 1'b1;
|
||||
if (instr.instr[25] != 1'b0 && riscv::XLEN == 32) illegal_instr_non_bm = 1'b1;
|
||||
if (instr.instr[25] != 1'b0 && CVA6Cfg.XLEN == 32) illegal_instr_non_bm = 1'b1;
|
||||
end
|
||||
endcase
|
||||
if (CVA6Cfg.RVB) begin
|
||||
|
|
@ -848,7 +848,7 @@ module decoder
|
|||
3'b001: instruction_o.op = ariane_pkg::SH;
|
||||
3'b010: instruction_o.op = ariane_pkg::SW;
|
||||
3'b011:
|
||||
if (riscv::XLEN == 64) instruction_o.op = ariane_pkg::SD;
|
||||
if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::SD;
|
||||
else illegal_instr = 1'b1;
|
||||
default: illegal_instr = 1'b1;
|
||||
endcase
|
||||
|
|
@ -867,10 +867,10 @@ module decoder
|
|||
3'b100: instruction_o.op = ariane_pkg::LBU;
|
||||
3'b101: instruction_o.op = ariane_pkg::LHU;
|
||||
3'b110:
|
||||
if (riscv::XLEN == 64) instruction_o.op = ariane_pkg::LWU;
|
||||
if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::LWU;
|
||||
else illegal_instr = 1'b1;
|
||||
3'b011:
|
||||
if (riscv::XLEN == 64) instruction_o.op = ariane_pkg::LD;
|
||||
if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::LD;
|
||||
else illegal_instr = 1'b1;
|
||||
default: illegal_instr = 1'b1;
|
||||
endcase
|
||||
|
|
@ -1278,10 +1278,12 @@ module decoder
|
|||
// Sign extend immediate
|
||||
// --------------------------------
|
||||
always_comb begin : sign_extend
|
||||
imm_i_type = {{riscv::XLEN - 12{instruction_i[31]}}, instruction_i[31:20]};
|
||||
imm_s_type = {{riscv::XLEN - 12{instruction_i[31]}}, instruction_i[31:25], instruction_i[11:7]};
|
||||
imm_i_type = {{CVA6Cfg.XLEN - 12{instruction_i[31]}}, instruction_i[31:20]};
|
||||
imm_s_type = {
|
||||
{CVA6Cfg.XLEN - 12{instruction_i[31]}}, instruction_i[31:25], instruction_i[11:7]
|
||||
};
|
||||
imm_sb_type = {
|
||||
{riscv::XLEN - 13{instruction_i[31]}},
|
||||
{CVA6Cfg.XLEN - 13{instruction_i[31]}},
|
||||
instruction_i[31],
|
||||
instruction_i[7],
|
||||
instruction_i[30:25],
|
||||
|
|
@ -1289,16 +1291,16 @@ module decoder
|
|||
1'b0
|
||||
};
|
||||
imm_u_type = {
|
||||
{riscv::XLEN - 32{instruction_i[31]}}, instruction_i[31:12], 12'b0
|
||||
{CVA6Cfg.XLEN - 32{instruction_i[31]}}, instruction_i[31:12], 12'b0
|
||||
}; // JAL, AUIPC, sign extended to 64 bit
|
||||
imm_uj_type = {
|
||||
{riscv::XLEN - 20{instruction_i[31]}},
|
||||
{CVA6Cfg.XLEN - 20{instruction_i[31]}},
|
||||
instruction_i[19:12],
|
||||
instruction_i[20],
|
||||
instruction_i[30:21],
|
||||
1'b0
|
||||
};
|
||||
imm_bi_type = {{riscv::XLEN - 5{instruction_i[24]}}, instruction_i[24:20]};
|
||||
imm_bi_type = {{CVA6Cfg.XLEN - 5{instruction_i[24]}}, instruction_i[24:20]};
|
||||
|
||||
// NOIMM, IIMM, SIMM, BIMM, UIMM, JIMM, RS3
|
||||
// select immediate
|
||||
|
|
@ -1325,11 +1327,11 @@ module decoder
|
|||
end
|
||||
RS3: begin
|
||||
// result holds address of fp operand rs3
|
||||
instruction_o.result = {{riscv::XLEN - 5{1'b0}}, instr.r4type.rs3};
|
||||
instruction_o.result = {{CVA6Cfg.XLEN - 5{1'b0}}, instr.r4type.rs3};
|
||||
instruction_o.use_imm = 1'b0;
|
||||
end
|
||||
default: begin
|
||||
instruction_o.result = {riscv::XLEN{1'b0}};
|
||||
instruction_o.result = {CVA6Cfg.XLEN{1'b0}};
|
||||
instruction_o.use_imm = 1'b0;
|
||||
end
|
||||
endcase
|
||||
|
|
@ -1345,7 +1347,7 @@ module decoder
|
|||
// ---------------------
|
||||
// Exception handling
|
||||
// ---------------------
|
||||
logic [riscv::XLEN-1:0] interrupt_cause;
|
||||
logic [CVA6Cfg.XLEN-1:0] interrupt_cause;
|
||||
|
||||
// this instruction has already executed if the exception is valid
|
||||
assign instruction_o.valid = instruction_o.ex.valid;
|
||||
|
|
@ -1360,9 +1362,9 @@ module decoder
|
|||
// if we didn't already get an exception save the instruction here as we may need it
|
||||
// in the commit stage if we got a access exception to one of the CSR registers
|
||||
if (CVA6Cfg.CvxifEn || CVA6Cfg.FpuEn)
|
||||
orig_instr_o = (is_compressed_i) ? {{riscv::XLEN-16{1'b0}}, compressed_instr_i} : {{riscv::XLEN-32{1'b0}}, instruction_i};
|
||||
orig_instr_o = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i};
|
||||
if (CVA6Cfg.TvalEn)
|
||||
instruction_o.ex.tval = (is_compressed_i) ? {{riscv::XLEN-16{1'b0}}, compressed_instr_i} : {{riscv::XLEN-32{1'b0}}, instruction_i};
|
||||
instruction_o.ex.tval = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i};
|
||||
else instruction_o.ex.tval = '0;
|
||||
// instructions which will throw an exception are marked as valid
|
||||
// e.g.: they can be committed anytime and do not need to wait for any functional unit
|
||||
|
|
@ -1424,11 +1426,11 @@ module decoder
|
|||
interrupt_cause = INTERRUPTS.M_EXT;
|
||||
end
|
||||
|
||||
if (interrupt_cause[riscv::XLEN-1] && irq_ctrl_i.global_enable) begin
|
||||
if (interrupt_cause[CVA6Cfg.XLEN-1] && irq_ctrl_i.global_enable) begin
|
||||
// However, if bit i in mideleg is set, interrupts are considered to be globally enabled if the hart’s current privilege
|
||||
// mode equals the delegated privilege mode (S or U) and that mode’s interrupt enable bit
|
||||
// (SIE or UIE in mstatus) is set, or if the current privilege mode is less than the delegated privilege mode.
|
||||
if (irq_ctrl_i.mideleg[interrupt_cause[$clog2(riscv::XLEN)-1:0]]) begin
|
||||
if (irq_ctrl_i.mideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin
|
||||
if ((CVA6Cfg.RVS && irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U)) begin
|
||||
instruction_o.ex.valid = 1'b1;
|
||||
instruction_o.ex.cause = interrupt_cause;
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ module ex_stage
|
|||
// Report whether isntruction is compressed - ISSUE_STAGE
|
||||
input logic is_compressed_instr_i,
|
||||
// Fixed Latency Unit result - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] flu_result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] flu_result_o,
|
||||
// ID of the scoreboard entry at which a=to write back - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] flu_trans_id_o,
|
||||
// Fixed Latency Unit exception - ISSUE_STAGE
|
||||
|
|
@ -83,7 +83,7 @@ module ex_stage
|
|||
// Load result is valid - ISSUE_STAGE
|
||||
output logic load_valid_o,
|
||||
// Load result valid - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] load_result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] load_result_o,
|
||||
// Load instruction ID - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_o,
|
||||
// Exception generated by load instruction - ISSUE_STAGE
|
||||
|
|
@ -91,7 +91,7 @@ module ex_stage
|
|||
// Store result is valid - ISSUe_STAGE
|
||||
output logic store_valid_o,
|
||||
// Store result - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] store_result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] store_result_o,
|
||||
// Store instruction ID - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] store_trans_id_o,
|
||||
// Exception generated by store instruction - ISSUE_STAGE
|
||||
|
|
@ -123,7 +123,7 @@ module ex_stage
|
|||
// FPU transaction ID - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id_o,
|
||||
// FPU result - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] fpu_result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] fpu_result_o,
|
||||
// FPU valid - ISSUE_STAGE
|
||||
output logic fpu_valid_o,
|
||||
// FPU exception - ISSUE_STAGE
|
||||
|
|
@ -139,7 +139,7 @@ module ex_stage
|
|||
// CVXIF exception - ISSUE_STAGE
|
||||
output exception_t x_exception_o,
|
||||
// CVXIF result - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] x_result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] x_result_o,
|
||||
// CVXIF result valid - ISSUE_STAGE
|
||||
output logic x_valid_o,
|
||||
// CVXIF write enable - ISSUE_STAGE
|
||||
|
|
@ -227,7 +227,7 @@ module ex_stage
|
|||
|
||||
// from ALU to branch unit
|
||||
logic alu_branch_res; // branch comparison result
|
||||
logic [riscv::XLEN-1:0] alu_result, csr_result, mult_result;
|
||||
logic [CVA6Cfg.XLEN-1:0] alu_result, csr_result, mult_result;
|
||||
logic [CVA6Cfg.VLEN-1:0] branch_result;
|
||||
logic csr_ready, mult_ready;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id;
|
||||
|
|
@ -297,7 +297,7 @@ module ex_stage
|
|||
// result MUX
|
||||
always_comb begin
|
||||
// Branch result as default case
|
||||
flu_result_o = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, branch_result};
|
||||
flu_result_o = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, branch_result};
|
||||
flu_trans_id_o = fu_data_i.trans_id;
|
||||
// ALU result
|
||||
if (alu_valid_i) begin
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ module fpu_wrap
|
|||
|
||||
// Features (enabled formats, vectors etc.)
|
||||
localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
|
||||
Width: unsigned'(riscv::XLEN), // parameterized using XLEN
|
||||
Width: unsigned'(CVA6Cfg.XLEN), // parameterized using CVA6Cfg.XLEN
|
||||
EnableVectors: CVA6Cfg.XFVec,
|
||||
EnableNanBox: 1'b1,
|
||||
FpFmtMask: {CVA6Cfg.RVF, CVA6Cfg.RVD, CVA6Cfg.XF16, CVA6Cfg.XF8, CVA6Cfg.XF16ALT},
|
||||
|
|
|
|||
|
|
@ -298,7 +298,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
|
|||
fetch_entry_o.ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
fetch_entry_o.ex.tval = {
|
||||
{(riscv::XLEN - CVA6Cfg.VLEN) {1'b0}}, instr_data_out[i].ex_vaddr
|
||||
{(CVA6Cfg.XLEN - CVA6Cfg.VLEN) {1'b0}}, instr_data_out[i].ex_vaddr
|
||||
};
|
||||
fetch_entry_o.branch_predict.cf = instr_data_out[i].cf;
|
||||
pop_instr[i] = fetch_entry_valid_o & fetch_entry_ready_i;
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ module instr_scan #(
|
|||
assign is_rvc = (instr_i[1:0] != 2'b11);
|
||||
|
||||
logic rv32_rvc_jal;
|
||||
assign rv32_rvc_jal = (riscv::XLEN == 32) & ((instr_i[15:13] == riscv::OpcodeC1Jal) & is_rvc & (instr_i[1:0] == riscv::OpcodeC1));
|
||||
assign rv32_rvc_jal = (CVA6Cfg.XLEN == 32) & ((instr_i[15:13] == riscv::OpcodeC1Jal) & is_rvc & (instr_i[1:0] == riscv::OpcodeC1));
|
||||
|
||||
logic is_xret;
|
||||
assign is_xret = logic'(instr_i[31:30] == 2'b00) & logic'(instr_i[28:0] == 29'b10000001000000000000001110011);
|
||||
|
|
|
|||
|
|
@ -613,9 +613,8 @@ package ariane_pkg;
|
|||
// ----------------------
|
||||
// Arithmetic Functions
|
||||
// ----------------------
|
||||
function automatic logic [riscv::XLEN-1:0] sext32(config_pkg::cva6_cfg_t Cfg,
|
||||
logic [31:0] operand);
|
||||
return {{riscv::XLEN - 32{operand[31]}}, operand[31:0]};
|
||||
function automatic logic [63:0] sext32to64(logic [31:0] operand);
|
||||
return {{32{operand[31]}}, operand[31:0]};
|
||||
endfunction
|
||||
|
||||
// ----------------------
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
package build_config_pkg;
|
||||
|
||||
function automatic config_pkg::cva6_cfg_t build_config(config_pkg::cva6_user_cfg_t CVA6Cfg);
|
||||
bit IS_XLEN32 = (riscv::XLEN == 32) ? 1'b1 : 1'b0;
|
||||
bit IS_XLEN64 = (riscv::XLEN == 32) ? 1'b0 : 1'b1;
|
||||
bit IS_XLEN32 = (CVA6Cfg.XLEN == 32) ? 1'b1 : 1'b0;
|
||||
bit IS_XLEN64 = (CVA6Cfg.XLEN == 32) ? 1'b0 : 1'b1;
|
||||
bit RVF = (IS_XLEN64 | IS_XLEN32) & CVA6Cfg.FpuEn;
|
||||
bit RVD = (IS_XLEN64 ? 1 : 0) & CVA6Cfg.FpuEn;
|
||||
bit FpPresent = RVF | RVD | CVA6Cfg.XF16 | CVA6Cfg.XF16ALT | CVA6Cfg.XF8;
|
||||
|
|
@ -29,12 +29,13 @@ package build_config_pkg;
|
|||
|
||||
config_pkg::cva6_cfg_t cfg;
|
||||
|
||||
cfg.VLEN = (riscv::XLEN == 32) ? 32 : 64;
|
||||
cfg.PLEN = (riscv::XLEN == 32) ? 34 : 56;
|
||||
cfg.XLEN = CVA6Cfg.XLEN;
|
||||
cfg.VLEN = (CVA6Cfg.XLEN == 32) ? 32 : 64;
|
||||
cfg.PLEN = (CVA6Cfg.XLEN == 32) ? 34 : 56;
|
||||
cfg.IS_XLEN32 = IS_XLEN32;
|
||||
cfg.IS_XLEN64 = IS_XLEN64;
|
||||
cfg.XLEN_ALIGN_BYTES = $clog2(riscv::XLEN / 8);
|
||||
cfg.ASID_WIDTH = (riscv::XLEN == 64) ? 16 : 1;
|
||||
cfg.XLEN_ALIGN_BYTES = $clog2(CVA6Cfg.XLEN / 8);
|
||||
cfg.ASID_WIDTH = (CVA6Cfg.XLEN == 64) ? 16 : 1;
|
||||
|
||||
cfg.FPGA_EN = CVA6Cfg.FPGA_EN;
|
||||
cfg.NrCommitPorts = CVA6Cfg.NrCommitPorts;
|
||||
|
|
@ -128,10 +129,10 @@ package build_config_pkg;
|
|||
cfg.INSTR_PER_FETCH = CVA6Cfg.RVC == 1'b1 ? (cfg.FETCH_WIDTH / 16) : 1;
|
||||
cfg.LOG2_INSTR_PER_FETCH = CVA6Cfg.RVC == 1'b1 ? $clog2(cfg.INSTR_PER_FETCH) : 1;
|
||||
|
||||
cfg.ModeW = (riscv::XLEN == 32) ? 1 : 4;
|
||||
cfg.ASIDW = (riscv::XLEN == 32) ? 9 : 16;
|
||||
cfg.PPNW = (riscv::XLEN == 32) ? 22 : 44;
|
||||
cfg.MODE_SV = (riscv::XLEN == 32) ? config_pkg::ModeSv32 : config_pkg::ModeSv39;
|
||||
cfg.ModeW = (CVA6Cfg.XLEN == 32) ? 1 : 4;
|
||||
cfg.ASIDW = (CVA6Cfg.XLEN == 32) ? 9 : 16;
|
||||
cfg.PPNW = (CVA6Cfg.XLEN == 32) ? 22 : 44;
|
||||
cfg.MODE_SV = (CVA6Cfg.XLEN == 32) ? config_pkg::ModeSv32 : config_pkg::ModeSv39;
|
||||
cfg.SV = (cfg.MODE_SV == config_pkg::ModeSv32) ? 32 : 39;
|
||||
|
||||
return cfg;
|
||||
|
|
|
|||
|
|
@ -46,6 +46,8 @@ package config_pkg;
|
|||
localparam NrMaxRules = 16;
|
||||
|
||||
typedef struct packed {
|
||||
// General Purpose Register Size (in bits)
|
||||
int unsigned XLEN;
|
||||
// Is FPGA optimization of CV32A6
|
||||
bit FPGA_EN;
|
||||
// Number of commit ports
|
||||
|
|
@ -163,6 +165,7 @@ package config_pkg;
|
|||
} cva6_user_cfg_t;
|
||||
|
||||
typedef struct packed {
|
||||
int unsigned XLEN;
|
||||
int unsigned VLEN;
|
||||
int unsigned PLEN;
|
||||
bit IS_XLEN32;
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -83,6 +83,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@ package cva6_config_pkg;
|
|||
localparam CVA6ConfigRvfiTrace = 1;
|
||||
|
||||
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
|
||||
XLEN: unsigned'(CVA6ConfigXlen),
|
||||
FPGA_EN: bit'(CVA6ConfigFPGAEn),
|
||||
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
|
||||
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
|
||||
|
|
|
|||
|
|
@ -7,32 +7,32 @@
|
|||
logic [config_pkg::NRET*64-1:0] order; \
|
||||
logic [config_pkg::NRET*config_pkg::ILEN-1:0] insn; \
|
||||
logic [config_pkg::NRET-1:0] trap; \
|
||||
logic [config_pkg::NRET*riscv::XLEN-1:0] cause; \
|
||||
logic [config_pkg::NRET*Cfg.XLEN-1:0] cause; \
|
||||
logic [config_pkg::NRET-1:0] halt; \
|
||||
logic [config_pkg::NRET-1:0] intr; \
|
||||
logic [config_pkg::NRET*2-1:0] mode; \
|
||||
logic [config_pkg::NRET*2-1:0] ixl; \
|
||||
logic [config_pkg::NRET*5-1:0] rs1_addr; \
|
||||
logic [config_pkg::NRET*5-1:0] rs2_addr; \
|
||||
logic [config_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; \
|
||||
logic [config_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; \
|
||||
logic [config_pkg::NRET*Cfg.XLEN-1:0] rs1_rdata; \
|
||||
logic [config_pkg::NRET*Cfg.XLEN-1:0] rs2_rdata; \
|
||||
logic [config_pkg::NRET*5-1:0] rd_addr; \
|
||||
logic [config_pkg::NRET*riscv::XLEN-1:0] rd_wdata; \
|
||||
logic [config_pkg::NRET*riscv::XLEN-1:0] pc_rdata; \
|
||||
logic [config_pkg::NRET*riscv::XLEN-1:0] pc_wdata; \
|
||||
logic [config_pkg::NRET*Cfg.XLEN-1:0] rd_wdata; \
|
||||
logic [config_pkg::NRET*Cfg.XLEN-1:0] pc_rdata; \
|
||||
logic [config_pkg::NRET*Cfg.XLEN-1:0] pc_wdata; \
|
||||
logic [config_pkg::NRET*Cfg.VLEN-1:0] mem_addr; \
|
||||
logic [config_pkg::NRET*Cfg.PLEN-1:0] mem_paddr; \
|
||||
logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; \
|
||||
logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; \
|
||||
logic [config_pkg::NRET*riscv::XLEN-1:0] mem_rdata; \
|
||||
logic [config_pkg::NRET*riscv::XLEN-1:0] mem_wdata; \
|
||||
logic [config_pkg::NRET*(Cfg.XLEN/8)-1:0] mem_rmask; \
|
||||
logic [config_pkg::NRET*(Cfg.XLEN/8)-1:0] mem_wmask; \
|
||||
logic [config_pkg::NRET*Cfg.XLEN-1:0] mem_rdata; \
|
||||
logic [config_pkg::NRET*Cfg.XLEN-1:0] mem_wdata; \
|
||||
}
|
||||
|
||||
`define RVFI_CSR_ELMT_T(Cfg) struct packed { \
|
||||
logic [riscv::XLEN-1:0] rdata; \
|
||||
logic [riscv::XLEN-1:0] rmask; \
|
||||
logic [riscv::XLEN-1:0] wdata; \
|
||||
logic [riscv::XLEN-1:0] wmask; \
|
||||
logic [Cfg.XLEN-1:0] rdata; \
|
||||
logic [Cfg.XLEN-1:0] rmask; \
|
||||
logic [Cfg.XLEN-1:0] wdata; \
|
||||
logic [Cfg.XLEN-1:0] wmask; \
|
||||
}
|
||||
|
||||
`define RVFI_CSR_T(Cfg, rvfi_csr_elmt_t) struct packed { \
|
||||
|
|
@ -103,60 +103,60 @@
|
|||
logic fetch_entry_valid; \
|
||||
logic [31:0] instruction; \
|
||||
logic is_compressed; \
|
||||
logic [riscv::XLEN-1:0] rs1_forwarding; \
|
||||
logic [riscv::XLEN-1:0] rs2_forwarding; \
|
||||
logic [Cfg.XLEN-1:0] rs1_forwarding; \
|
||||
logic [Cfg.XLEN-1:0] rs2_forwarding; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_pc; \
|
||||
ariane_pkg::fu_op [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.TRANS_ID_BITS-1:0] commit_instr_op; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs1; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs2; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rd; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::XLEN-1:0] commit_instr_result; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.XLEN-1:0] commit_instr_result; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_valid; \
|
||||
logic [riscv::XLEN-1:0] ex_commit_cause; \
|
||||
logic [Cfg.XLEN-1:0] ex_commit_cause; \
|
||||
logic ex_commit_valid; \
|
||||
riscv::priv_lvl_t priv_lvl; \
|
||||
logic [Cfg.VLEN-1:0] lsu_ctrl_vaddr; \
|
||||
ariane_pkg::fu_t lsu_ctrl_fu; \
|
||||
logic [(riscv::XLEN/8)-1:0] lsu_ctrl_be; \
|
||||
logic [(Cfg.XLEN/8)-1:0] lsu_ctrl_be; \
|
||||
logic [Cfg.TRANS_ID_BITS-1:0] lsu_ctrl_trans_id; \
|
||||
logic [((cva6_config_pkg::CVA6ConfigCvxifEn || cva6_config_pkg::CVA6ConfigVExtEn) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata; \
|
||||
logic [((cva6_config_pkg::CVA6ConfigCvxifEn || cva6_config_pkg::CVA6ConfigVExtEn) ? 5 : 4)-1:0][Cfg.XLEN-1:0] wbdata; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_ack; \
|
||||
logic [Cfg.PLEN-1:0] mem_paddr; \
|
||||
logic debug_mode; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::XLEN-1:0] wdata; \
|
||||
logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][Cfg.XLEN-1:0] wdata; \
|
||||
}
|
||||
|
||||
`define RVFI_PROBES_CSR_T(Cfg) struct packed { \
|
||||
riscv::fcsr_t fcsr_q; \
|
||||
riscv::dcsr_t dcsr_q; \
|
||||
logic [riscv::XLEN-1:0] dpc_q; \
|
||||
logic [riscv::XLEN-1:0] dscratch0_q; \
|
||||
logic [riscv::XLEN-1:0] dscratch1_q; \
|
||||
logic [riscv::XLEN-1:0] mie_q; \
|
||||
logic [riscv::XLEN-1:0] mip_q; \
|
||||
logic [riscv::XLEN-1:0] stvec_q; \
|
||||
logic [riscv::XLEN-1:0] scounteren_q; \
|
||||
logic [riscv::XLEN-1:0] sscratch_q; \
|
||||
logic [riscv::XLEN-1:0] sepc_q; \
|
||||
logic [riscv::XLEN-1:0] scause_q; \
|
||||
logic [riscv::XLEN-1:0] stval_q; \
|
||||
logic [riscv::XLEN-1:0] satp_q; \
|
||||
logic [riscv::XLEN-1:0] mstatus_extended; \
|
||||
logic [riscv::XLEN-1:0] medeleg_q; \
|
||||
logic [riscv::XLEN-1:0] mideleg_q; \
|
||||
logic [riscv::XLEN-1:0] mtvec_q; \
|
||||
logic [riscv::XLEN-1:0] mcounteren_q; \
|
||||
logic [riscv::XLEN-1:0] mscratch_q; \
|
||||
logic [riscv::XLEN-1:0] mepc_q; \
|
||||
logic [riscv::XLEN-1:0] mcause_q; \
|
||||
logic [riscv::XLEN-1:0] mtval_q; \
|
||||
logic [Cfg.XLEN-1:0] dpc_q; \
|
||||
logic [Cfg.XLEN-1:0] dscratch0_q; \
|
||||
logic [Cfg.XLEN-1:0] dscratch1_q; \
|
||||
logic [Cfg.XLEN-1:0] mie_q; \
|
||||
logic [Cfg.XLEN-1:0] mip_q; \
|
||||
logic [Cfg.XLEN-1:0] stvec_q; \
|
||||
logic [Cfg.XLEN-1:0] scounteren_q; \
|
||||
logic [Cfg.XLEN-1:0] sscratch_q; \
|
||||
logic [Cfg.XLEN-1:0] sepc_q; \
|
||||
logic [Cfg.XLEN-1:0] scause_q; \
|
||||
logic [Cfg.XLEN-1:0] stval_q; \
|
||||
logic [Cfg.XLEN-1:0] satp_q; \
|
||||
logic [Cfg.XLEN-1:0] mstatus_extended; \
|
||||
logic [Cfg.XLEN-1:0] medeleg_q; \
|
||||
logic [Cfg.XLEN-1:0] mideleg_q; \
|
||||
logic [Cfg.XLEN-1:0] mtvec_q; \
|
||||
logic [Cfg.XLEN-1:0] mcounteren_q; \
|
||||
logic [Cfg.XLEN-1:0] mscratch_q; \
|
||||
logic [Cfg.XLEN-1:0] mepc_q; \
|
||||
logic [Cfg.XLEN-1:0] mcause_q; \
|
||||
logic [Cfg.XLEN-1:0] mtval_q; \
|
||||
logic fiom_q; \
|
||||
logic [ariane_pkg::MHPMCounterNum+3-1:0] mcountinhibit_q; \
|
||||
logic [63:0] cycle_q; \
|
||||
logic [63:0] instret_q; \
|
||||
logic [riscv::XLEN-1:0] dcache_q; \
|
||||
logic [riscv::XLEN-1:0] icache_q; \
|
||||
logic [riscv::XLEN-1:0] acc_cons_q; \
|
||||
logic [Cfg.XLEN-1:0] dcache_q; \
|
||||
logic [Cfg.XLEN-1:0] icache_q; \
|
||||
logic [Cfg.XLEN-1:0] acc_cons_q; \
|
||||
riscv::pmpcfg_t [15:0] pmpcfg_q; \
|
||||
logic [15:0][Cfg.PLEN-3:0] pmpaddr_q; \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,13 +42,13 @@ module issue_read_operands
|
|||
// rs1 operand address - scoreboard
|
||||
output logic [REG_ADDR_SIZE-1:0] rs1_o,
|
||||
// rs1 operand - scoreboard
|
||||
input logic [riscv::XLEN-1:0] rs1_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] rs1_i,
|
||||
// rs1 operand is valid - scoreboard
|
||||
input logic rs1_valid_i,
|
||||
// rs2 operand address - scoreboard
|
||||
output logic [REG_ADDR_SIZE-1:0] rs2_o,
|
||||
// rs2 operand - scoreboard
|
||||
input logic [riscv::XLEN-1:0] rs2_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] rs2_i,
|
||||
// rs2 operand is valid - scoreboard
|
||||
input logic rs2_valid_i,
|
||||
// rs3 operand address - scoreboard
|
||||
|
|
@ -65,9 +65,9 @@ module issue_read_operands
|
|||
// TO_BE_COMPLETED - TO_BE_COMPLETED
|
||||
output fu_data_t fu_data_o,
|
||||
// Unregistered version of fu_data_o.operanda - TO_BE_COMPLETED
|
||||
output logic [riscv::XLEN-1:0] rs1_forwarding_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] rs1_forwarding_o,
|
||||
// Unregistered version of fu_data_o.operandb - TO_BE_COMPLETED
|
||||
output logic [riscv::XLEN-1:0] rs2_forwarding_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] rs2_forwarding_o,
|
||||
// Instruction pc - TO_BE_COMPLETED
|
||||
output logic [CVA6Cfg.VLEN-1:0] pc_o,
|
||||
// Is compressed instruction - TO_BE_COMPLETED
|
||||
|
|
@ -105,7 +105,7 @@ module issue_read_operands
|
|||
// TO_BE_COMPLETED - TO_BE_COMPLETED
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
|
||||
// TO_BE_COMPLETED - TO_BE_COMPLETED
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i,
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i,
|
||||
// TO_BE_COMPLETED - TO_BE_COMPLETED
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i,
|
||||
// TO_BE_COMPLETED - TO_BE_COMPLETED
|
||||
|
|
@ -116,13 +116,13 @@ module issue_read_operands
|
|||
);
|
||||
logic stall;
|
||||
logic fu_busy; // functional unit is busy
|
||||
logic [riscv::XLEN-1:0] operand_a_regfile, operand_b_regfile; // operands coming from regfile
|
||||
logic [CVA6Cfg.XLEN-1:0] operand_a_regfile, operand_b_regfile; // operands coming from regfile
|
||||
rs3_len_t
|
||||
operand_c_regfile,
|
||||
operand_c_fpr,
|
||||
operand_c_gpr; // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3
|
||||
// output flipflop (ID <-> EX)
|
||||
logic [riscv::XLEN-1:0]
|
||||
logic [CVA6Cfg.XLEN-1:0]
|
||||
operand_a_n, operand_a_q, operand_b_n, operand_b_q, imm_n, imm_q, imm_forward_rs3;
|
||||
|
||||
logic alu_valid_q;
|
||||
|
|
@ -262,7 +262,7 @@ module issue_read_operands
|
|||
if (CVA6Cfg.NrRgprPorts == 3) begin : gen_gp_rs3
|
||||
assign imm_forward_rs3 = rs3_i;
|
||||
end else begin : gen_fp_rs3
|
||||
assign imm_forward_rs3 = {{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, rs3_i};
|
||||
assign imm_forward_rs3 = {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, rs3_i};
|
||||
end
|
||||
|
||||
// Forwarding/Output MUX
|
||||
|
|
@ -274,11 +274,11 @@ module issue_read_operands
|
|||
// for FP operations, the imm field can also be the third operand from the regfile
|
||||
if (CVA6Cfg.NrRgprPorts == 3) begin
|
||||
imm_n = (CVA6Cfg.FpPresent && is_imm_fpr(issue_instr_i.op)) ?
|
||||
{{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, operand_c_regfile} :
|
||||
{{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, operand_c_regfile} :
|
||||
issue_instr_i.op == OFFLOAD ? operand_c_regfile : issue_instr_i.result;
|
||||
end else begin
|
||||
imm_n = (CVA6Cfg.FpPresent && is_imm_fpr(issue_instr_i.op)) ?
|
||||
{{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, operand_c_regfile} : issue_instr_i.result;
|
||||
{{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, operand_c_regfile} : issue_instr_i.result;
|
||||
end
|
||||
trans_id_n = issue_instr_i.trans_id;
|
||||
fu_n = issue_instr_i.fu;
|
||||
|
|
@ -299,14 +299,14 @@ module issue_read_operands
|
|||
// use the PC as operand a
|
||||
if (issue_instr_i.use_pc) begin
|
||||
operand_a_n = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{issue_instr_i.pc[CVA6Cfg.VLEN-1]}}, issue_instr_i.pc
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{issue_instr_i.pc[CVA6Cfg.VLEN-1]}}, issue_instr_i.pc
|
||||
};
|
||||
end
|
||||
|
||||
// use the zimm as operand a
|
||||
if (issue_instr_i.use_zimm) begin
|
||||
// zero extend operand a
|
||||
operand_a_n = {{riscv::XLEN - 5{1'b0}}, issue_instr_i.rs1[4:0]};
|
||||
operand_a_n = {{CVA6Cfg.XLEN - 5{1'b0}}, issue_instr_i.rs1[4:0]};
|
||||
end
|
||||
// or is it an immediate (including PC), this is not the case for a store, control flow, and accelerator instructions
|
||||
// also make sure operand B is not already used as an FP operand
|
||||
|
|
@ -464,13 +464,13 @@ module issue_read_operands
|
|||
// ----------------------
|
||||
// Integer Register File
|
||||
// ----------------------
|
||||
logic [ CVA6Cfg.NrRgprPorts-1:0][riscv::XLEN-1:0] rdata;
|
||||
logic [ CVA6Cfg.NrRgprPorts-1:0][ 4:0] raddr_pack;
|
||||
logic [ CVA6Cfg.NrRgprPorts-1:0][CVA6Cfg.XLEN-1:0] rdata;
|
||||
logic [ CVA6Cfg.NrRgprPorts-1:0][ 4:0] raddr_pack;
|
||||
|
||||
// pack signals
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][ 4:0] waddr_pack;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_pack;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0] we_pack;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][ 4:0] waddr_pack;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_pack;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0] we_pack;
|
||||
|
||||
if (CVA6Cfg.NrRgprPorts == 3) begin : gen_rs3
|
||||
assign raddr_pack = {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]};
|
||||
|
|
@ -486,7 +486,7 @@ module issue_read_operands
|
|||
if (CVA6Cfg.FPGA_EN) begin : gen_fpga_regfile
|
||||
ariane_regfile_fpga #(
|
||||
.CVA6Cfg (CVA6Cfg),
|
||||
.DATA_WIDTH (riscv::XLEN),
|
||||
.DATA_WIDTH (CVA6Cfg.XLEN),
|
||||
.NR_READ_PORTS(CVA6Cfg.NrRgprPorts),
|
||||
.ZERO_REG_ZERO(1)
|
||||
) i_ariane_regfile_fpga (
|
||||
|
|
@ -501,7 +501,7 @@ module issue_read_operands
|
|||
end else begin : gen_asic_regfile
|
||||
ariane_regfile #(
|
||||
.CVA6Cfg (CVA6Cfg),
|
||||
.DATA_WIDTH (riscv::XLEN),
|
||||
.DATA_WIDTH (CVA6Cfg.XLEN),
|
||||
.NR_READ_PORTS(CVA6Cfg.NrRgprPorts),
|
||||
.ZERO_REG_ZERO(1)
|
||||
) i_ariane_regfile (
|
||||
|
|
@ -522,7 +522,7 @@ module issue_read_operands
|
|||
|
||||
// pack signals
|
||||
logic [2:0][4:0] fp_raddr_pack;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] fp_wdata_pack;
|
||||
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] fp_wdata_pack;
|
||||
|
||||
generate
|
||||
if (CVA6Cfg.FpPresent) begin : float_regfile_gen
|
||||
|
|
@ -569,7 +569,7 @@ module issue_read_operands
|
|||
endgenerate
|
||||
|
||||
if (CVA6Cfg.NrRgprPorts == 3) begin : gen_operand_c
|
||||
assign operand_c_fpr = {{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[2]};
|
||||
assign operand_c_fpr = {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[2]};
|
||||
assign operand_c_gpr = rdata[2];
|
||||
end else begin
|
||||
assign operand_c_fpr = fprdata[2];
|
||||
|
|
@ -577,10 +577,10 @@ module issue_read_operands
|
|||
|
||||
assign operand_a_regfile = (CVA6Cfg.FpPresent && is_rs1_fpr(
|
||||
issue_instr_i.op
|
||||
)) ? {{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[0]} : rdata[0];
|
||||
)) ? {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[0]} : rdata[0];
|
||||
assign operand_b_regfile = (CVA6Cfg.FpPresent && is_rs2_fpr(
|
||||
issue_instr_i.op
|
||||
)) ? {{riscv::XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[1]} : rdata[1];
|
||||
)) ? {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, fprdata[1]} : rdata[1];
|
||||
assign operand_c_regfile = (CVA6Cfg.NrRgprPorts == 3) ? ((CVA6Cfg.FpPresent && is_imm_fpr(
|
||||
issue_instr_i.op
|
||||
)) ? operand_c_fpr : operand_c_gpr) : operand_c_fpr;
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ module issue_stage
|
|||
// The branch engine uses the write back from the ALU - EX_STAGE
|
||||
input bp_resolve_t resolved_branch_i,
|
||||
// TO_BE_COMPLETED - EX_STAGE
|
||||
input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i,
|
||||
input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_i,
|
||||
// exception from execute stage or CVXIF - EX_STAGE
|
||||
input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_i,
|
||||
// TO_BE_COMPLETED - EX_STAGE
|
||||
|
|
@ -107,7 +107,7 @@ module issue_stage
|
|||
// TO_BE_COMPLETED - EX_STAGE
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
|
||||
// TO_BE_COMPLETED - EX_STAGE
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i,
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_i,
|
||||
// GPR write enable - EX_STAGE
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i,
|
||||
// FPR write enable - EX_STAGE
|
||||
|
|
@ -126,17 +126,17 @@ module issue_stage
|
|||
// ---------------------------------------------------
|
||||
// Scoreboard (SB) <-> Issue and Read Operands (IRO)
|
||||
// ---------------------------------------------------
|
||||
typedef logic [(CVA6Cfg.NrRgprPorts == 3 ? riscv::XLEN : CVA6Cfg.FLen)-1:0] rs3_len_t;
|
||||
typedef logic [(CVA6Cfg.NrRgprPorts == 3 ? CVA6Cfg.XLEN : CVA6Cfg.FLen)-1:0] rs3_len_t;
|
||||
|
||||
fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_gpr_sb_iro;
|
||||
fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_fpr_sb_iro;
|
||||
|
||||
logic [ REG_ADDR_SIZE-1:0] rs1_iro_sb;
|
||||
logic [ riscv::XLEN-1:0] rs1_sb_iro;
|
||||
logic [ CVA6Cfg.XLEN-1:0] rs1_sb_iro;
|
||||
logic rs1_valid_sb_iro;
|
||||
|
||||
logic [ REG_ADDR_SIZE-1:0] rs2_iro_sb;
|
||||
logic [ riscv::XLEN-1:0] rs2_sb_iro;
|
||||
logic [ CVA6Cfg.XLEN-1:0] rs2_sb_iro;
|
||||
logic rs2_valid_iro_sb;
|
||||
|
||||
logic [ REG_ADDR_SIZE-1:0] rs3_iro_sb;
|
||||
|
|
@ -148,8 +148,8 @@ module issue_stage
|
|||
logic issue_instr_valid_sb_iro;
|
||||
logic issue_ack_iro_sb;
|
||||
|
||||
logic [ riscv::XLEN-1:0] rs1_forwarding_xlen;
|
||||
logic [ riscv::XLEN-1:0] rs2_forwarding_xlen;
|
||||
logic [ CVA6Cfg.XLEN-1:0] rs1_forwarding_xlen;
|
||||
logic [ CVA6Cfg.XLEN-1:0] rs2_forwarding_xlen;
|
||||
|
||||
assign rs1_forwarding_o = rs1_forwarding_xlen[CVA6Cfg.VLEN-1:0];
|
||||
assign rs2_forwarding_o = rs2_forwarding_xlen[CVA6Cfg.VLEN-1:0];
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ module load_store_unit
|
|||
// Load transaction ID - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_o,
|
||||
// Load result - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] load_result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] load_result_o,
|
||||
// Load result is valid - ISSUE_STAGE
|
||||
output logic load_valid_o,
|
||||
// Load exception - ISSUE_STAGE
|
||||
|
|
@ -58,7 +58,7 @@ module load_store_unit
|
|||
// Store transaction ID - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] store_trans_id_o,
|
||||
// Store result - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] store_result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] store_result_o,
|
||||
// Store result is valid - ISSUE_STAGE
|
||||
output logic store_valid_o,
|
||||
// Store exception - ISSUE_STAGE
|
||||
|
|
@ -128,30 +128,30 @@ module load_store_unit
|
|||
);
|
||||
|
||||
// data is misaligned
|
||||
logic data_misaligned;
|
||||
logic data_misaligned;
|
||||
// --------------------------------------
|
||||
// 1st register stage - (stall registers)
|
||||
// --------------------------------------
|
||||
// those are the signals which are always correct
|
||||
// e.g.: they keep the value in the stall case
|
||||
lsu_ctrl_t lsu_ctrl;
|
||||
lsu_ctrl_t lsu_ctrl;
|
||||
|
||||
logic pop_st;
|
||||
logic pop_ld;
|
||||
logic pop_st;
|
||||
logic pop_ld;
|
||||
|
||||
// ------------------------------
|
||||
// Address Generation Unit (AGU)
|
||||
// ------------------------------
|
||||
// virtual address as calculated by the AGU in the first cycle
|
||||
logic [ CVA6Cfg.VLEN-1:0] vaddr_i;
|
||||
logic [ riscv::XLEN-1:0] vaddr_xlen;
|
||||
logic overflow;
|
||||
logic [(riscv::XLEN/8)-1:0] be_i;
|
||||
logic [ CVA6Cfg.VLEN-1:0] vaddr_i;
|
||||
logic [ CVA6Cfg.XLEN-1:0] vaddr_xlen;
|
||||
logic overflow;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] be_i;
|
||||
|
||||
assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a));
|
||||
assign vaddr_i = vaddr_xlen[CVA6Cfg.VLEN-1:0];
|
||||
// we work with SV39 or SV32, so if VM is enabled, check that all bits [XLEN-1:38] or [XLEN-1:31] are equal
|
||||
assign overflow = (CVA6Cfg.IS_XLEN64 && (!((&vaddr_xlen[riscv::XLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|vaddr_xlen[riscv::XLEN-1:CVA6Cfg.SV-1]) == 1'b0)));
|
||||
// we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.XLEN-1:38] or [CVA6Cfg.XLEN-1:31] are equal
|
||||
assign overflow = (CVA6Cfg.IS_XLEN64 && (!((&vaddr_xlen[CVA6Cfg.XLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|vaddr_xlen[CVA6Cfg.XLEN-1:CVA6Cfg.SV-1]) == 1'b0)));
|
||||
|
||||
logic st_valid_i;
|
||||
logic ld_valid_i;
|
||||
|
|
@ -169,10 +169,10 @@ module load_store_unit
|
|||
|
||||
logic ld_valid;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id;
|
||||
logic [ riscv::XLEN-1:0] ld_result;
|
||||
logic [ CVA6Cfg.XLEN-1:0] ld_result;
|
||||
logic st_valid;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id;
|
||||
logic [ riscv::XLEN-1:0] st_result;
|
||||
logic [ CVA6Cfg.XLEN-1:0] st_result;
|
||||
|
||||
logic [ 11:0] page_offset;
|
||||
logic page_offset_matches;
|
||||
|
|
@ -184,7 +184,7 @@ module load_store_unit
|
|||
// -------------------
|
||||
// MMU e.g.: TLBs/PTW
|
||||
// -------------------
|
||||
if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39
|
||||
if (MMU_PRESENT && (CVA6Cfg.XLEN == 64)) begin : gen_mmu_sv39
|
||||
mmu #(
|
||||
.CVA6Cfg (CVA6Cfg),
|
||||
.exception_t (exception_t),
|
||||
|
|
@ -219,7 +219,7 @@ module load_store_unit
|
|||
.pmpaddr_i,
|
||||
.*
|
||||
);
|
||||
end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32
|
||||
end else if (MMU_PRESENT && (CVA6Cfg.XLEN == 32)) begin : gen_mmu_sv32
|
||||
cva6_mmu_sv32 #(
|
||||
.CVA6Cfg (CVA6Cfg),
|
||||
.exception_t (exception_t),
|
||||
|
|
@ -458,7 +458,7 @@ module load_store_unit
|
|||
// can augment the exception if other memory related exceptions like a page fault or access errors
|
||||
always_comb begin : data_misaligned_detection
|
||||
|
||||
misaligned_exception = {{riscv::XLEN{1'b0}}, {riscv::XLEN{1'b0}}, 1'b0};
|
||||
misaligned_exception = {{CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.XLEN{1'b0}}, 1'b0};
|
||||
|
||||
data_misaligned = 1'b0;
|
||||
|
||||
|
|
@ -501,13 +501,13 @@ module load_store_unit
|
|||
misaligned_exception.cause = riscv::LD_ADDR_MISALIGNED;
|
||||
misaligned_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
misaligned_exception.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
||||
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
||||
|
||||
end else if (lsu_ctrl.fu == STORE) begin
|
||||
misaligned_exception.cause = riscv::ST_ADDR_MISALIGNED;
|
||||
misaligned_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
misaligned_exception.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
||||
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -517,13 +517,13 @@ module load_store_unit
|
|||
misaligned_exception.cause = riscv::LD_ACCESS_FAULT;
|
||||
misaligned_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
misaligned_exception.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
||||
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
||||
|
||||
end else if (lsu_ctrl.fu == STORE) begin
|
||||
misaligned_exception.cause = riscv::ST_ACCESS_FAULT;
|
||||
misaligned_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
misaligned_exception.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
||||
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ module load_unit
|
|||
// Load transaction ID - TO_BE_COMPLETED
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_o,
|
||||
// Load result - TO_BE_COMPLETED
|
||||
output logic [riscv::XLEN-1:0] result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] result_o,
|
||||
// Load exception - TO_BE_COMPLETED
|
||||
output exception_t ex_o,
|
||||
// Request address translation - TO_BE_COMPLETED
|
||||
|
|
@ -453,7 +453,7 @@ module load_unit
|
|||
// ---------------
|
||||
// Sign Extend
|
||||
// ---------------
|
||||
logic [riscv::XLEN-1:0] shifted_data;
|
||||
logic [CVA6Cfg.XLEN-1:0] shifted_data;
|
||||
|
||||
// realign as needed
|
||||
assign shifted_data = req_port_i.data_rdata >> {ldbuf_rdata.address_offset, 3'b000};
|
||||
|
|
@ -473,7 +473,7 @@ module load_unit
|
|||
end */
|
||||
|
||||
// result mux fast
|
||||
logic [ (riscv::XLEN/8)-1:0] rdata_sign_bits;
|
||||
logic [ (CVA6Cfg.XLEN/8)-1:0] rdata_sign_bits;
|
||||
logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] rdata_offset;
|
||||
logic rdata_sign_bit, rdata_is_signed, rdata_is_fp_signed;
|
||||
|
||||
|
|
@ -485,7 +485,7 @@ module load_unit
|
|||
( ldbuf_rdata.operation inside {ariane_pkg::LH, ariane_pkg::FLH}) ? ldbuf_rdata.address_offset + 1 :
|
||||
ldbuf_rdata.address_offset;
|
||||
|
||||
for (genvar i = 0; i < (riscv::XLEN / 8); i++) begin : gen_sign_bits
|
||||
for (genvar i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : gen_sign_bits
|
||||
assign rdata_sign_bits[i] = req_port_i.data_rdata[(i+1)*8-1];
|
||||
end
|
||||
|
||||
|
|
@ -498,30 +498,30 @@ module load_unit
|
|||
always_comb begin
|
||||
unique case (ldbuf_rdata.operation)
|
||||
ariane_pkg::LW, ariane_pkg::LWU:
|
||||
result_o = {{riscv::XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]};
|
||||
result_o = {{CVA6Cfg.XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]};
|
||||
ariane_pkg::LH, ariane_pkg::LHU:
|
||||
result_o = {{riscv::XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]};
|
||||
result_o = {{CVA6Cfg.XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]};
|
||||
ariane_pkg::LB, ariane_pkg::LBU:
|
||||
result_o = {{riscv::XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]};
|
||||
result_o = {{CVA6Cfg.XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]};
|
||||
default: begin
|
||||
// FLW, FLH and FLB have been defined here in default case to improve Code Coverage
|
||||
if (CVA6Cfg.FpPresent) begin
|
||||
unique case (ldbuf_rdata.operation)
|
||||
ariane_pkg::FLW: begin
|
||||
result_o = {{riscv::XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]};
|
||||
result_o = {{CVA6Cfg.XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]};
|
||||
end
|
||||
ariane_pkg::FLH: begin
|
||||
result_o = {{riscv::XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]};
|
||||
result_o = {{CVA6Cfg.XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]};
|
||||
end
|
||||
ariane_pkg::FLB: begin
|
||||
result_o = {{riscv::XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]};
|
||||
result_o = {{CVA6Cfg.XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]};
|
||||
end
|
||||
default: begin
|
||||
result_o = shifted_data[riscv::XLEN-1:0];
|
||||
result_o = shifted_data[CVA6Cfg.XLEN-1:0];
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
result_o = shifted_data[riscv::XLEN-1:0];
|
||||
result_o = shifted_data[CVA6Cfg.XLEN-1:0];
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ module macro_decoder #(
|
|||
default: reg_numbers = '0;
|
||||
endcase
|
||||
|
||||
if (riscv::XLEN == 32) begin
|
||||
if (CVA6Cfg.XLEN == 32) begin
|
||||
unique case (instr_i[7:4])
|
||||
4'b0100, 4'b0101, 4'b0110, 4'b0111: begin
|
||||
unique case (instr_i[3:2])
|
||||
|
|
@ -327,7 +327,7 @@ module macro_decoder #(
|
|||
fetch_stall_o = 1'b1; // stall inst fetch
|
||||
|
||||
if (reg_numbers == 4'b0001) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
7'b1111111, 5'h1, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore
|
||||
}; // sd store_reg, -4(sp)
|
||||
|
|
@ -340,7 +340,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers == 4'b0010) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {7'b1111111, 5'h8, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore};
|
||||
end else begin
|
||||
instr_o_reg = {7'b1111111, 5'h8, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore};
|
||||
|
|
@ -348,7 +348,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers == 4'b0011) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {7'b1111111, 5'h9, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore};
|
||||
end else begin
|
||||
instr_o_reg = {7'b1111111, 5'h9, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore};
|
||||
|
|
@ -357,7 +357,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers >= 4 && reg_numbers <= 12) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {7'b1111111, store_reg, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore};
|
||||
end else begin
|
||||
instr_o_reg = {7'b1111111, store_reg, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore};
|
||||
|
|
@ -372,7 +372,7 @@ module macro_decoder #(
|
|||
if ((macro_instr_type == POP || macro_instr_type == POPRETZ || macro_instr_type == POPRET)) begin
|
||||
fetch_stall_o = 1; // stall inst fetch
|
||||
if (reg_numbers == 1) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_reg - 12'h4, 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad
|
||||
}; // ld store_reg, Imm(sp)
|
||||
|
|
@ -393,7 +393,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers == 2) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad};
|
||||
end else begin
|
||||
instr_o_reg = {offset_reg, 5'h2, 3'h2, 5'h8, riscv::OpcodeLoad};
|
||||
|
|
@ -401,7 +401,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers == 3) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad};
|
||||
end else begin
|
||||
instr_o_reg = {offset_reg, 5'h2, 3'h2, 5'h9, riscv::OpcodeLoad};
|
||||
|
|
@ -409,7 +409,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers >= 4 && reg_numbers <= 12) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, store_reg, riscv::OpcodeLoad};
|
||||
end else begin
|
||||
instr_o_reg = {offset_reg, 5'h2, 3'h2, store_reg, riscv::OpcodeLoad};
|
||||
|
|
@ -426,7 +426,7 @@ module macro_decoder #(
|
|||
fetch_stall_o = 1'b1; // stall inst fetch
|
||||
if (issue_ack_i && is_macro_instr_i && macro_instr_type == PUSH) begin
|
||||
if (reg_numbers_q == 4'b0001) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_d[11:5],
|
||||
5'h1,
|
||||
|
|
@ -444,7 +444,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers_q == 4'b0010) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_d[11:5],
|
||||
5'h8,
|
||||
|
|
@ -463,7 +463,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers_q == 4'b0011) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_d[11:5],
|
||||
5'h9,
|
||||
|
|
@ -482,7 +482,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers_q >= 4 && reg_numbers_q <= 12) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_d[11:5],
|
||||
store_reg_q,
|
||||
|
|
@ -510,7 +510,7 @@ module macro_decoder #(
|
|||
if (issue_ack_i && is_macro_instr_i && (macro_instr_type == POP || macro_instr_type == POPRETZ || macro_instr_type == POPRET)) begin
|
||||
|
||||
if (reg_numbers_q == 1) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad
|
||||
};
|
||||
|
|
@ -529,7 +529,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers_q == 2) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad
|
||||
};
|
||||
|
|
@ -541,7 +541,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers_q == 3) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad
|
||||
};
|
||||
|
|
@ -553,7 +553,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
if (reg_numbers_q >= 4 && reg_numbers_q <= 12) begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
instr_o_reg = {
|
||||
offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, store_reg_q, riscv::OpcodeLoad
|
||||
};
|
||||
|
|
@ -600,7 +600,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
PUSH_ADDI: begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
if (issue_ack_i && is_macro_instr_i && macro_instr_type == PUSH) begin
|
||||
// addi sp, sp, stack_adj
|
||||
instr_o_reg = {itype_inst.imm - 12'h4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm};
|
||||
|
|
@ -646,7 +646,7 @@ module macro_decoder #(
|
|||
end
|
||||
|
||||
PUSH_POP_INSTR_2: begin
|
||||
if (riscv::XLEN == 64) begin
|
||||
if (CVA6Cfg.XLEN == 64) begin
|
||||
case (macro_instr_type)
|
||||
PUSH: begin
|
||||
if (issue_ack_i) begin
|
||||
|
|
|
|||
|
|
@ -304,7 +304,7 @@ module cva6_mmu_sv32
|
|||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
};
|
||||
end
|
||||
|
||||
|
|
@ -331,7 +331,7 @@ module cva6_mmu_sv32
|
|||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
};
|
||||
//to check on wave --> not connected
|
||||
end else if (!pmp_instr_allow) begin
|
||||
|
|
@ -351,7 +351,9 @@ module cva6_mmu_sv32
|
|||
icache_areq_o.fetch_exception.cause = riscv::INSTR_PAGE_FAULT;
|
||||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, update_vaddr};
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, update_vaddr
|
||||
};
|
||||
end //to check on wave
|
||||
// TODO(moschn,zarubaf): What should the value of tval be in this case?
|
||||
else begin
|
||||
|
|
@ -470,7 +472,7 @@ module cva6_mmu_sv32
|
|||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
};
|
||||
// to check on wave
|
||||
// Check if any PMPs are violated
|
||||
|
|
@ -489,7 +491,7 @@ module cva6_mmu_sv32
|
|||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
};
|
||||
// Check if any PMPs are violated
|
||||
end else if (!pmp_data_allow) begin
|
||||
|
|
@ -515,14 +517,14 @@ module cva6_mmu_sv32
|
|||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr
|
||||
};
|
||||
end else begin
|
||||
lsu_exception_o.cause = riscv::LOAD_PAGE_FAULT;
|
||||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr
|
||||
};
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ module cva6_ptw_sv32
|
|||
|
||||
// input registers
|
||||
logic data_rvalid_q;
|
||||
logic [riscv::XLEN-1:0] data_rdata_q;
|
||||
logic [CVA6Cfg.XLEN-1:0] data_rdata_q;
|
||||
|
||||
riscv::pte_sv32_t pte;
|
||||
assign pte = riscv::pte_sv32_t'(data_rdata_q);
|
||||
|
|
|
|||
|
|
@ -243,7 +243,7 @@ module mmu
|
|||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
};
|
||||
end
|
||||
|
||||
|
|
@ -273,14 +273,14 @@ module mmu
|
|||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
};
|
||||
end else if (!pmp_instr_allow) begin
|
||||
icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT;
|
||||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, icache_areq_i.fetch_vaddr
|
||||
};
|
||||
end
|
||||
end else
|
||||
|
|
@ -294,12 +294,16 @@ module mmu
|
|||
icache_areq_o.fetch_exception.cause = riscv::INSTR_PAGE_FAULT;
|
||||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, update_vaddr};
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, update_vaddr
|
||||
};
|
||||
end else begin
|
||||
icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT;
|
||||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, update_vaddr};
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, update_vaddr
|
||||
};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -310,7 +314,7 @@ module mmu
|
|||
icache_areq_o.fetch_exception.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
icache_areq_o.fetch_exception.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.PLEN{1'b0}}, icache_areq_o.fetch_paddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.PLEN{1'b0}}, icache_areq_o.fetch_paddr
|
||||
};
|
||||
end
|
||||
end
|
||||
|
|
@ -416,7 +420,7 @@ module mmu
|
|||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
};
|
||||
// Check if any PMPs are violated
|
||||
end else if (!pmp_data_allow) begin
|
||||
|
|
@ -424,7 +428,7 @@ module mmu
|
|||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
};
|
||||
end
|
||||
|
||||
|
|
@ -436,7 +440,7 @@ module mmu
|
|||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
};
|
||||
// Check if any PMPs are violated
|
||||
end else if (!pmp_data_allow) begin
|
||||
|
|
@ -444,7 +448,7 @@ module mmu
|
|||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
|
||||
};
|
||||
end
|
||||
end
|
||||
|
|
@ -465,14 +469,14 @@ module mmu
|
|||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr
|
||||
};
|
||||
end else begin
|
||||
lsu_exception_o.cause = riscv::LOAD_PAGE_FAULT;
|
||||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {
|
||||
{riscv::XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr
|
||||
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, update_vaddr
|
||||
};
|
||||
end
|
||||
end
|
||||
|
|
@ -485,12 +489,12 @@ module mmu
|
|||
lsu_exception_o.cause = riscv::ST_ACCESS_FAULT;
|
||||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_vaddr_n};
|
||||
lsu_exception_o.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_vaddr_n};
|
||||
end else begin
|
||||
lsu_exception_o.cause = riscv::LD_ACCESS_FAULT;
|
||||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {{riscv::XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_vaddr_n};
|
||||
lsu_exception_o.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_vaddr_n};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -500,12 +504,12 @@ module mmu
|
|||
lsu_exception_o.cause = riscv::ST_ACCESS_FAULT;
|
||||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {{riscv::XLEN - CVA6Cfg.PLEN{1'b0}}, lsu_paddr_o};
|
||||
lsu_exception_o.tval = {{CVA6Cfg.XLEN - CVA6Cfg.PLEN{1'b0}}, lsu_paddr_o};
|
||||
end else begin
|
||||
lsu_exception_o.cause = riscv::LD_ACCESS_FAULT;
|
||||
lsu_exception_o.valid = 1'b1;
|
||||
if (CVA6Cfg.TvalEn)
|
||||
lsu_exception_o.tval = {{riscv::XLEN - CVA6Cfg.PLEN{1'b0}}, lsu_paddr_o};
|
||||
lsu_exception_o.tval = {{CVA6Cfg.XLEN - CVA6Cfg.PLEN{1'b0}}, lsu_paddr_o};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
22
core/mult.sv
22
core/mult.sv
|
|
@ -17,7 +17,7 @@ module mult
|
|||
// Mult instruction is valid - ISSUE_STAGE
|
||||
input logic mult_valid_i,
|
||||
// Mult result - ISSUE_STAGE
|
||||
output logic [ riscv::XLEN-1:0] result_o,
|
||||
output logic [ CVA6Cfg.XLEN-1:0] result_o,
|
||||
// Mult result is valid - ISSUE_STAGE
|
||||
output logic mult_valid_o,
|
||||
// Mutl is ready - ISSUE_STAGE
|
||||
|
|
@ -30,8 +30,8 @@ module mult
|
|||
logic div_ready_i; // receiver of division result is able to accept the result
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] mul_trans_id;
|
||||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] div_trans_id;
|
||||
logic [riscv::XLEN-1:0] mul_result;
|
||||
logic [riscv::XLEN-1:0] div_result;
|
||||
logic [CVA6Cfg.XLEN-1:0] mul_result;
|
||||
logic [CVA6Cfg.XLEN-1:0] div_result;
|
||||
|
||||
logic div_valid_op;
|
||||
logic mul_valid_op;
|
||||
|
|
@ -74,13 +74,13 @@ module mult
|
|||
// ---------------------
|
||||
// Division
|
||||
// ---------------------
|
||||
logic [riscv::XLEN-1:0]
|
||||
logic [CVA6Cfg.XLEN-1:0]
|
||||
operand_b,
|
||||
operand_a; // input operands after input MUX (input silencing, word operations or full inputs)
|
||||
logic [riscv::XLEN-1:0] result; // result before result mux
|
||||
logic [CVA6Cfg.XLEN-1:0] result; // result before result mux
|
||||
|
||||
logic div_signed; // signed or unsigned division
|
||||
logic rem; // is it a reminder (or not a reminder e.g.: a division)
|
||||
logic div_signed; // signed or unsigned division
|
||||
logic rem; // is it a reminder (or not a reminder e.g.: a division)
|
||||
logic word_op_d, word_op_q; // save whether the operation was signed or not
|
||||
|
||||
// is this a signed op?
|
||||
|
|
@ -102,8 +102,8 @@ module mult
|
|||
if (CVA6Cfg.IS_XLEN64 && (fu_data_i.operation == DIVW || fu_data_i.operation == DIVUW || fu_data_i.operation == REMW || fu_data_i.operation == REMUW)) begin
|
||||
// yes so check if we should sign extend this is only done for a signed operation
|
||||
if (div_signed) begin
|
||||
operand_a = sext32(CVA6Cfg, fu_data_i.operand_a[31:0]);
|
||||
operand_b = sext32(CVA6Cfg, fu_data_i.operand_b[31:0]);
|
||||
operand_a = sext32to64(fu_data_i.operand_a[31:0]);
|
||||
operand_b = sext32to64(fu_data_i.operand_b[31:0]);
|
||||
end else begin
|
||||
operand_a = fu_data_i.operand_a[31:0];
|
||||
operand_b = fu_data_i.operand_b[31:0];
|
||||
|
|
@ -125,7 +125,7 @@ module mult
|
|||
// ---------------------
|
||||
serdiv #(
|
||||
.CVA6Cfg(CVA6Cfg),
|
||||
.WIDTH (riscv::XLEN)
|
||||
.WIDTH (CVA6Cfg.XLEN)
|
||||
) i_div (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
|
|
@ -144,7 +144,7 @@ module mult
|
|||
|
||||
// Result multiplexer
|
||||
// if it was a signed word operation the bit will be set and the result will be sign extended accordingly
|
||||
assign div_result = (CVA6Cfg.IS_XLEN64 && word_op_q) ? sext32(CVA6Cfg, result) : result;
|
||||
assign div_result = (CVA6Cfg.IS_XLEN64 && word_op_q) ? sext32to64(result) : result;
|
||||
|
||||
// ---------------------
|
||||
// Registers
|
||||
|
|
|
|||
|
|
@ -31,11 +31,11 @@ module multiplier
|
|||
// Multiplier operation - Mult
|
||||
input fu_op operation_i,
|
||||
// A operand - Mult
|
||||
input logic [ riscv::XLEN-1:0] operand_a_i,
|
||||
input logic [ CVA6Cfg.XLEN-1:0] operand_a_i,
|
||||
// B operand - Mult
|
||||
input logic [ riscv::XLEN-1:0] operand_b_i,
|
||||
input logic [ CVA6Cfg.XLEN-1:0] operand_b_i,
|
||||
// Multiplier result - Mult
|
||||
output logic [ riscv::XLEN-1:0] result_o,
|
||||
output logic [ CVA6Cfg.XLEN-1:0] result_o,
|
||||
// Mutliplier result is valid - Mult
|
||||
output logic mult_valid_o,
|
||||
// Multiplier FU is ready - Mult
|
||||
|
|
@ -44,7 +44,7 @@ module multiplier
|
|||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id_o
|
||||
);
|
||||
// Carry-less multiplication
|
||||
logic [riscv::XLEN-1:0]
|
||||
logic [CVA6Cfg.XLEN-1:0]
|
||||
clmul_q, clmul_d, clmulr_q, clmulr_d, operand_a, operand_b, operand_a_rev, operand_b_rev;
|
||||
logic clmul_rmode, clmul_hmode;
|
||||
|
||||
|
|
@ -54,9 +54,9 @@ module multiplier
|
|||
assign clmul_hmode = (operation_i == CLMULH);
|
||||
|
||||
// operand_a and b reverse generator
|
||||
for (genvar i = 0; i < riscv::XLEN; i++) begin
|
||||
assign operand_a_rev[i] = operand_a_i[(riscv::XLEN-1)-i];
|
||||
assign operand_b_rev[i] = operand_b_i[(riscv::XLEN-1)-i];
|
||||
for (genvar i = 0; i < CVA6Cfg.XLEN; i++) begin
|
||||
assign operand_a_rev[i] = operand_a_i[(CVA6Cfg.XLEN-1)-i];
|
||||
assign operand_b_rev[i] = operand_b_i[(CVA6Cfg.XLEN-1)-i];
|
||||
end
|
||||
|
||||
// operand_a and operand_b selection
|
||||
|
|
@ -66,14 +66,14 @@ module multiplier
|
|||
// implementation
|
||||
always_comb begin
|
||||
clmul_d = '0;
|
||||
for (int i = 0; i <= riscv::XLEN; i++) begin
|
||||
for (int i = 0; i <= CVA6Cfg.XLEN; i++) begin
|
||||
clmul_d = (|((operand_b >> i) & 1)) ? clmul_d ^ (operand_a << i) : clmul_d;
|
||||
end
|
||||
end
|
||||
|
||||
// clmulr + clmulh result generator
|
||||
for (genvar i = 0; i < riscv::XLEN; i++) begin
|
||||
assign clmulr_d[i] = clmul_d[(riscv::XLEN-1)-i];
|
||||
for (genvar i = 0; i < CVA6Cfg.XLEN; i++) begin
|
||||
assign clmulr_d[i] = clmul_d[(CVA6Cfg.XLEN-1)-i];
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -81,7 +81,7 @@ module multiplier
|
|||
logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_q;
|
||||
logic mult_valid_q;
|
||||
fu_op operator_d, operator_q;
|
||||
logic [riscv::XLEN*2-1:0] mult_result_d, mult_result_q;
|
||||
logic [CVA6Cfg.XLEN*2-1:0] mult_result_d, mult_result_q;
|
||||
|
||||
// control registers
|
||||
logic sign_a, sign_b;
|
||||
|
|
@ -116,9 +116,9 @@ module multiplier
|
|||
|
||||
// single stage version
|
||||
assign mult_result_d = $signed(
|
||||
{operand_a_i[riscv::XLEN-1] & sign_a, operand_a_i}
|
||||
{operand_a_i[CVA6Cfg.XLEN-1] & sign_a, operand_a_i}
|
||||
) * $signed(
|
||||
{operand_b_i[riscv::XLEN-1] & sign_b, operand_b_i}
|
||||
{operand_b_i[CVA6Cfg.XLEN-1] & sign_b, operand_b_i}
|
||||
);
|
||||
|
||||
|
||||
|
|
@ -126,15 +126,14 @@ module multiplier
|
|||
|
||||
always_comb begin : p_selmux
|
||||
unique case (operator_q)
|
||||
MULH, MULHU, MULHSU: result_o = mult_result_q[riscv::XLEN*2-1:riscv::XLEN];
|
||||
MULH, MULHU, MULHSU: result_o = mult_result_q[CVA6Cfg.XLEN*2-1:CVA6Cfg.XLEN];
|
||||
CLMUL: result_o = clmul_q;
|
||||
CLMULH: result_o = clmulr_q >> 1;
|
||||
CLMULR: result_o = clmulr_q;
|
||||
// MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register
|
||||
// MUL performs an CVA6Cfg.XLEN-bit×CVA6Cfg.XLEN-bit multiplication and places the lower CVA6Cfg.XLEN bits in the destination register
|
||||
default: begin
|
||||
if (operator_q == MULW && CVA6Cfg.IS_XLEN64)
|
||||
result_o = sext32(CVA6Cfg, mult_result_q[31:0]);
|
||||
else result_o = mult_result_q[riscv::XLEN-1:0]; // including MUL
|
||||
if (operator_q == MULW && CVA6Cfg.IS_XLEN64) result_o = sext32to64(mult_result_q[31:0]);
|
||||
else result_o = mult_result_q[CVA6Cfg.XLEN-1:0]; // including MUL
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
|
|
|||
|
|
@ -31,8 +31,8 @@ module perf_counters
|
|||
// SRAM like interface
|
||||
input logic [11:0] addr_i, // read/write address (up to 6 counters possible)
|
||||
input logic we_i, // write enable
|
||||
input logic [riscv::XLEN-1:0] data_i, // data to write
|
||||
output logic [riscv::XLEN-1:0] data_o, // data to read
|
||||
input logic [CVA6Cfg.XLEN-1:0] data_i, // data to write
|
||||
output logic [CVA6Cfg.XLEN-1:0] data_o, // data to read
|
||||
// from commit stage
|
||||
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // the instruction we want to commit
|
||||
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // acknowledge that we are indeed committing
|
||||
|
|
@ -160,7 +160,8 @@ module perf_counters
|
|||
riscv::CSR_MHPM_COUNTER_6,
|
||||
riscv::CSR_MHPM_COUNTER_7,
|
||||
riscv::CSR_MHPM_COUNTER_8 :begin
|
||||
if (riscv::XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3+1][31:0];
|
||||
if (CVA6Cfg.XLEN == 32)
|
||||
data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3+1][31:0];
|
||||
else data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3+1];
|
||||
end
|
||||
riscv::CSR_MHPM_COUNTER_3H,
|
||||
|
|
@ -169,7 +170,7 @@ module perf_counters
|
|||
riscv::CSR_MHPM_COUNTER_6H,
|
||||
riscv::CSR_MHPM_COUNTER_7H,
|
||||
riscv::CSR_MHPM_COUNTER_8H :begin
|
||||
if (riscv::XLEN == 32)
|
||||
if (CVA6Cfg.XLEN == 32)
|
||||
data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3H+1][63:32];
|
||||
else read_access_exception = 1'b1;
|
||||
end
|
||||
|
|
@ -186,7 +187,7 @@ module perf_counters
|
|||
riscv::CSR_HPM_COUNTER_6,
|
||||
riscv::CSR_HPM_COUNTER_7,
|
||||
riscv::CSR_HPM_COUNTER_8 :begin
|
||||
if (riscv::XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3+1][31:0];
|
||||
if (CVA6Cfg.XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3+1][31:0];
|
||||
else data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3+1];
|
||||
end
|
||||
riscv::CSR_HPM_COUNTER_3H,
|
||||
|
|
@ -195,7 +196,7 @@ module perf_counters
|
|||
riscv::CSR_HPM_COUNTER_6H,
|
||||
riscv::CSR_HPM_COUNTER_7H,
|
||||
riscv::CSR_HPM_COUNTER_8H :begin
|
||||
if (riscv::XLEN == 32)
|
||||
if (CVA6Cfg.XLEN == 32)
|
||||
data_o = generic_counter_q[addr_i-riscv::CSR_HPM_COUNTER_3H+1][63:32];
|
||||
else read_access_exception = 1'b1;
|
||||
end
|
||||
|
|
@ -211,7 +212,7 @@ module perf_counters
|
|||
riscv::CSR_MHPM_COUNTER_6,
|
||||
riscv::CSR_MHPM_COUNTER_7,
|
||||
riscv::CSR_MHPM_COUNTER_8 :begin
|
||||
if (riscv::XLEN == 32)
|
||||
if (CVA6Cfg.XLEN == 32)
|
||||
generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3+1][31:0] = data_i;
|
||||
else generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3+1] = data_i;
|
||||
end
|
||||
|
|
@ -221,7 +222,7 @@ module perf_counters
|
|||
riscv::CSR_MHPM_COUNTER_6H,
|
||||
riscv::CSR_MHPM_COUNTER_7H,
|
||||
riscv::CSR_MHPM_COUNTER_8H :begin
|
||||
if (riscv::XLEN == 32)
|
||||
if (CVA6Cfg.XLEN == 32)
|
||||
generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3H+1][63:32] = data_i;
|
||||
else update_access_exception = 1'b1;
|
||||
end
|
||||
|
|
|
|||
|
|
@ -39,14 +39,14 @@ module scoreboard #(
|
|||
// rs1 operand address - issue_read_operands
|
||||
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs1_i,
|
||||
// rs1 operand - issue_read_operands
|
||||
output logic [ riscv::XLEN-1:0] rs1_o,
|
||||
output logic [ CVA6Cfg.XLEN-1:0] rs1_o,
|
||||
// rs1 operand is valid - issue_read_operands
|
||||
output logic rs1_valid_o,
|
||||
|
||||
// rs2 operand address - issue_read_operands
|
||||
input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs2_i,
|
||||
// rs2 operand - issue_read_operands
|
||||
output logic [ riscv::XLEN-1:0] rs2_o,
|
||||
output logic [ CVA6Cfg.XLEN-1:0] rs2_o,
|
||||
// rs2 operand is valid - issue_read_operands
|
||||
output logic rs2_valid_o,
|
||||
|
||||
|
|
@ -89,7 +89,7 @@ module scoreboard #(
|
|||
// Transaction ID at which to write the result back - TO_BE_COMPLETED
|
||||
input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_i,
|
||||
// Results to write back - TO_BE_COMPLETED
|
||||
input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i,
|
||||
input logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] wbdata_i,
|
||||
// Exception from a functional unit (e.g.: ld/st exception) - TO_BE_COMPLETED
|
||||
input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i,
|
||||
// Indicates valid results - TO_BE_COMPLETED
|
||||
|
|
@ -331,7 +331,7 @@ module scoreboard #(
|
|||
// ----------------------------------
|
||||
// read operand interface: same logic as register file
|
||||
logic [CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0] rs1_fwd_req, rs2_fwd_req, rs3_fwd_req;
|
||||
logic [CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] rs_data;
|
||||
logic [CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] rs_data;
|
||||
logic rs1_valid, rs2_valid, rs3_valid;
|
||||
|
||||
// WB ports have higher prio than entries
|
||||
|
|
@ -375,7 +375,7 @@ module scoreboard #(
|
|||
// this implicitly gives higher prio to WB ports
|
||||
rr_arb_tree #(
|
||||
.NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts),
|
||||
.DataWidth(riscv::XLEN),
|
||||
.DataWidth(CVA6Cfg.XLEN),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) i_sel_rs1 (
|
||||
|
|
@ -394,7 +394,7 @@ module scoreboard #(
|
|||
|
||||
rr_arb_tree #(
|
||||
.NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts),
|
||||
.DataWidth(riscv::XLEN),
|
||||
.DataWidth(CVA6Cfg.XLEN),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) i_sel_rs2 (
|
||||
|
|
@ -411,11 +411,11 @@ module scoreboard #(
|
|||
.idx_o ()
|
||||
);
|
||||
|
||||
logic [riscv::XLEN-1:0] rs3;
|
||||
logic [CVA6Cfg.XLEN-1:0] rs3;
|
||||
|
||||
rr_arb_tree #(
|
||||
.NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts),
|
||||
.DataWidth(riscv::XLEN),
|
||||
.DataWidth(CVA6Cfg.XLEN),
|
||||
.ExtPrio(1'b1),
|
||||
.AxiVldRdy(1'b1)
|
||||
) i_sel_rs3 (
|
||||
|
|
@ -433,7 +433,7 @@ module scoreboard #(
|
|||
);
|
||||
|
||||
if (CVA6Cfg.NrRgprPorts == 3) begin : gen_gp_three_port
|
||||
assign rs3_o = rs3[riscv::XLEN-1:0];
|
||||
assign rs3_o = rs3[CVA6Cfg.XLEN-1:0];
|
||||
end else begin : gen_fp_three_port
|
||||
assign rs3_o = rs3[CVA6Cfg.FLen-1:0];
|
||||
end
|
||||
|
|
|
|||
|
|
@ -42,8 +42,8 @@ module store_buffer
|
|||
|
||||
input logic [CVA6Cfg.PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue
|
||||
output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o,
|
||||
input logic [riscv::XLEN-1:0] data_i, // data which is placed in the queue
|
||||
input logic [(riscv::XLEN/8)-1:0] be_i, // byte enable in
|
||||
input logic [CVA6Cfg.XLEN-1:0] data_i, // data which is placed in the queue
|
||||
input logic [(CVA6Cfg.XLEN/8)-1:0] be_i, // byte enable in
|
||||
input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write)
|
||||
|
||||
// D$ interface
|
||||
|
|
@ -56,8 +56,8 @@ module store_buffer
|
|||
// 2. Commit queue which is non-speculative, e.g.: the store will definitely happen.
|
||||
struct packed {
|
||||
logic [CVA6Cfg.PLEN-1:0] address;
|
||||
logic [riscv::XLEN-1:0] data;
|
||||
logic [(riscv::XLEN/8)-1:0] be;
|
||||
logic [CVA6Cfg.XLEN-1:0] data;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] be;
|
||||
logic [1:0] data_size;
|
||||
logic valid; // this entry is valid, we need this for checking if the address offset matches
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ module store_unit
|
|||
// Transaction ID - ISSUE_STAGE
|
||||
output logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_o,
|
||||
// Store result - ISSUE_STAGE
|
||||
output logic [riscv::XLEN-1:0] result_o,
|
||||
output logic [CVA6Cfg.XLEN-1:0] result_o,
|
||||
// Store exception output - TO_BE_COMPLETED
|
||||
output exception_t ex_o,
|
||||
// Address translation request - TO_BE_COMPLETED
|
||||
|
|
@ -81,24 +81,24 @@ module store_unit
|
|||
);
|
||||
|
||||
// align data to address e.g.: shift data to be naturally 64
|
||||
function automatic [riscv::XLEN-1:0] data_align(logic [2:0] addr, logic [63:0] data);
|
||||
function automatic [CVA6Cfg.XLEN-1:0] data_align(logic [2:0] addr, logic [63:0] data);
|
||||
// Set addr[2] to 1'b0 when 32bits
|
||||
logic [ 2:0] addr_tmp = {(addr[2] && CVA6Cfg.IS_XLEN64), addr[1:0]};
|
||||
logic [63:0] data_tmp = {64{1'b0}};
|
||||
case (addr_tmp)
|
||||
3'b000: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-1:0]};
|
||||
3'b000: data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-1:0]};
|
||||
3'b001:
|
||||
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-9:0], data[riscv::XLEN-1:riscv::XLEN-8]};
|
||||
data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-9:0], data[CVA6Cfg.XLEN-1:CVA6Cfg.XLEN-8]};
|
||||
3'b010:
|
||||
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-17:0], data[riscv::XLEN-1:riscv::XLEN-16]};
|
||||
data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-17:0], data[CVA6Cfg.XLEN-1:CVA6Cfg.XLEN-16]};
|
||||
3'b011:
|
||||
data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-25:0], data[riscv::XLEN-1:riscv::XLEN-24]};
|
||||
data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-25:0], data[CVA6Cfg.XLEN-1:CVA6Cfg.XLEN-24]};
|
||||
3'b100: data_tmp = {data[31:0], data[63:32]};
|
||||
3'b101: data_tmp = {data[23:0], data[63:24]};
|
||||
3'b110: data_tmp = {data[15:0], data[63:16]};
|
||||
3'b111: data_tmp = {data[7:0], data[63:8]};
|
||||
endcase
|
||||
return data_tmp[riscv::XLEN-1:0];
|
||||
return data_tmp[CVA6Cfg.XLEN-1:0];
|
||||
endfunction
|
||||
|
||||
// it doesn't matter what we are writing back as stores don't return anything
|
||||
|
|
@ -119,8 +119,8 @@ module store_unit
|
|||
logic instr_is_amo;
|
||||
assign instr_is_amo = is_amo(lsu_ctrl_i.operation);
|
||||
// keep the data and the byte enable for the second cycle (after address translation)
|
||||
logic [riscv::XLEN-1:0] st_data_n, st_data_q;
|
||||
logic [(riscv::XLEN/8)-1:0] st_be_n, st_be_q;
|
||||
logic [CVA6Cfg.XLEN-1:0] st_data_n, st_data_q;
|
||||
logic [(CVA6Cfg.XLEN/8)-1:0] st_be_n, st_be_q;
|
||||
logic [1:0] st_data_size_n, st_data_size_q;
|
||||
amo_t amo_op_d, amo_op_q;
|
||||
|
||||
|
|
@ -236,8 +236,8 @@ module store_unit
|
|||
always_comb begin
|
||||
st_be_n = lsu_ctrl_i.be;
|
||||
// don't shift the data if we are going to perform an AMO as we still need to operate on this data
|
||||
st_data_n = (CVA6Cfg.RVA && instr_is_amo) ? lsu_ctrl_i.data[riscv::XLEN-1:0] :
|
||||
data_align(lsu_ctrl_i.vaddr[2:0], {{64 - riscv::XLEN{1'b0}}, lsu_ctrl_i.data});
|
||||
st_data_n = (CVA6Cfg.RVA && instr_is_amo) ? lsu_ctrl_i.data[CVA6Cfg.XLEN-1:0] :
|
||||
data_align(lsu_ctrl_i.vaddr[2:0], {{64 - CVA6Cfg.XLEN{1'b0}}, lsu_ctrl_i.data});
|
||||
st_data_size_n = extract_transfer_size(lsu_ctrl_i.operation);
|
||||
// save AMO op for next cycle
|
||||
if (CVA6Cfg.RVA) begin
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
// constant frequency, and the platform must provide a mechanism for determining the timebase of mtime (device tree).
|
||||
|
||||
module clint #(
|
||||
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
|
||||
parameter int unsigned AXI_ADDR_WIDTH = 64,
|
||||
parameter int unsigned AXI_DATA_WIDTH = 64,
|
||||
parameter int unsigned AXI_ID_WIDTH = 10,
|
||||
|
|
@ -101,7 +102,7 @@ module clint #(
|
|||
end
|
||||
|
||||
[MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin
|
||||
if (riscv::XLEN == 32) begin
|
||||
if (CVA6Cfg.XLEN == 32) begin
|
||||
if (be[3:0] == 4'hf)
|
||||
mtimecmp_n[$unsigned(address[AddrSelWidth-1+3:3])][31:0] = wdata[31:0];
|
||||
else
|
||||
|
|
@ -113,7 +114,7 @@ module clint #(
|
|||
end
|
||||
|
||||
[MTIME_BASE:MTIME_BASE+4]: begin
|
||||
if (riscv::XLEN == 32) begin
|
||||
if (CVA6Cfg.XLEN == 32) begin
|
||||
if (address[2:0] == 3'h0)
|
||||
mtime_n[31:0] = wdata[31:0];
|
||||
else begin
|
||||
|
|
@ -136,14 +137,14 @@ module clint #(
|
|||
if (en && !we) begin
|
||||
case (register_address) inside
|
||||
[MSIP_BASE:MSIP_BASE+4*NR_CORES]: begin
|
||||
if (riscv::XLEN == 32)
|
||||
if (CVA6Cfg.XLEN == 32)
|
||||
rdata[31:0] = msip_q[$unsigned(address[AddrSelWidth-1+2:2])];
|
||||
else
|
||||
rdata = msip_q[$unsigned(address[AddrSelWidth-1+2:2])];
|
||||
end
|
||||
|
||||
[MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin
|
||||
if (riscv::XLEN == 32) begin
|
||||
if (CVA6Cfg.XLEN == 32) begin
|
||||
if (address[2:0] == 3'h0)
|
||||
rdata[31:0] = mtimecmp_q[$unsigned(address[AddrSelWidth-1+3:3])][31:0];
|
||||
else begin
|
||||
|
|
@ -157,7 +158,7 @@ module clint #(
|
|||
end
|
||||
|
||||
[MTIME_BASE:MTIME_BASE+4]: begin
|
||||
if (riscv::XLEN == 32) begin
|
||||
if (CVA6Cfg.XLEN == 32) begin
|
||||
if (address[2:0] == 3'h0)
|
||||
rdata[31:0] = mtime_q[31:0];
|
||||
else begin
|
||||
|
|
|
|||
|
|
@ -205,8 +205,8 @@ AXI_BUS #(
|
|||
) master[ariane_soc::NB_PERIPHERALS-1:0]();
|
||||
|
||||
AXI_BUS #(
|
||||
.AXI_ADDR_WIDTH ( riscv::XLEN ),
|
||||
.AXI_DATA_WIDTH ( riscv::XLEN ),
|
||||
.AXI_ADDR_WIDTH ( CVA6Cfg.XLEN ),
|
||||
.AXI_DATA_WIDTH ( CVA6Cfg.XLEN ),
|
||||
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
|
||||
.AXI_USER_WIDTH ( AxiUserWidth )
|
||||
) master_to_dm[0:0]();
|
||||
|
|
@ -356,24 +356,24 @@ ariane_axi::resp_t dm_axi_m_resp;
|
|||
|
||||
logic dm_slave_req;
|
||||
logic dm_slave_we;
|
||||
logic [riscv::XLEN-1:0] dm_slave_addr;
|
||||
logic [riscv::XLEN/8-1:0] dm_slave_be;
|
||||
logic [riscv::XLEN-1:0] dm_slave_wdata;
|
||||
logic [riscv::XLEN-1:0] dm_slave_rdata;
|
||||
logic [CVA6Cfg.XLEN-1:0] dm_slave_addr;
|
||||
logic [CVA6Cfg.XLEN/8-1:0] dm_slave_be;
|
||||
logic [CVA6Cfg.XLEN-1:0] dm_slave_wdata;
|
||||
logic [CVA6Cfg.XLEN-1:0] dm_slave_rdata;
|
||||
|
||||
logic dm_master_req;
|
||||
logic [riscv::XLEN-1:0] dm_master_add;
|
||||
logic [CVA6Cfg.XLEN-1:0] dm_master_add;
|
||||
logic dm_master_we;
|
||||
logic [riscv::XLEN-1:0] dm_master_wdata;
|
||||
logic [riscv::XLEN/8-1:0] dm_master_be;
|
||||
logic [CVA6Cfg.XLEN-1:0] dm_master_wdata;
|
||||
logic [CVA6Cfg.XLEN/8-1:0] dm_master_be;
|
||||
logic dm_master_gnt;
|
||||
logic dm_master_r_valid;
|
||||
logic [riscv::XLEN-1:0] dm_master_r_rdata;
|
||||
logic [CVA6Cfg.XLEN-1:0] dm_master_r_rdata;
|
||||
|
||||
// debug module
|
||||
dm_top #(
|
||||
.NrHarts ( 1 ),
|
||||
.BusWidth ( riscv::XLEN ),
|
||||
.BusWidth ( CVA6Cfg.XLEN ),
|
||||
.SelectableHarts ( 1'b1 )
|
||||
) i_dm_top (
|
||||
.clk_i ( clk ),
|
||||
|
|
@ -409,8 +409,8 @@ dm_top #(
|
|||
|
||||
axi2mem #(
|
||||
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
|
||||
.AXI_ADDR_WIDTH ( riscv::XLEN ),
|
||||
.AXI_DATA_WIDTH ( riscv::XLEN ),
|
||||
.AXI_ADDR_WIDTH ( CVA6Cfg.XLEN ),
|
||||
.AXI_DATA_WIDTH ( CVA6Cfg.XLEN ),
|
||||
.AXI_USER_WIDTH ( AxiUserWidth )
|
||||
) i_dm_axi2mem (
|
||||
.clk_i ( clk ),
|
||||
|
|
@ -424,7 +424,7 @@ axi2mem #(
|
|||
.data_i ( dm_slave_rdata )
|
||||
);
|
||||
|
||||
if (riscv::XLEN==32 ) begin
|
||||
if (CVA6Cfg.XLEN==32 ) begin
|
||||
|
||||
assign master_to_dm[0].aw_user = '0;
|
||||
assign master_to_dm[0].w_user = '0;
|
||||
|
|
@ -578,11 +578,11 @@ end
|
|||
|
||||
logic [1:0] axi_adapter_size;
|
||||
|
||||
assign axi_adapter_size = (riscv::XLEN == 64) ? 2'b11 : 2'b10;
|
||||
assign axi_adapter_size = (CVA6Cfg.XLEN == 64) ? 2'b11 : 2'b10;
|
||||
|
||||
axi_adapter #(
|
||||
.CVA6Cfg ( CVA6Cfg ),
|
||||
.DATA_WIDTH ( riscv::XLEN ),
|
||||
.DATA_WIDTH ( CVA6Cfg.XLEN ),
|
||||
.axi_req_t ( ariane_axi::req_t ),
|
||||
.axi_rsp_t ( ariane_axi::resp_t )
|
||||
) i_dm_axi_master (
|
||||
|
|
@ -607,7 +607,7 @@ axi_adapter #(
|
|||
.axi_resp_i ( dm_axi_m_resp )
|
||||
);
|
||||
|
||||
if (riscv::XLEN==32 ) begin
|
||||
if (CVA6Cfg.XLEN==32 ) begin
|
||||
logic [31 : 0] dm_master_m_awaddr;
|
||||
logic [31 : 0] dm_master_m_araddr;
|
||||
|
||||
|
|
@ -754,6 +754,7 @@ axi_slave_req_t axi_clint_req;
|
|||
axi_slave_resp_t axi_clint_resp;
|
||||
|
||||
clint #(
|
||||
.CVA6Cfg ( CVA6Cfg ),
|
||||
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
|
||||
.AXI_DATA_WIDTH ( AxiDataWidth ),
|
||||
.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
|
||||
|
|
@ -794,7 +795,7 @@ axi2mem #(
|
|||
.data_i ( rom_rdata )
|
||||
);
|
||||
|
||||
if (riscv::XLEN==32 ) begin
|
||||
if (CVA6Cfg.XLEN==32 ) begin
|
||||
bootrom_32 i_bootrom (
|
||||
.clk_i ( clk ),
|
||||
.req_i ( rom_req ),
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ module ariane import ariane_pkg::*; #(
|
|||
input logic rst_ni,
|
||||
// Core ID, Cluster ID and boot address are considered more or less static
|
||||
input logic [CVA6Cfg.VLEN-1:0] boot_addr_i, // reset boot address
|
||||
input logic [riscv::XLEN-1:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR)
|
||||
input logic [CVA6Cfg.XLEN-1:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR)
|
||||
|
||||
// Interrupt inputs
|
||||
input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async)
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ module ariane_testharness #(
|
|||
initial begin
|
||||
if (!$value$plusargs("jtag_rbb_enable=%b", jtag_enable)) jtag_enable = 'h0;
|
||||
if ($test$plusargs("debug_disable")) debug_enable = 'h0; else debug_enable = 'h1;
|
||||
if (riscv::XLEN != 32 & riscv::XLEN != 64) $error("XLEN different from 32 and 64");
|
||||
if (CVA6Cfg.XLEN != 32 & CVA6Cfg.XLEN != 64) $error("CVA6Cfg.XLEN different from 32 and 64");
|
||||
end
|
||||
|
||||
// debug if MUX
|
||||
|
|
@ -540,6 +540,7 @@ module ariane_testharness #(
|
|||
ariane_axi_soc::resp_slv_t axi_clint_resp;
|
||||
|
||||
clint #(
|
||||
.CVA6Cfg ( CVA6Cfg ),
|
||||
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
|
||||
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
|
||||
.AXI_ID_WIDTH ( ariane_axi_soc::IdWidthSlave ),
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ module rvfi_tracer #(
|
|||
always_ff @(posedge clk_i) begin
|
||||
end_of_test_q = (rst_ni && (end_of_test_d[0] == 1'b1)) ? end_of_test_d : 0;
|
||||
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
|
||||
pc64 = {{riscv::XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
|
||||
pc64 = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
|
||||
// print the instruction information if the instruction is valid or a trap is taken
|
||||
if (rvfi_i[i].valid) begin
|
||||
// Instruction information
|
||||
|
|
@ -73,8 +73,8 @@ module rvfi_tracer #(
|
|||
(rvfi_i[i].insn[6:0] == 7'b1010011 && rvfi_i[i].insn[31:26] != 6'b111000
|
||||
&& rvfi_i[i].insn[31:26] != 6'b101000
|
||||
&& rvfi_i[i].insn[31:26] != 6'b110000) ||
|
||||
(rvfi_i[i].insn[0] == 1'b0 && ((rvfi_i[i].insn[15:13] == 3'b001 && riscv::XLEN == 64) ||
|
||||
(rvfi_i[i].insn[15:13] == 3'b011 && riscv::XLEN == 32) ))) begin
|
||||
(rvfi_i[i].insn[0] == 1'b0 && ((rvfi_i[i].insn[15:13] == 3'b001 && CVA6Cfg.XLEN == 64) ||
|
||||
(rvfi_i[i].insn[15:13] == 3'b011 && CVA6Cfg.XLEN == 32) ))) begin
|
||||
$fwrite(f, " f%d 0x%h", rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata);
|
||||
end else if (rvfi_i[i].rd_addr != 0) begin
|
||||
$fwrite(f, " x%d 0x%h", rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata);
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #(
|
|||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic [XLEN-1:0] boot_addr_i,
|
||||
input logic [CVA6Cfg.XLEN-1:0] boot_addr_i,
|
||||
output logic [31:0] tb_exit_o,
|
||||
output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o,
|
||||
output rvfi_csr_t rvfi_csr_o,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue