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Added debug address filter to ariane_verilog_wrap.sv

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Michael Schaffner 2018-11-28 22:52:54 +01:00
parent 89a0f6b5f6
commit bdec1f695d
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1 changed files with 15 additions and 2 deletions
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17
openpiton/ariane_verilog_wrap.sv
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@ -57,10 +57,17 @@ module ariane_verilog_wrap #(
assign axi_resp = axi_resp_i;
`else
// L15 (memory side)
serpent_cache_pkg::l15_req_t l15_req;
serpent_cache_pkg::l15_req_t l15_req, l15_req_remapped;
serpent_cache_pkg::l15_rtrn_t l15_rtrn;
assign l15_req_o = l15_req;
always_comb begin : p_remap
l15_req_remapped = l15_req;
if (l15_req.l15_address < 64'h1000) begin
l15_req_remapped.l15_address = l15_req.l15_address + 64'hfff1000000;
end
end
assign l15_req_o = l15_req_remapped;
assign l15_rtrn = l15_rtrn_i;
`endif
@ -87,6 +94,12 @@ module ariane_verilog_wrap #(
// 128KB..8K cycles
// 256KB..16K cycles
// etc, so this should be enough for 512k per tile
// assign wake_up_cnt_d = (wake_up_cnt_q[$high(wake_up_cnt_q)]) ? wake_up_cnt_q :
// (((l15_rtrn.l15_returntype == serpent_cache_pkg::L15_INT_RET) && l15_rtrn.l15_val) || wake_up_cnt_q>0) ? wake_up_cnt_q +1:
// wake_up_cnt_q;
logic [15:0] wake_up_cnt_d, wake_up_cnt_q;
logic rst_n;