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Use stream_arbiter and fix write ordering
This commit is contained in:
Florian Zaruba
parent
6381b3d3ee
commit
be0b4cd440
2 changed files with 58 additions and 95 deletions
1
Makefile
1
Makefile
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@ -100,6 +100,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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src/common_cells/src/rstgen.sv \
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src/common_cells/src/stream_mux.sv \
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src/common_cells/src/stream_demux.sv \
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src/common_cells/src/stream_arbiter.sv \
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src/util/axi_master_connect.sv \
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src/util/axi_slave_connect.sv \
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src/util/axi_master_connect_rev.sv \
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@ -101,81 +101,70 @@ module std_cache_subsystem #(
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// -----------------------
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// Arbitrate AXI Ports
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// -----------------------
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logic [1:0] aw_select, ar_select, w_select;
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logic aw_arbiter_valid, ar_arbiter_valid, w_arbiter_valid;
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logic aw_enable_d, aw_enable_q;
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logic ar_enable_d, ar_enable_q;
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logic w_enable_d, w_enable_q;
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// AW Channel
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rrarbiter #(
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.NUM_REQ ( 3 ),
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.LOCK_IN ( 1 )
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) i_rrarbiter_aw (
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.clk_i,
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.rst_ni,
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.flush_i ( 1'b0 ),
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.en_i ( aw_enable_q ),
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.req_i ( {axi_req_icache.aw_valid, axi_req_bypass.aw_valid, axi_req_data.aw_valid} ),
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.ack_o ( ),
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.vld_o ( aw_arbiter_valid ),
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.idx_o ( aw_select )
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);
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stream_mux #(
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.DATA_T ( ariane_axi::aw_chan_t ),
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.N_INP ( 3 )
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) i_stream_mux_aw (
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.inp_data_i ( {axi_req_icache.aw, axi_req_bypass.aw, axi_req_data.aw} ),
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.inp_valid_i ( {axi_req_icache.aw_valid, axi_req_bypass.aw_valid, axi_req_data.aw_valid} ),
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.inp_ready_o ( {axi_resp_icache.aw_ready, axi_resp_bypass.aw_ready, axi_resp_data.aw_ready} ),
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.inp_sel_i ( aw_select ),
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.oup_data_o ( axi_req_o.aw ),
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.oup_valid_o ( axi_req_o.aw_valid ),
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.oup_ready_i ( axi_resp_i.aw_ready )
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);
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logic [1:0] w_select, w_id;
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logic full;
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// AR Channel
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rrarbiter #(
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.NUM_REQ ( 3 ),
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.LOCK_IN ( 1 )
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) i_rrarbiter_ar (
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.clk_i,
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.rst_ni,
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.flush_i ( 1'b0 ),
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.en_i ( ar_enable_q ),
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.req_i ( {axi_req_icache.ar_valid, axi_req_bypass.ar_valid, axi_req_data.ar_valid} ),
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.ack_o ( ),
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.vld_o ( ar_arbiter_valid ),
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.idx_o ( ar_select )
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);
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stream_mux #(
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stream_arbiter #(
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.DATA_T ( ariane_axi::ar_chan_t ),
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.N_INP ( 3 )
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) i_stream_mux_ar (
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) i_stream_arbiter_ar (
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.clk_i,
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.rst_ni,
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.inp_data_i ( {axi_req_icache.ar, axi_req_bypass.ar, axi_req_data.ar} ),
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.inp_valid_i ( {axi_req_icache.ar_valid, axi_req_bypass.ar_valid, axi_req_data.ar_valid} ),
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.inp_ready_o ( {axi_resp_icache.ar_ready, axi_resp_bypass.ar_ready, axi_resp_data.ar_ready} ),
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.inp_sel_i ( ar_select ),
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.oup_data_o ( axi_req_o.ar ),
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.oup_valid_o ( axi_req_o.ar_valid ),
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.oup_ready_i ( axi_resp_i.ar_ready )
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);
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// W Channel
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rrarbiter #(
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.NUM_REQ ( 3 ),
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.LOCK_IN ( 1 )
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) i_rrarbiter_w (
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// AW Channel
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stream_arbiter #(
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.DATA_T ( ariane_axi::aw_chan_t ),
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.N_INP ( 3 )
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) i_stream_arbiter_aw (
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.clk_i,
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.rst_ni,
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.flush_i ( 1'b0 ),
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.en_i ( w_enable_q ),
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.req_i ( {axi_req_icache.w_valid, axi_req_bypass.w_valid, axi_req_data.w_valid} ),
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.ack_o ( ),
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.vld_o ( w_arbiter_valid ),
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.idx_o ( w_select )
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.inp_data_i ( {axi_req_icache.aw, axi_req_bypass.aw, axi_req_data.aw} ),
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.inp_valid_i ( {axi_req_icache.aw_valid & ~full, axi_req_bypass.aw_valid & ~full, axi_req_data.aw_valid & ~full} ),
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.inp_ready_o ( {axi_resp_icache.aw_ready, axi_resp_bypass.aw_ready, axi_resp_data.aw_ready} ),
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.oup_data_o ( axi_req_o.aw ),
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.oup_valid_o ( axi_req_o.aw_valid ),
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.oup_ready_i ( axi_resp_i.aw_ready )
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);
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// WID has been removed in AXI 4 so we need to keep track which AW request has been accepted
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// to forward the correct write data.
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always_comb begin
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w_select = 0;
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unique case (axi_req_o.aw.id)
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4'b1111: w_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: w_select = 1; // bypass
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4'b0000: w_select = 2; // icache
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default: w_select = 0;
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endcase
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end
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fifo_v3 #(
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.FALL_THROUGH ( 1'b1 ),
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.DATA_WIDTH ( 2 ),
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.DEPTH ( 4 )
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) i_fifo_w_channel (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( 1'b0 ),
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.testmode_i ( 1'b0 ),
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.full_o ( full ),
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.empty_o ( ), // leave open
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.usage_o ( ), // leave open
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.data_i ( w_select ),
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// a new transaction was requested
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.push_i ( axi_req_o.aw_valid & axi_resp_i.aw_ready & ~full ),
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// write ID to select the output MUX
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.data_o ( w_id ),
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// transaction has finished
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.pop_i ( axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last )
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);
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stream_mux #(
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@ -185,39 +174,12 @@ module std_cache_subsystem #(
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.inp_data_i ( {axi_req_icache.w, axi_req_bypass.w, axi_req_data.w} ),
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.inp_valid_i ( {axi_req_icache.w_valid, axi_req_bypass.w_valid, axi_req_data.w_valid} ),
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.inp_ready_o ( {axi_resp_icache.w_ready, axi_resp_bypass.w_ready, axi_resp_data.w_ready} ),
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.inp_sel_i ( w_select ),
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.inp_sel_i ( w_id ),
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.oup_data_o ( axi_req_o.w ),
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.oup_valid_o ( axi_req_o.w_valid ),
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.oup_ready_i ( axi_resp_i.w_ready )
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);
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always_comb begin
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aw_enable_d = aw_enable_q;
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ar_enable_d = ar_enable_q;
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w_enable_d = w_enable_q;
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// freeze the arbiter
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if (aw_arbiter_valid) aw_enable_d = 1'b0;
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if (ar_arbiter_valid) ar_enable_d = 1'b0;
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if (w_arbiter_valid) w_enable_d = 1'b0;
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// we've got a valid transaction, free the arbitration decision
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if (axi_resp_i.aw_ready && axi_req_o.aw_valid) aw_enable_d = 1'b1;
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if (axi_resp_i.ar_ready && axi_req_o.ar_valid) ar_enable_d = 1'b1;
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if (axi_resp_i.w_ready && axi_req_o.w_valid) w_enable_d = 1'b1;
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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aw_enable_q <= 1'b1;
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ar_enable_q <= 1'b1;
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w_enable_q <= 1'b1;
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end else begin
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aw_enable_q <= aw_enable_d;
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ar_enable_q <= ar_enable_d;
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w_enable_q <= w_enable_d;
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end
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end
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// Route responses based on ID
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// 0000 -> I$
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// 10[00|10|01|11] -> Bypass
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@ -232,10 +194,10 @@ module std_cache_subsystem #(
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always_comb begin
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r_select = 0;
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unique case (axi_resp_i.r.id)
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4'b0000: r_select = 2; // icache
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4'b1111: r_select = 0; // dcache
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4'b1111: r_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: r_select = 1; // bypass
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default: r_select = 0;
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4'b0000: r_select = 2; // icache
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default: r_select = 0;
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endcase
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end
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@ -259,10 +221,10 @@ module std_cache_subsystem #(
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always_comb begin
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b_select = 0;
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unique case (axi_resp_i.b.id)
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4'b0000: b_select = 2; // icache
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4'b1111: b_select = 0; // dcache
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4'b1111: b_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: b_select = 1; // bypass
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default: b_select = 0;
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4'b0000: b_select = 2; // icache
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default: b_select = 0;
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endcase
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end
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