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Add config PipelineOnly (no cache) and OBIVersion, 0 means not compliant -> best perf

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Yannick Casamatta 2024-11-15 17:24:30 +01:00 • committed by JeanRochCoulon
parent 24cd6e23b0
commit be3b8fc0d4
18 changed files with 101 additions and 18 deletions
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44
core/include/build_config_pkg.sv
View file

@ -30,7 +30,7 @@ package build_config_pkg;
int unsigned PtLevels = (CVA6Cfg.XLEN == 64) ? 3 : 2;
config_pkg::cva6_cfg_t cfg;
cfg.ObiVersion = 1; //FIXME CVA6Cfg.ObiVersion; //0 not compliant
cfg.XLEN = CVA6Cfg.XLEN;
cfg.VLEN = CVA6Cfg.VLEN;
cfg.PLEN = (CVA6Cfg.XLEN == 32) ? 34 : 56;
@ -57,7 +57,7 @@ package build_config_pkg;
cfg.AxiIdWidth = CVA6Cfg.AxiIdWidth;
cfg.AxiUserWidth = CVA6Cfg.AxiUserWidth;
cfg.MEM_TID_WIDTH = CVA6Cfg.MemTidWidth;
cfg.NrLoadBufEntries = CVA6Cfg.NrLoadBufEntries;
cfg.NrLoadBufEntries = CVA6Cfg.NrLoadBufEntries; //cfg.ObiVersion == 0 ? CVA6Cfg.NrLoadBufEntries : 1;
cfg.RVF = CVA6Cfg.RVF;
cfg.RVD = CVA6Cfg.RVD;
cfg.XF16 = CVA6Cfg.XF16;
@ -188,6 +188,46 @@ package build_config_pkg;
cfg.X_DUALWRITE = 0;
cfg.X_ISSUE_REGISTER_SPLIT = 0;
cfg.IdWidth = cfg.AxiIdWidth; //to be changed
cfg.ObiFetchbusCfg.UseRReady = 1'b1;
cfg.ObiFetchbusCfg.CombGnt = 1'b0;
cfg.ObiFetchbusCfg.AddrWidth = cfg.PLEN;
cfg.ObiFetchbusCfg.DataWidth = cfg.FETCH_WIDTH;
cfg.ObiFetchbusCfg.IdWidth = cfg.IdWidth;
cfg.ObiFetchbusCfg.Integrity = 1'b0;
cfg.ObiFetchbusCfg.BeFull = 1'b1;
cfg.ObiFetchbusCfg.OptionalCfg.UseAtop = 1'b1;
cfg.ObiFetchbusCfg.OptionalCfg.UseMemtype = 1'b1;
cfg.ObiFetchbusCfg.OptionalCfg.UseProt = 1'b1;
cfg.ObiFetchbusCfg.OptionalCfg.UseDbg = 1'b1;
cfg.ObiFetchbusCfg.OptionalCfg.AUserWidth = 1;
cfg.ObiFetchbusCfg.OptionalCfg.WUserWidth = cfg.FETCH_USER_WIDTH;
cfg.ObiFetchbusCfg.OptionalCfg.RUserWidth = cfg.FETCH_USER_WIDTH;
cfg.ObiFetchbusCfg.OptionalCfg.MidWidth = 1;
cfg.ObiFetchbusCfg.OptionalCfg.AChkWidth = 1;
cfg.ObiFetchbusCfg.OptionalCfg.RChkWidth = 1;
cfg.ObiDatabusCfg.UseRReady = 1'b1;
cfg.ObiDatabusCfg.CombGnt = 1'b0;
cfg.ObiDatabusCfg.AddrWidth = cfg.PLEN;
cfg.ObiDatabusCfg.DataWidth = cfg.XLEN;
cfg.ObiDatabusCfg.IdWidth = cfg.IdWidth;
cfg.ObiDatabusCfg.Integrity = 1'b0;
cfg.ObiDatabusCfg.BeFull = 1'b1;
cfg.ObiDatabusCfg.OptionalCfg.UseAtop = 1'b1;
cfg.ObiDatabusCfg.OptionalCfg.UseMemtype = 1'b1;
cfg.ObiDatabusCfg.OptionalCfg.UseProt = 1'b1;
cfg.ObiDatabusCfg.OptionalCfg.UseDbg = 1'b1;
cfg.ObiDatabusCfg.OptionalCfg.AUserWidth = 1;
cfg.ObiDatabusCfg.OptionalCfg.WUserWidth = cfg.DCACHE_USER_WIDTH;
cfg.ObiDatabusCfg.OptionalCfg.RUserWidth = cfg.DCACHE_USER_WIDTH;
cfg.ObiDatabusCfg.OptionalCfg.MidWidth = 1;
cfg.ObiDatabusCfg.OptionalCfg.AChkWidth = 1;
cfg.ObiDatabusCfg.OptionalCfg.RChkWidth = 1;
cfg.PipelineOnly = CVA6Cfg.PipelineOnly;
return cfg;
endfunction

11
core/include/config_pkg.sv
View file

@ -224,6 +224,10 @@ package config_pkg;
bit unsigned UseSharedTlb;
// MMU depth of shared TLB
int unsigned SharedTlbDepth;
// OBI version compliance, 0 mean non compliant --> best performance
int unsigned ObiVersion;
// Configuration defines cva6_pipeline module as top instead of cva6 (no cache and OBI instead of AXI)
bit PipelineOnly;
} cva6_user_cfg_t;
typedef struct packed {
@ -383,6 +387,13 @@ package config_pkg;
int unsigned X_DUALWRITE;
int unsigned X_ISSUE_REGISTER_SPLIT;
int unsigned IdWidth;
int unsigned ObiVersion;
obi_pkg::obi_cfg_t ObiFetchbusCfg;
obi_pkg::obi_cfg_t ObiDatabusCfg;
bit PipelineOnly;
} cva6_cfg_t;
/// Empty configuration to sanity check proper parameter passing. Whenever

4
core/include/cv32a60x_config_pkg.sv
View file

@ -103,7 +103,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(0),
NrStorePipeRegs: int'(0),
DcacheIdWidth: int'(1)
DcacheIdWidth: int'(1),
ObiVersion: int'(1),
PipelineOnly: bit'(0) //FIXME
};
endpackage

4
core/include/cv32a65x_config_pkg.sv
View file

@ -103,7 +103,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(0),
NrStorePipeRegs: int'(0),
DcacheIdWidth: int'(1)
DcacheIdWidth: int'(1),
ObiVersion: int'(1),
PipelineOnly: bit'(0) //FIXME
};
endpackage

4
core/include/cv32a6_embedded_config_pkg_deprecated.sv
View file

@ -157,7 +157,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file

@ -155,7 +155,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv32a6_imac_sv0_config_pkg.sv
View file

@ -155,6 +155,8 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -154,7 +154,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv32a6_imafc_sv32_config_pkg.sv
View file

@ -155,7 +155,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
View file

@ -158,7 +158,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file

@ -158,7 +158,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
View file

@ -165,7 +165,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file

@ -158,7 +158,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
View file

@ -158,7 +158,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_imafdch_sv39_config_pkg.sv
View file

@ -158,7 +158,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
View file

@ -158,7 +158,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file

@ -158,6 +158,8 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage

4
core/include/cv64a6_mmu_config_pkg.sv
View file

@ -110,7 +110,9 @@ package cva6_config_pkg;
SharedTlbDepth: int'(64),
NrLoadPipeRegs: int'(0),
NrStorePipeRegs: int'(0),
DcacheIdWidth: int'(1)
DcacheIdWidth: int'(1),
ObiVersion: int'(1),
PipelineOnly: bit'(0)
};
endpackage