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Merge pull request #2112 from ThalesSiliconSecurity/test

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ISACOV: add x7 (t2) register in load hazard test
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André Sintzoff 2023-08-09 14:18:30 +02:00 • committed by GitHub
commit bfd77a2b1c
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10
cva6/tests/custom/isacov/load_reg_hazard.S
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@ -20,6 +20,7 @@ main:
li tp, 0x80000000
li t0, 0x80000000
li t1, 0x80000000
li t2, 0x80000000
li s0, 0x80000000
li s1, 0x80000000
li a0, 0x80000000
@ -51,6 +52,7 @@ main:
lw tp, 52(tp)
lw t0, 52(t0)
lw t1, 52(t1)
lw t2, 52(t2)
lw s0, 1024(s0)
lw s1, 1024(s1)
lw a0, 1024(a0)
@ -81,6 +83,7 @@ main:
li tp, 0x80000000
li t0, 0x80000000
li t1, 0x80000000
li t2, 0x80000000
li s0, 0x80000000
li s1, 0x80000000
li a0, 0x80000000
@ -112,6 +115,7 @@ main:
lh tp, 52(tp)
lh t0, 52(t0)
lh t1, 52(t1)
lh t2, 52(t2)
lh s0, 1024(s0)
lh s1, 1024(s1)
lh a0, 1024(a0)
@ -142,6 +146,7 @@ main:
li tp, 0x80000000
li t0, 0x80000000
li t1, 0x80000000
li t2, 0x80000000
li s0, 0x80000000
li s1, 0x80000000
li a0, 0x80000000
@ -173,6 +178,7 @@ main:
lb tp, 52(tp)
lb t0, 52(t0)
lb t1, 52(t1)
lb t2, 52(t2)
lb s0, 1024(s0)
lb s1, 1024(s1)
lb a0, 1024(a0)
@ -203,6 +209,7 @@ main:
li tp, 0x80000000
li t0, 0x80000000
li t1, 0x80000000
li t2, 0x80000000
li s0, 0x80000000
li s1, 0x80000000
li a0, 0x80000000
@ -234,6 +241,7 @@ main:
lbu tp, 52(tp)
lbu t0, 52(t0)
lbu t1, 52(t1)
lbu t2, 52(t2)
lbu s0, 1024(s0)
lbu s1, 1024(s1)
lbu a0, 1024(a0)
@ -264,6 +272,7 @@ main:
li tp, 0x80000000
li t0, 0x80000000
li t1, 0x80000000
li t2, 0x80000000
li s0, 0x80000000
li s1, 0x80000000
li a0, 0x80000000
@ -295,6 +304,7 @@ main:
lhu tp, 52(tp)
lhu t0, 52(t0)
lhu t1, 52(t1)
lhu t2, 52(t2)
lhu s0, 1024(s0)
lhu s1, 1024(s1)
lhu a0, 1024(a0)