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Add missing PITON_ARIANE in wt_cache_subsystem

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Michael Schaffner 2019-03-18 14:24:51 +01:00
parent 48be94f822
commit c1d5004dfa
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1 changed files with 9 additions and 1 deletions
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10
src/cache_subsystem/wt_cache_subsystem.sv
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@ -75,7 +75,11 @@ wt_cache_pkg::dcache_req_t dcache_adapter;
wt_cache_pkg::dcache_rtrn_t adapter_dcache;
wt_icache #(
`ifdef PITON_ARIANE
.Axi64BitCompliant ( 1'b0 ),
`else
.Axi64BitCompliant ( 1'b1 ),
`endif
// use ID 0 for icache reads
.RdTxId ( 0 ),
.CachedAddrBeg ( CachedAddrBeg ),
@ -103,7 +107,11 @@ wt_icache #(
// they have equal prio and are RR arbited
// Port 2 is write only and goes into the merging write buffer
wt_dcache #(
.Axi64BitCompliant ( 1'b1 ),
`ifdef PITON_ARIANE
.Axi64BitCompliant ( 1'b0 ),
`else
.Axi64BitCompliant ( 1'b1 ),
`endif
// use ID 1 for dcache reads and amos. note that the writebuffer
// uses all IDs up to DCACHE_MAX_TX-1 for write transactions.
.RdAmoTxId ( 1 ),