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Declare rvfi package as common lib (#1179)

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Merge this PR. The Thales CI will be failed before updating core-v-verif with corresponding modification.
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JeanRochCoulon 2023-04-11 20:16:10 +02:00 • committed by GitHub
parent ee1560fa38
commit c1df1da568
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9 changed files with 9 additions and 54 deletions
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1
Makefile
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@ -95,7 +95,6 @@ endif
# Package files -> compile first
ariane_pkg := \
corev_apu/register_interface/src/reg_intf.sv \
corev_apu/tb/rvfi_pkg.sv \
corev_apu/tb/ariane_soc_pkg.sv \
corev_apu/riscv-dbg/src/dm_pkg.sv \
corev_apu/tb/ariane_axi_soc_pkg.sv

0
corev_apu/tb/rvfi_pkg.sv → common/local/rvfi/rvfi_pkg.sv
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2
core/Flist.cva6
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@ -36,11 +36,11 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv
${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/common/local/rvfi/rvfi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv

2
core/Flist.cva6_gate
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@ -10,11 +10,11 @@
${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/common/local/rvfi/rvfi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv

8
core/cva6.sv
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@ -48,7 +48,7 @@ module cva6 import ariane_pkg::*; #(
input logic debug_req_i, // debug request (async)
// RISC-V formal interface port (`rvfi`):
// Can be left open when formal tracing is not needed.
output ariane_rvfi_pkg::rvfi_port_t rvfi_o,
output ariane_pkg::rvfi_port_t rvfi_o,
output cvxif_pkg::cvxif_req_t cvxif_req_o,
input cvxif_pkg::cvxif_resp_t cvxif_resp_i,
// L15 (memory side)
@ -628,7 +628,7 @@ module cva6 import ariane_pkg::*; #(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.debug_mode_i ( debug_mode ),
.addr_i ( addr_csr_perf ),
.addr_i ( addr_csr_perf ),
.we_i ( we_csr_perf ),
.data_i ( data_csr_perf ),
.data_o ( data_perf_csr ),
@ -647,8 +647,8 @@ module cva6 import ariane_pkg::*; #(
.branch_exceptions_i ( flu_exception_ex_id ),
.l1_icache_access_i ( icache_dreq_if_cache ),
.l1_dcache_access_i ( dcache_req_ports_ex_cache ),
.miss_vld_bits_i ( miss_vld_bits ),
.i_tlb_flush_i ( flush_tlb_ctrl_ex ),
.miss_vld_bits_i ( miss_vld_bits ),
.i_tlb_flush_i ( flush_tlb_ctrl_ex ),
.stall_issue_i ( stall_issue )
);
end

1
core/include/ariane_pkg.sv
View file

@ -664,6 +664,7 @@ package ariane_pkg;
// ---------------
localparam RVFI = cva6_config_pkg::CVA6ConfigRvfiTrace;
typedef rvfi_pkg::rvfi_instr_t [NR_COMMIT_PORTS-1:0] rvfi_port_t;
typedef struct packed {
logic [riscv::VLEN-1:0] pc; // PC of instruction

45
core/include/ariane_rvfi_pkg.sv
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@ -1,45 +0,0 @@
// Copyright 2020 Thales DIS design services SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Jean-Roch COULON - Thales
package ariane_rvfi_pkg;
localparam NRET = 1;
localparam ILEN = 32;
typedef struct packed {
logic [NRET-1:0] valid;
logic [NRET*64-1:0] order;
logic [NRET*ILEN-1:0] insn;
logic [NRET-1:0] trap;
logic [NRET*riscv::XLEN-1:0] cause;
logic [NRET-1:0] halt;
logic [NRET-1:0] intr;
logic [NRET*2-1:0] mode;
logic [NRET*2-1:0] ixl;
logic [NRET*5-1:0] rs1_addr;
logic [NRET*5-1:0] rs2_addr;
logic [NRET*riscv::XLEN-1:0] rs1_rdata;
logic [NRET*riscv::XLEN-1:0] rs2_rdata;
logic [NRET*5-1:0] rd_addr;
logic [NRET*riscv::XLEN-1:0] rd_wdata;
logic [NRET*riscv::XLEN-1:0] pc_rdata;
logic [NRET*riscv::XLEN-1:0] pc_wdata;
logic [NRET*riscv::VLEN-1:0] mem_addr;
logic [NRET*riscv::PLEN-1:0] mem_paddr;
logic [NRET*(riscv::XLEN/8)-1:0] mem_rmask;
logic [NRET*(riscv::XLEN/8)-1:0] mem_wmask;
logic [NRET*riscv::XLEN-1:0] mem_rdata;
logic [NRET*riscv::XLEN-1:0] mem_wdata;
} rvfi_instr_t;
typedef rvfi_instr_t [ariane_pkg::NR_COMMIT_PORTS-1:0] rvfi_port_t;
endpackage

2
corev_apu/tb/ariane.sv
View file

@ -13,7 +13,7 @@
// Description: Ariane Top-level module
module ariane import ariane_pkg::*; import ariane_rvfi_pkg::*; #(
module ariane import ariane_pkg::*; #(
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth,
parameter int unsigned AxiDataWidth = ariane_axi::DataWidth,

2
corev_apu/tb/ariane_testharness.sv
View file

@ -620,7 +620,7 @@ module ariane_testharness #(
// ---------------
ariane_axi_soc::req_t axi_ariane_req;
ariane_axi_soc::resp_t axi_ariane_resp;
ariane_rvfi_pkg::rvfi_port_t rvfi;
ariane_pkg::rvfi_port_t rvfi;
ariane #(
.ArianeCfg ( ariane_soc::ArianeSocCfg )