Add CSRs tests for embedded config (#1601)

.gitlab-ci.yml

@@ -413,11 +413,26 @@ directed_isacov-tests:
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
+csr_embedded_tests:
+  extends:
+    - .verif_test
+  variables:
+    DASHBOARD_JOB_TITLE: "csr_embedded test $DV_TARGET"
+    DASHBOARD_JOB_DESCRIPTION: "CSR Test generated using UVM-REG"
+    DASHBOARD_SORT_INDEX: 15
+    DASHBOARD_JOB_CATEGORY: "CSR tests"
+    DV_SIMULATORS: "vcs-uvm"
+  script:
+    - mkdir -p artifacts/coverage
+    - source verif/regress/dv-csr-embedded-tests.sh
+    - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
+    - python3 .gitlab-ci/scripts/report_pass.py
+
 directed_xif-tests:
   extends:
     - .verif_test
   variables:
-    DASHBOARD_SORT_INDEX: 15
+    DASHBOARD_SORT_INDEX: 16
     DASHBOARD_JOB_CATEGORY: "Functional Coverage"
   parallel:
     matrix:
@@ -496,6 +511,7 @@ code_coverage-report:
     - directed_isacov-tests
     - generated_xif_tests
     - directed_xif-tests
+    - csr_embedded_tests
   variables:
     DASHBOARD_JOB_TITLE: "Report merge coverage"
     DASHBOARD_JOB_DESCRIPTION: "Report merge coverage of generated tests"

verif/regress/dv-csr-embedded-tests.sh

@@ -0,0 +1,33 @@
+# Copyright 2023 Thales DIS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Ayoub JALALI - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+  echo "Error: RISCV variable undefined"
+  return
+fi
+
+# install the required tools
+source verif/regress/install-cva6.sh
+source verif/regress/install-riscv-dv.sh
+
+export cov=1 #enable the Code Coverage
+
+if ! [ -n "$DV_TARGET" ]; then
+  DV_TARGET=cv32a6_embedded
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+  DV_SIMULATORS=vcs-uvm,spike
+fi
+
+cd verif/sim/
+python3 cva6.py --testlist=../tests/testlist_csr_embedded.yaml --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
+
+cd -

verif/tests/custom/csr_embedded/csr_test.S

@@ -0,0 +1,42 @@
+# Copyright 2023 Thales DIS France SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+
+#include "csrrst_test.S"
+#include "csrrw_fields_test.S"
+#include "csrrw_test.S"
+#include "csrrwi_test.S"
+#include "csrcs_test.S"
+#include "csrcsi_test.S"
+
+.globl main
+main:
+    #Start CSR tests: all tests
+    call csrrst
+    call csrrw_fields
+    call csrrw
+    call csrrwi
+    call csrcs
+    call csrcsi
+
+    #End of csr test
+    j csr_pass
+
+csr_pass:
+    li x1, 0
+    slli x1, x1, 1
+    addi x1, x1, 1
+    sw x1, tohost, x30
+    self_loop: j self_loop
+
+csr_fail:
+    li x1, 1
+    slli x1, x1, 1
+    addi x1, x1, 1
+    sw x1, tohost, x30
+    self_loop_2: j self_loop_2
+

verif/tests/custom/csr_embedded/csrrst_test.S

@@ -0,0 +1,403 @@
+# Copyright 2023 Thales DIS France SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+
+csrrst:
+    #Start CSR tests: Read all registers reset value in random order
+    #User ignored registers: 
+
+    #MCAUSE read value
+    csrr x14, 0x342
+
+    #MHPMCOUNTERH20 read value
+    csrr x14, 0xb94
+
+    #MISA read value
+    csrr x14, 0x301
+
+    #PMPCFG0 read value
+    csrr x14, 0x3a0
+
+    #PMPCFG1 read value
+    csrr x14, 0x3a1
+
+    #PMPADDR14 read value
+    csrr x14, 0x3be
+
+    #MHPMCOUNTERH30 read value
+    csrr x14, 0xb9e
+
+    #MHPMEVENT28 read value
+    csrr x14, 0x33c
+
+    #INSTRETH read value
+    csrr x14, 0xc82
+
+    #MHPMCOUNTERH9 read value
+    csrr x14, 0xb89
+
+    #PMPCFG2 read value
+    csrr x14, 0x3a2
+
+    #PMPADDR15 read value
+    csrr x14, 0x3bf
+
+    #MHPMCOUNTERH3 read value
+    csrr x14, 0xb83
+
+    #MIP read value
+    csrr x14, 0x344
+
+    #MHPMEVENT23 read value
+    csrr x14, 0x337
+
+    #MHPMEVENT20 read value
+    csrr x14, 0x334
+
+    #MTVEC read value
+    csrr x14, 0x305
+
+    #PMPADDR1 read value
+    csrr x14, 0x3b1
+
+    #MHPMCOUNTERH7 read value
+    csrr x14, 0xb87
+
+    #MHPMEVENT30 read value
+    csrr x14, 0x33e
+
+    #MHPMCOUNTERH24 read value
+    csrr x14, 0xb98
+
+    #MHPMEVENT12 read value
+    csrr x14, 0x32c
+
+    #MHPMCOUNTERH28 read value
+    csrr x14, 0xb9c
+
+    #MHPMCOUNTERH16 read value
+    csrr x14, 0xb90
+
+    #MHPMCOUNTER13 read value
+    csrr x14, 0xb0d
+
+    #INSTRET read value
+    csrr x14, 0xc02
+
+    #MHPMCOUNTERH19 read value
+    csrr x14, 0xb93
+
+    #MHPMEVENT3 read value
+    csrr x14, 0x323
+
+    #MCYCLEH read value
+    csrr x14, 0xb80
+
+    #MHPMEVENT31 read value
+    csrr x14, 0x33f
+
+    #MIE read value
+    csrr x14, 0x304
+
+    #MHPMEVENT11 read value
+    csrr x14, 0x32b
+
+    #MHPMCOUNTERH4 read value
+    csrr x14, 0xb84
+
+    #MHPMCOUNTER3 read value
+    csrr x14, 0xb03
+
+    #MHPMCOUNTERH15 read value
+    csrr x14, 0xb8f
+
+    #CYCLE read value
+    csrr x14, 0xc00
+
+    #MHPMEVENT27 read value
+    csrr x14, 0x33b
+
+    #MHPMCOUNTER18 read value
+    csrr x14, 0xb12
+
+    #MHPMCOUNTERH11 read value
+    csrr x14, 0xb8b
+
+    #MHPMEVENT29 read value
+    csrr x14, 0x33d
+
+    #MHPMCOUNTER11 read value
+    csrr x14, 0xb0b
+
+    #MHPMCOUNTERH27 read value
+    csrr x14, 0xb9b
+
+    #MHPMEVENT19 read value
+    csrr x14, 0x333
+
+    #MHPMCOUNTER21 read value
+    csrr x14, 0xb15
+
+    #MHPMCOUNTER6 read value
+    csrr x14, 0xb06
+
+    #MHPMCOUNTERH10 read value
+    csrr x14, 0xb8a
+
+    #MHPMCOUNTER30 read value
+    csrr x14, 0xb1e
+
+    #MHPMCOUNTER23 read value
+    csrr x14, 0xb17
+
+    #MHPMEVENT16 read value
+    csrr x14, 0x330
+
+    #MHPMCOUNTER4 read value
+    csrr x14, 0xb04
+
+    #MTVAL read value
+    csrr x14, 0x343
+
+    #MCYCLE read value
+    csrr x14, 0xb00
+
+    #MHPMCOUNTER28 read value
+    csrr x14, 0xb1c
+
+    #MHPMCOUNTERH25 read value
+    csrr x14, 0xb99
+
+    #MHPMCOUNTER8 read value
+    csrr x14, 0xb08
+
+    #MHPMEVENT4 read value
+    csrr x14, 0x324
+
+    #MHPMEVENT17 read value
+    csrr x14, 0x331
+
+    #CYCLEH read value
+    csrr x14, 0xc80
+
+    #PMPADDR10 read value
+    csrr x14, 0x3ba
+
+    #MSTATUS read value
+    csrr x14, 0x300
+
+    #MHPMCOUNTERH31 read value
+    csrr x14, 0xb9f
+
+    #PMPADDR13 read value
+    csrr x14, 0x3bd
+
+    #MHPMCOUNTER24 read value
+    csrr x14, 0xb18
+
+    #MARCHID read value
+    csrr x14, 0xf12
+
+    #MHPMCOUNTERH29 read value
+    csrr x14, 0xb9d
+
+    #MHPMCOUNTERH21 read value
+    csrr x14, 0xb95
+
+    #MHPMCOUNTER25 read value
+    csrr x14, 0xb19
+
+    #MHPMEVENT15 read value
+    csrr x14, 0x32f
+
+    #MHPMEVENT18 read value
+    csrr x14, 0x332
+
+    #MHPMCOUNTER20 read value
+    csrr x14, 0xb14
+
+    #MHPMCOUNTER26 read value
+    csrr x14, 0xb1a
+
+    #MHPMCOUNTER27 read value
+    csrr x14, 0xb1b
+
+    #MHPMCOUNTERH18 read value
+    csrr x14, 0xb92
+
+    #MHPMEVENT24 read value
+    csrr x14, 0x338
+
+    #MHPMEVENT14 read value
+    csrr x14, 0x32e
+
+    #PMPADDR5 read value
+    csrr x14, 0x3b5
+
+    #MHPMCOUNTERH13 read value
+    csrr x14, 0xb8d
+
+    #MHPMCOUNTER17 read value
+    csrr x14, 0xb11
+
+    #PMPADDR3 read value
+    csrr x14, 0x3b3
+
+    #PMPADDR2 read value
+    csrr x14, 0x3b2
+
+    #MHPMEVENT26 read value
+    csrr x14, 0x33a
+
+    #MINSTRETH read value
+    csrr x14, 0xb82
+
+    #MHPMEVENT10 read value
+    csrr x14, 0x32a
+
+    #MINSTRET read value
+    csrr x14, 0xb02
+
+    #MHPMCOUNTERH14 read value
+    csrr x14, 0xb8e
+
+    #PMPADDR7 read value
+    csrr x14, 0x3b7
+
+    #PMPCFG3 read value
+    csrr x14, 0x3a3
+
+    #MHPMCOUNTERH5 read value
+    csrr x14, 0xb85
+
+    #MIMPID read value
+    csrr x14, 0xf13
+
+    #MHPMCOUNTER29 read value
+    csrr x14, 0xb1d
+
+    #MHARTID read value
+    csrr x14, 0xf14
+
+    #MHPMCOUNTER31 read value
+    csrr x14, 0xb1f
+
+    #MHPMCOUNTERH6 read value
+    csrr x14, 0xb86
+
+    #MHPMEVENT6 read value
+    csrr x14, 0x326
+
+    #MHPMEVENT22 read value
+    csrr x14, 0x336
+
+    #MHPMCOUNTER14 read value
+    csrr x14, 0xb0e
+
+    #PMPADDR9 read value
+    csrr x14, 0x3b9
+
+    #PMPADDR8 read value
+    csrr x14, 0x3b8
+
+    #MHPMEVENT13 read value
+    csrr x14, 0x32d
+
+    #PMPADDR6 read value
+    csrr x14, 0x3b6
+
+    #MSCRATCH read value
+    csrr x14, 0x340
+
+    #MHPMCOUNTER19 read value
+    csrr x14, 0xb13
+
+    #MHPMCOUNTER12 read value
+    csrr x14, 0xb0c
+
+    #MHPMEVENT9 read value
+    csrr x14, 0x329
+
+    #MHPMCOUNTERH26 read value
+    csrr x14, 0xb9a
+
+    #MHPMCOUNTERH12 read value
+    csrr x14, 0xb8c
+
+    #MHPMCOUNTER15 read value
+    csrr x14, 0xb0f
+
+    #MHPMCOUNTER7 read value
+    csrr x14, 0xb07
+
+    #MHPMCOUNTER10 read value
+    csrr x14, 0xb0a
+
+    #MEPC read value
+    csrr x14, 0x341
+
+    #MHPMCOUNTERH23 read value
+    csrr x14, 0xb97
+
+    #PMPADDR11 read value
+    csrr x14, 0x3bb
+
+    #MHPMCOUNTERH17 read value
+    csrr x14, 0xb91
+
+    #MHPMCOUNTER22 read value
+    csrr x14, 0xb16
+
+    #MSTATUSH read value
+    csrr x14, 0x310
+
+    #PMPADDR12 read value
+    csrr x14, 0x3bc
+
+    #MHPMEVENT7 read value
+    csrr x14, 0x327
+
+    #ICACHE read value
+    csrr x14, 0x7c0
+
+    #MHPMCOUNTER5 read value
+    csrr x14, 0xb05
+
+    #MHPMCOUNTER9 read value
+    csrr x14, 0xb09
+
+    #MHPMEVENT21 read value
+    csrr x14, 0x335
+
+    #PMPADDR4 read value
+    csrr x14, 0x3b4
+
+    #MHPMCOUNTERH22 read value
+    csrr x14, 0xb96
+
+    #MVENDORID read value
+    csrr x14, 0xf11
+
+    #PMPADDR0 read value
+    csrr x14, 0x3b0
+
+    #MHPMEVENT25 read value
+    csrr x14, 0x339
+
+    #MHPMCOUNTER16 read value
+    csrr x14, 0xb10
+
+    #MHPMEVENT5 read value
+    csrr x14, 0x325
+
+    #MHPMEVENT8 read value
+    csrr x14, 0x328
+
+    #MHPMCOUNTERH8 read value
+    csrr x14, 0xb88
+
+    ret

verif/tests/custom/isacov/csr_test.S

@@ -1,73 +0,0 @@
-# Copyright 2023 Thales DIS France SAS
-#
-# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-# You may obtain a copy of the License at https://solderpad.org/licenses/
-#
-
-#include "csrrw_test.S"
-#include "csrrwi_test.S"
-#include "csrcs_test.S"
-#include "csrcsi_test.S"
-
-.globl main
-main:
-    #Start CSR tests: all tests
-    #Handle exceptions
-    la x6, exception_handler
-    csrw mtvec, x6  ## Load the address of the exception handler into MTVEC
-    csrw 0x341, x0  ## Writing Zero to MEPC CSR
-    csrw 0x342, x0  ## Writing Zero to MCAUSE CSR
-    #End Handle exceptions
-    call csrrw
-    call csrrwi
-    call csrcs
-    call csrcsi
-
-    #End of csr test
-    j csr_pass
-
-csr_pass:
-    li x1, 0xBEEFBEEF
-    li x1, 0
-    slli x1, x1, 1
-    addi x1, x1, 1
-    sw x1, tohost, x30
-    self_loop: j self_loop
-
-csr_fail:
-    li x1, 0xBADBAD
-    li x1, 1
-    slli x1, x1, 1
-    addi x1, x1, 1
-    sw x1, tohost, x30
-    self_loop_2: j self_loop_2
-
-exception_handler:
-    #addi x10, x10, 1  ##Increment number of exceptions
-    li x1, 0xABCDEF
-    csrr x3, 0x300
-    srli x3, x3, 11
-    andi x3, x3, 0b11
-    li x8, 3
-    li x9, 1
-    beq x3, x8, machine_exception_handler
-    #beqz x3, user_exception_handler
-    #beq x3, x9, supervisor_exception_handler
-    j csr_fail
-
-machine_exception_handler:
-    csrr x6, 0x300
-    csrr x30, 0x341          ## Reading MEPC CSR which holds exception origin Address
-    csrr x31, 0x342          ## Reading MCAUSE CSR which holds the cause of exception
-    li x2 ,2                 ## MCAUSE == Illegal instruction
-    beq x31, x2, goto_next_instr   ## Checking if exception is illegal instruction
-    j csr_fail
-
-goto_next_instr:
-    csrw 0x342, 0		        ## Reseting MCAUSE value to 0 before handling new exception
-    beq x30, x0, csr_fail
-    addi x7, x30, 4
-    jr x7			           ## Jump to latest instruction: MEPC + 4 Address location
-    j csr_fail

verif/tests/custom/isacov/csrcs_test.S

@@ -1,684 +0,0 @@
-# Copyright 2023 Thales DIS France SAS
-#
-# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-# You may obtain a copy of the License at https://solderpad.org/licenses/
-#
-
-csrcs:
-    #Start CSR tests: Write/Read all registers using Clear/Set instructions
-    #User ignored registers: MHPMEVENT3 ,MHPMEVENT4 ,MHPMEVENT5 ,MHPMEVENT6 ,MHPMEVENT7 ,MHPMEVENT8 ,MHPMEVENT9 ,MHPMEVENT10 ,MHPMEVENT11 ,MHPMEVENT12 ,MHPMEVENT13 ,MHPMEVENT14 ,MHPMEVENT15 ,MHPMEVENT16 ,MHPMEVENT17 ,MHPMEVENT18 ,MHPMEVENT19 ,MHPMEVENT20 ,MHPMEVENT21 ,MHPMEVENT22 ,MHPMEVENT23 ,MHPMEVENT24 ,MHPMEVENT25 ,MHPMEVENT26 ,MHPMEVENT27 ,MHPMEVENT28 ,MHPMEVENT29 ,MHPMEVENT30 ,MHPMEVENT31 ,PMPCFG0 ,PMPCFG1 ,PMPCFG2 ,PMPCFG3 ,PMPADDR0 ,PMPADDR1 ,PMPADDR2 ,PMPADDR3 ,PMPADDR4 ,PMPADDR5 ,PMPADDR6 ,PMPADDR7 ,PMPADDR8 ,PMPADDR9 ,PMPADDR10 ,PMPADDR11 ,PMPADDR12 ,PMPADDR13 ,PMPADDR14 ,PMPADDR15 ,ICACHE ,MHPMCOUNTER3 ,MHPMCOUNTER4 ,MHPMCOUNTER5 ,MHPMCOUNTER6 ,MHPMCOUNTER7 ,MHPMCOUNTER8 ,MHPMCOUNTER9 ,MHPMCOUNTER10 ,MHPMCOUNTER11 ,MHPMCOUNTER12 ,MHPMCOUNTER13 ,MHPMCOUNTER14 ,MHPMCOUNTER15 ,MHPMCOUNTER16 ,MHPMCOUNTER17 ,MHPMCOUNTER18 ,MHPMCOUNTER19 ,MHPMCOUNTER20 ,MHPMCOUNTER21 ,MHPMCOUNTER22 ,MHPMCOUNTER23 ,MHPMCOUNTER24 ,MHPMCOUNTER25 ,MHPMCOUNTER26 ,MHPMCOUNTER27 ,MHPMCOUNTER28 ,MHPMCOUNTER29 ,MHPMCOUNTER30 ,MHPMCOUNTER31 ,MHPMCOUNTERH3 ,MHPMCOUNTERH4 ,MHPMCOUNTERH5 ,MHPMCOUNTERH6 ,MHPMCOUNTERH7 ,MHPMCOUNTERH8 ,MHPMCOUNTERH9 ,MHPMCOUNTERH10 ,MHPMCOUNTERH11 ,MHPMCOUNTERH12 ,MHPMCOUNTERH13 ,MHPMCOUNTERH14 ,MHPMCOUNTERH15 ,MHPMCOUNTERH16 ,MHPMCOUNTERH17 ,MHPMCOUNTERH18 ,MHPMCOUNTERH19 ,MHPMCOUNTERH20 ,MHPMCOUNTERH21 ,MHPMCOUNTERH22 ,MHPMCOUNTERH23 ,MHPMCOUNTERH24 ,MHPMCOUNTERH25 ,MHPMCOUNTERH26 ,MHPMCOUNTERH27 ,MHPMCOUNTERH28 ,MHPMCOUNTERH29 ,MHPMCOUNTERH30 ,MHPMCOUNTERH31 ,
-    ##########################
-    #MSTATUS testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18}
-    ##########################
-    #MSTATUS Write clear/set value 0x1f
-    li x3, 0x7ffe19e0
-    csrrc x14, 0x300, x3
-    li x3, 0x1f
-    csrrs x14, 0x300, x3
-
-    #MSTATUS read value, expected 0xa
-    csrr x14, 0x300
-
-    #MSTATUS Write clear/set value 0x0
-    li x3, 0x7ffe19ff
-    csrrc x14, 0x300, x3
-    li x3, 0x0
-    csrrs x14, 0x300, x3
-
-    #MSTATUS read value, expected 0x0
-    csrr x14, 0x300
-
-    #MSTATUS Write clear/set value 0x15
-    li x3, 0x7ffe19ea
-    csrrc x14, 0x300, x3
-    li x3, 0x15
-    csrrs x14, 0x300, x3
-
-    #MSTATUS read value, expected 0x0
-    csrr x14, 0x300
-
-    #MSTATUS Write clear/set value 0xa
-    li x3, 0x7ffe19f5
-    csrrc x14, 0x300, x3
-    li x3, 0xa
-    csrrs x14, 0x300, x3
-
-    #MSTATUS read value, expected 0xa
-    csrr x14, 0x300
-
-    #MSTATUS Write clear/set value 0x18
-    li x3, 0x7ffe19e7
-    csrrc x14, 0x300, x3
-    li x3, 0x18
-    csrrs x14, 0x300, x3
-
-    #MSTATUS read value, expected 0x8
-    csrr x14, 0x300
-
-    ##########################
-    #MTVEC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h4}
-    ##########################
-    #MTVEC Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0x305, x3
-    li x3, 0x1f
-    csrrs x14, 0x305, x3
-
-    #MTVEC read value, expected 0x1f
-    csrr x14, 0x305
-
-    #MTVEC Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0x305, x3
-    li x3, 0x0
-    csrrs x14, 0x305, x3
-
-    #MTVEC read value, expected 0x0
-    csrr x14, 0x305
-
-    #MTVEC Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0x305, x3
-    li x3, 0x15
-    csrrs x14, 0x305, x3
-
-    #MTVEC read value, expected 0x15
-    csrr x14, 0x305
-
-    #MTVEC Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0x305, x3
-    li x3, 0xa
-    csrrs x14, 0x305, x3
-
-    #MTVEC read value, expected 0xa
-    csrr x14, 0x305
-
-    #MTVEC Write clear/set value 0x4
-    li x3, 0xfffffffb
-    csrrc x14, 0x305, x3
-    li x3, 0x4
-    csrrs x14, 0x305, x3
-
-    #MTVEC read value, expected 0x4
-    csrr x14, 0x305
-
-    ##########################
-    #MSTATUSH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1}
-    ##########################
-    #MSTATUSH Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0x310, x3
-    li x3, 0x1f
-    csrrs x14, 0x310, x3
-
-    #MSTATUSH read value, expected 0x10
-    csrr x14, 0x310
-
-    #MSTATUSH Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0x310, x3
-    li x3, 0x0
-    csrrs x14, 0x310, x3
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    #MSTATUSH Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0x310, x3
-    li x3, 0x15
-    csrrs x14, 0x310, x3
-
-    #MSTATUSH read value, expected 0x10
-    csrr x14, 0x310
-
-    #MSTATUSH Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0x310, x3
-    li x3, 0xa
-    csrrs x14, 0x310, x3
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    #MSTATUSH Write clear/set value 0x1
-    li x3, 0xfffffffe
-    csrrc x14, 0x310, x3
-    li x3, 0x1
-    csrrs x14, 0x310, x3
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    ##########################
-    #MCYCLEH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h2}
-    ##########################
-    #MCYCLEH Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0xb80, x3
-    li x3, 0x1f
-    csrrs x14, 0xb80, x3
-
-    #MCYCLEH read value, expected 0x1f
-    csrr x14, 0xb80
-
-    #MCYCLEH Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0xb80, x3
-    li x3, 0x0
-    csrrs x14, 0xb80, x3
-
-    #MCYCLEH read value, expected 0x0
-    csrr x14, 0xb80
-
-    #MCYCLEH Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0xb80, x3
-    li x3, 0x15
-    csrrs x14, 0xb80, x3
-
-    #MCYCLEH read value, expected 0x15
-    csrr x14, 0xb80
-
-    #MCYCLEH Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0xb80, x3
-    li x3, 0xa
-    csrrs x14, 0xb80, x3
-
-    #MCYCLEH read value, expected 0xa
-    csrr x14, 0xb80
-
-    #MCYCLEH Write clear/set value 0x2
-    li x3, 0xfffffffd
-    csrrc x14, 0xb80, x3
-    li x3, 0x2
-    csrrs x14, 0xb80, x3
-
-    #MCYCLEH read value, expected 0x2
-    csrr x14, 0xb80
-
-    ##########################
-    #MSCRATCH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'hd}
-    ##########################
-    #MSCRATCH Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0x340, x3
-    li x3, 0x1f
-    csrrs x14, 0x340, x3
-
-    #MSCRATCH read value, expected 0x1f
-    csrr x14, 0x340
-
-    #MSCRATCH Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0x340, x3
-    li x3, 0x0
-    csrrs x14, 0x340, x3
-
-    #MSCRATCH read value, expected 0x0
-    csrr x14, 0x340
-
-    #MSCRATCH Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0x340, x3
-    li x3, 0x15
-    csrrs x14, 0x340, x3
-
-    #MSCRATCH read value, expected 0x15
-    csrr x14, 0x340
-
-    #MSCRATCH Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0x340, x3
-    li x3, 0xa
-    csrrs x14, 0x340, x3
-
-    #MSCRATCH read value, expected 0xa
-    csrr x14, 0x340
-
-    #MSCRATCH Write clear/set value 0xd
-    li x3, 0xfffffff2
-    csrrc x14, 0x340, x3
-    li x3, 0xd
-    csrrs x14, 0x340, x3
-
-    #MSCRATCH read value, expected 0xd
-    csrr x14, 0x340
-
-    ##########################
-    #MINSTRET testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h15}
-    ##########################
-    #MINSTRET Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0xb02, x3
-    li x3, 0x1f
-    csrrs x14, 0xb02, x3
-
-    #MINSTRET read value, expected 0x1f
-    csrr x14, 0xb02
-
-    #MINSTRET Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0xb02, x3
-    li x3, 0x0
-    csrrs x14, 0xb02, x3
-
-    #MINSTRET read value, expected 0x0
-    csrr x14, 0xb02
-
-    #MINSTRET Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0xb02, x3
-    li x3, 0x15
-    csrrs x14, 0xb02, x3
-
-    #MINSTRET read value, expected 0x15
-    csrr x14, 0xb02
-
-    #MINSTRET Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0xb02, x3
-    li x3, 0xa
-    csrrs x14, 0xb02, x3
-
-    #MINSTRET read value, expected 0xa
-    csrr x14, 0xb02
-
-    #MINSTRET Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0xb02, x3
-    li x3, 0x15
-    csrrs x14, 0xb02, x3
-
-    #MINSTRET read value, expected 0x15
-    csrr x14, 0xb02
-
-    ##########################
-    #MIP testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h4}
-    ##########################
-    #MIP Write clear/set value 0x1f
-    li x3, 0xfffff760
-    csrrc x14, 0x344, x3
-    li x3, 0x1f
-    csrrs x14, 0x344, x3
-
-    #MIP read value, expected 0x1b
-    csrr x14, 0x344
-
-    #MIP Write clear/set value 0x0
-    li x3, 0xfffff777
-    csrrc x14, 0x344, x3
-    li x3, 0x0
-    csrrs x14, 0x344, x3
-
-    #MIP read value, expected 0x0
-    csrr x14, 0x344
-
-    #MIP Write clear/set value 0x15
-    li x3, 0xfffff762
-    csrrc x14, 0x344, x3
-    li x3, 0x15
-    csrrs x14, 0x344, x3
-
-    #MIP read value, expected 0x11
-    csrr x14, 0x344
-
-    #MIP Write clear/set value 0xa
-    li x3, 0xfffff775
-    csrrc x14, 0x344, x3
-    li x3, 0xa
-    csrrs x14, 0x344, x3
-
-    #MIP read value, expected 0xa
-    csrr x14, 0x344
-
-    #MIP Write clear/set value 0x4
-    li x3, 0xfffff773
-    csrrc x14, 0x344, x3
-    li x3, 0x4
-    csrrs x14, 0x344, x3
-
-    #MIP read value, expected 0x0
-    csrr x14, 0x344
-
-    ##########################
-    #MEPC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1b}
-    ##########################
-    #MEPC Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0x341, x3
-    li x3, 0x1f
-    csrrs x14, 0x341, x3
-
-    #MEPC read value, expected 0x1f
-    csrr x14, 0x341
-
-    #MEPC Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0x341, x3
-    li x3, 0x0
-    csrrs x14, 0x341, x3
-
-    #MEPC read value, expected 0x0
-    csrr x14, 0x341
-
-    #MEPC Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0x341, x3
-    li x3, 0x15
-    csrrs x14, 0x341, x3
-
-    #MEPC read value, expected 0x15
-    csrr x14, 0x341
-
-    #MEPC Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0x341, x3
-    li x3, 0xa
-    csrrs x14, 0x341, x3
-
-    #MEPC read value, expected 0xa
-    csrr x14, 0x341
-
-    #MEPC Write clear/set value 0x1b
-    li x3, 0xffffffe4
-    csrrc x14, 0x341, x3
-    li x3, 0x1b
-    csrrs x14, 0x341, x3
-
-    #MEPC read value, expected 0x1b
-    csrr x14, 0x341
-
-    ##########################
-    #MCYCLE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1d}
-    ##########################
-    #MCYCLE Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0xb00, x3
-    li x3, 0x1f
-    csrrs x14, 0xb00, x3
-
-    #MCYCLE read value, expected 0x1f
-    csrr x14, 0xb00
-
-    #MCYCLE Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0xb00, x3
-    li x3, 0x0
-    csrrs x14, 0xb00, x3
-
-    #MCYCLE read value, expected 0x0
-    csrr x14, 0xb00
-
-    #MCYCLE Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0xb00, x3
-    li x3, 0x15
-    csrrs x14, 0xb00, x3
-
-    #MCYCLE read value, expected 0x15
-    csrr x14, 0xb00
-
-    #MCYCLE Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0xb00, x3
-    li x3, 0xa
-    csrrs x14, 0xb00, x3
-
-    #MCYCLE read value, expected 0xa
-    csrr x14, 0xb00
-
-    #MCYCLE Write clear/set value 0x1d
-    li x3, 0xffffffe2
-    csrrc x14, 0xb00, x3
-    li x3, 0x1d
-    csrrs x14, 0xb00, x3
-
-    #MCYCLE read value, expected 0x1d
-    csrr x14, 0xb00
-
-    ##########################
-    #MINSTRETH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1a}
-    ##########################
-    #MINSTRETH Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0xb82, x3
-    li x3, 0x1f
-    csrrs x14, 0xb82, x3
-
-    #MINSTRETH read value, expected 0x1f
-    csrr x14, 0xb82
-
-    #MINSTRETH Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0xb82, x3
-    li x3, 0x0
-    csrrs x14, 0xb82, x3
-
-    #MINSTRETH read value, expected 0x0
-    csrr x14, 0xb82
-
-    #MINSTRETH Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0xb82, x3
-    li x3, 0x15
-    csrrs x14, 0xb82, x3
-
-    #MINSTRETH read value, expected 0x15
-    csrr x14, 0xb82
-
-    #MINSTRETH Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0xb82, x3
-    li x3, 0xa
-    csrrs x14, 0xb82, x3
-
-    #MINSTRETH read value, expected 0xa
-    csrr x14, 0xb82
-
-    #MINSTRETH Write clear/set value 0x1a
-    li x3, 0xffffffe5
-    csrrc x14, 0xb82, x3
-    li x3, 0x1a
-    csrrs x14, 0xb82, x3
-
-    #MINSTRETH read value, expected 0x1a
-    csrr x14, 0xb82
-
-    ##########################
-    #MCAUSE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16}
-    ##########################
-    #MCAUSE Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0x342, x3
-    li x3, 0x1f
-    csrrs x14, 0x342, x3
-
-    #MCAUSE read value, expected 0x1f
-    csrr x14, 0x342
-
-    #MCAUSE Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0x342, x3
-    li x3, 0x0
-    csrrs x14, 0x342, x3
-
-    #MCAUSE read value, expected 0x0
-    csrr x14, 0x342
-
-    #MCAUSE Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0x342, x3
-    li x3, 0x15
-    csrrs x14, 0x342, x3
-
-    #MCAUSE read value, expected 0x15
-    csrr x14, 0x342
-
-    #MCAUSE Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0x342, x3
-    li x3, 0xa
-    csrrs x14, 0x342, x3
-
-    #MCAUSE read value, expected 0xa
-    csrr x14, 0x342
-
-    #MCAUSE Write clear/set value 0x16
-    li x3, 0xffffffe9
-    csrrc x14, 0x342, x3
-    li x3, 0x16
-    csrrs x14, 0x342, x3
-
-    #MCAUSE read value, expected 0x16
-    csrr x14, 0x342
-
-    ##########################
-    #MISA testing W/R values '{'h1b, 'h4, 'h15, 'ha, 'h8}
-    ##########################
-    #MISA Write clear/set value 0x1b
-    li x3, 0xffffffe4
-    csrrc x14, 0x301, x3
-    li x3, 0x1b
-    csrrs x14, 0x301, x3
-
-    #MISA read value, expected 0x1b
-    csrr x14, 0x301
-
-    #MISA Write clear/set value 0x4
-    li x3, 0xfffffffb
-    csrrc x14, 0x301, x3
-    li x3, 0x4
-    csrrs x14, 0x301, x3
-
-    #MISA read value, expected 0x4
-    csrr x14, 0x301
-
-    #MISA Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0x301, x3
-    li x3, 0x15
-    csrrs x14, 0x301, x3
-
-    #MISA read value, expected 0x15
-    csrr x14, 0x301
-
-    #MISA Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0x301, x3
-    li x3, 0xa
-    csrrs x14, 0x301, x3
-
-    #MISA read value, expected 0xa
-    csrr x14, 0x301
-
-    #MISA Write clear/set value 0x8
-    li x3, 0xfffffff7
-    csrrc x14, 0x301, x3
-    li x3, 0x8
-    csrrs x14, 0x301, x3
-
-    #MISA read value, expected 0x8
-    csrr x14, 0x301
-
-    ##########################
-    #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1e}
-    ##########################
-    #MTVAL Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0x343, x3
-    li x3, 0x1f
-    csrrs x14, 0x343, x3
-
-    #MTVAL read value, expected 0x1f
-    csrr x14, 0x343
-
-    #MTVAL Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0x343, x3
-    li x3, 0x0
-    csrrs x14, 0x343, x3
-
-    #MTVAL read value, expected 0x0
-    csrr x14, 0x343
-
-    #MTVAL Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0x343, x3
-    li x3, 0x15
-    csrrs x14, 0x343, x3
-
-    #MTVAL read value, expected 0x15
-    csrr x14, 0x343
-
-    #MTVAL Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0x343, x3
-    li x3, 0xa
-    csrrs x14, 0x343, x3
-
-    #MTVAL read value, expected 0xa
-    csrr x14, 0x343
-
-    #MTVAL Write clear/set value 0x1e
-    li x3, 0xffffffe1
-    csrrc x14, 0x343, x3
-    li x3, 0x1e
-    csrrs x14, 0x343, x3
-
-    #MTVAL read value, expected 0x1e
-    csrr x14, 0x343
-
-    ##########################
-    #MIE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1a}
-    ##########################
-    #MIE Write clear/set value 0x1f
-    li x3, 0xffffffe0
-    csrrc x14, 0x304, x3
-    li x3, 0x1f
-    csrrs x14, 0x304, x3
-
-    #MIE read value, expected 0x1b
-    csrr x14, 0x304
-
-    #MIE Write clear/set value 0x0
-    li x3, 0xffffffff
-    csrrc x14, 0x304, x3
-    li x3, 0x0
-    csrrs x14, 0x304, x3
-
-    #MIE read value, expected 0x0
-    csrr x14, 0x304
-
-    #MIE Write clear/set value 0x15
-    li x3, 0xffffffea
-    csrrc x14, 0x304, x3
-    li x3, 0x15
-    csrrs x14, 0x304, x3
-
-    #MIE read value, expected 0x11
-    csrr x14, 0x304
-
-    #MIE Write clear/set value 0xa
-    li x3, 0xfffffff5
-    csrrc x14, 0x304, x3
-    li x3, 0xa
-    csrrs x14, 0x304, x3
-
-    #MIE read value, expected 0xa
-    csrr x14, 0x304
-
-    #MIE Write clear/set value 0x1a
-    li x3, 0xffffffe5
-    csrrc x14, 0x304, x3
-    li x3, 0x1a
-    csrrs x14, 0x304, x3
-
-    #MIE read value, expected 0x1a
-    csrr x14, 0x304
-
-    ret

verif/tests/custom/isacov/csrcsi_test.S

@@ -1,544 +0,0 @@
-# Copyright 2023 Thales DIS France SAS
-#
-# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-# You may obtain a copy of the License at https://solderpad.org/licenses/
-#
-
-csrcsi:
-    #Start CSR tests: Write/Read all registers using Clear/Set immediate instructions
-    #User ignored registers: MHPMEVENT3 ,MHPMEVENT4 ,MHPMEVENT5 ,MHPMEVENT6 ,MHPMEVENT7 ,MHPMEVENT8 ,MHPMEVENT9 ,MHPMEVENT10 ,MHPMEVENT11 ,MHPMEVENT12 ,MHPMEVENT13 ,MHPMEVENT14 ,MHPMEVENT15 ,MHPMEVENT16 ,MHPMEVENT17 ,MHPMEVENT18 ,MHPMEVENT19 ,MHPMEVENT20 ,MHPMEVENT21 ,MHPMEVENT22 ,MHPMEVENT23 ,MHPMEVENT24 ,MHPMEVENT25 ,MHPMEVENT26 ,MHPMEVENT27 ,MHPMEVENT28 ,MHPMEVENT29 ,MHPMEVENT30 ,MHPMEVENT31 ,PMPCFG0 ,PMPCFG1 ,PMPCFG2 ,PMPCFG3 ,PMPADDR0 ,PMPADDR1 ,PMPADDR2 ,PMPADDR3 ,PMPADDR4 ,PMPADDR5 ,PMPADDR6 ,PMPADDR7 ,PMPADDR8 ,PMPADDR9 ,PMPADDR10 ,PMPADDR11 ,PMPADDR12 ,PMPADDR13 ,PMPADDR14 ,PMPADDR15 ,ICACHE ,MHPMCOUNTER3 ,MHPMCOUNTER4 ,MHPMCOUNTER5 ,MHPMCOUNTER6 ,MHPMCOUNTER7 ,MHPMCOUNTER8 ,MHPMCOUNTER9 ,MHPMCOUNTER10 ,MHPMCOUNTER11 ,MHPMCOUNTER12 ,MHPMCOUNTER13 ,MHPMCOUNTER14 ,MHPMCOUNTER15 ,MHPMCOUNTER16 ,MHPMCOUNTER17 ,MHPMCOUNTER18 ,MHPMCOUNTER19 ,MHPMCOUNTER20 ,MHPMCOUNTER21 ,MHPMCOUNTER22 ,MHPMCOUNTER23 ,MHPMCOUNTER24 ,MHPMCOUNTER25 ,MHPMCOUNTER26 ,MHPMCOUNTER27 ,MHPMCOUNTER28 ,MHPMCOUNTER29 ,MHPMCOUNTER30 ,MHPMCOUNTER31 ,MHPMCOUNTERH3 ,MHPMCOUNTERH4 ,MHPMCOUNTERH5 ,MHPMCOUNTERH6 ,MHPMCOUNTERH7 ,MHPMCOUNTERH8 ,MHPMCOUNTERH9 ,MHPMCOUNTERH10 ,MHPMCOUNTERH11 ,MHPMCOUNTERH12 ,MHPMCOUNTERH13 ,MHPMCOUNTERH14 ,MHPMCOUNTERH15 ,MHPMCOUNTERH16 ,MHPMCOUNTERH17 ,MHPMCOUNTERH18 ,MHPMCOUNTERH19 ,MHPMCOUNTERH20 ,MHPMCOUNTERH21 ,MHPMCOUNTERH22 ,MHPMCOUNTERH23 ,MHPMCOUNTERH24 ,MHPMCOUNTERH25 ,MHPMCOUNTERH26 ,MHPMCOUNTERH27 ,MHPMCOUNTERH28 ,MHPMCOUNTERH29 ,MHPMCOUNTERH30 ,MHPMCOUNTERH31 ,
-    ##########################
-    #MSTATUS testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16}
-    ##########################
-    #MSTATUS Write clear/set value 0x1f
-    csrrci x14, 0x300, 0x0
-    csrrsi x14, 0x300, 0x1f
-
-    #MSTATUS read value, expected 0xa
-    csrr x14, 0x300
-
-    #MSTATUS Write clear/set value 0x0
-    csrrci x14, 0x300, 0x1f
-    csrrsi x14, 0x300, 0x0
-
-    #MSTATUS read value, expected 0x0
-    csrr x14, 0x300
-
-    #MSTATUS Write clear/set value 0x15
-    csrrci x14, 0x300, 0xa
-    csrrsi x14, 0x300, 0x15
-
-    #MSTATUS read value, expected 0x0
-    csrr x14, 0x300
-
-    #MSTATUS Write clear/set value 0xa
-    csrrci x14, 0x300, 0x15
-    csrrsi x14, 0x300, 0xa
-
-    #MSTATUS read value, expected 0xa
-    csrr x14, 0x300
-
-    #MSTATUS Write clear/set value 0x16
-    csrrci x14, 0x300, 0x9
-    csrrsi x14, 0x300, 0x16
-
-    #MSTATUS read value, expected 0x2
-    csrr x14, 0x300
-
-    ##########################
-    #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18}
-    ##########################
-    #MTVAL Write clear/set value 0x1f
-    csrrci x14, 0x343, 0x0
-    csrrsi x14, 0x343, 0x1f
-
-    #MTVAL read value, expected 0x1f
-    csrr x14, 0x343
-
-    #MTVAL Write clear/set value 0x0
-    csrrci x14, 0x343, 0x1f
-    csrrsi x14, 0x343, 0x0
-
-    #MTVAL read value, expected 0x0
-    csrr x14, 0x343
-
-    #MTVAL Write clear/set value 0x15
-    csrrci x14, 0x343, 0xa
-    csrrsi x14, 0x343, 0x15
-
-    #MTVAL read value, expected 0x15
-    csrr x14, 0x343
-
-    #MTVAL Write clear/set value 0xa
-    csrrci x14, 0x343, 0x15
-    csrrsi x14, 0x343, 0xa
-
-    #MTVAL read value, expected 0xa
-    csrr x14, 0x343
-
-    #MTVAL Write clear/set value 0x18
-    csrrci x14, 0x343, 0x7
-    csrrsi x14, 0x343, 0x18
-
-    #MTVAL read value, expected 0x18
-    csrr x14, 0x343
-
-    ##########################
-    #MSCRATCH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h9}
-    ##########################
-    #MSCRATCH Write clear/set value 0x1f
-    csrrci x14, 0x340, 0x0
-    csrrsi x14, 0x340, 0x1f
-
-    #MSCRATCH read value, expected 0x1f
-    csrr x14, 0x340
-
-    #MSCRATCH Write clear/set value 0x0
-    csrrci x14, 0x340, 0x1f
-    csrrsi x14, 0x340, 0x0
-
-    #MSCRATCH read value, expected 0x0
-    csrr x14, 0x340
-
-    #MSCRATCH Write clear/set value 0x15
-    csrrci x14, 0x340, 0xa
-    csrrsi x14, 0x340, 0x15
-
-    #MSCRATCH read value, expected 0x15
-    csrr x14, 0x340
-
-    #MSCRATCH Write clear/set value 0xa
-    csrrci x14, 0x340, 0x15
-    csrrsi x14, 0x340, 0xa
-
-    #MSCRATCH read value, expected 0xa
-    csrr x14, 0x340
-
-    #MSCRATCH Write clear/set value 0x9
-    csrrci x14, 0x340, 0x16
-    csrrsi x14, 0x340, 0x9
-
-    #MSCRATCH read value, expected 0x9
-    csrr x14, 0x340
-
-    ##########################
-    #MCYCLE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h2}
-    ##########################
-    #MCYCLE Write clear/set value 0x1f
-    csrrci x14, 0xb00, 0x0
-    csrrsi x14, 0xb00, 0x1f
-
-    #MCYCLE read value, expected 0x1f
-    csrr x14, 0xb00
-
-    #MCYCLE Write clear/set value 0x0
-    csrrci x14, 0xb00, 0x1f
-    csrrsi x14, 0xb00, 0x0
-
-    #MCYCLE read value, expected 0x0
-    csrr x14, 0xb00
-
-    #MCYCLE Write clear/set value 0x15
-    csrrci x14, 0xb00, 0xa
-    csrrsi x14, 0xb00, 0x15
-
-    #MCYCLE read value, expected 0x15
-    csrr x14, 0xb00
-
-    #MCYCLE Write clear/set value 0xa
-    csrrci x14, 0xb00, 0x15
-    csrrsi x14, 0xb00, 0xa
-
-    #MCYCLE read value, expected 0xa
-    csrr x14, 0xb00
-
-    #MCYCLE Write clear/set value 0x2
-    csrrci x14, 0xb00, 0x1d
-    csrrsi x14, 0xb00, 0x2
-
-    #MCYCLE read value, expected 0x2
-    csrr x14, 0xb00
-
-    ##########################
-    #MTVEC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h7}
-    ##########################
-    #MTVEC Write clear/set value 0x1f
-    csrrci x14, 0x305, 0x0
-    csrrsi x14, 0x305, 0x1f
-
-    #MTVEC read value, expected 0x1f
-    csrr x14, 0x305
-
-    #MTVEC Write clear/set value 0x0
-    csrrci x14, 0x305, 0x1f
-    csrrsi x14, 0x305, 0x0
-
-    #MTVEC read value, expected 0x0
-    csrr x14, 0x305
-
-    #MTVEC Write clear/set value 0x15
-    csrrci x14, 0x305, 0xa
-    csrrsi x14, 0x305, 0x15
-
-    #MTVEC read value, expected 0x15
-    csrr x14, 0x305
-
-    #MTVEC Write clear/set value 0xa
-    csrrci x14, 0x305, 0x15
-    csrrsi x14, 0x305, 0xa
-
-    #MTVEC read value, expected 0xa
-    csrr x14, 0x305
-
-    #MTVEC Write clear/set value 0x7
-    csrrci x14, 0x305, 0x18
-    csrrsi x14, 0x305, 0x7
-
-    #MTVEC read value, expected 0x7
-    csrr x14, 0x305
-
-    ##########################
-    #MCAUSE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16}
-    ##########################
-    #MCAUSE Write clear/set value 0x1f
-    csrrci x14, 0x342, 0x0
-    csrrsi x14, 0x342, 0x1f
-
-    #MCAUSE read value, expected 0x1f
-    csrr x14, 0x342
-
-    #MCAUSE Write clear/set value 0x0
-    csrrci x14, 0x342, 0x1f
-    csrrsi x14, 0x342, 0x0
-
-    #MCAUSE read value, expected 0x0
-    csrr x14, 0x342
-
-    #MCAUSE Write clear/set value 0x15
-    csrrci x14, 0x342, 0xa
-    csrrsi x14, 0x342, 0x15
-
-    #MCAUSE read value, expected 0x15
-    csrr x14, 0x342
-
-    #MCAUSE Write clear/set value 0xa
-    csrrci x14, 0x342, 0x15
-    csrrsi x14, 0x342, 0xa
-
-    #MCAUSE read value, expected 0xa
-    csrr x14, 0x342
-
-    #MCAUSE Write clear/set value 0x16
-    csrrci x14, 0x342, 0x9
-    csrrsi x14, 0x342, 0x16
-
-    #MCAUSE read value, expected 0x16
-    csrr x14, 0x342
-
-    ##########################
-    #MINSTRETH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1f}
-    ##########################
-    #MINSTRETH Write clear/set value 0x1f
-    csrrci x14, 0xb82, 0x0
-    csrrsi x14, 0xb82, 0x1f
-
-    #MINSTRETH read value, expected 0x1f
-    csrr x14, 0xb82
-
-    #MINSTRETH Write clear/set value 0x0
-    csrrci x14, 0xb82, 0x1f
-    csrrsi x14, 0xb82, 0x0
-
-    #MINSTRETH read value, expected 0x0
-    csrr x14, 0xb82
-
-    #MINSTRETH Write clear/set value 0x15
-    csrrci x14, 0xb82, 0xa
-    csrrsi x14, 0xb82, 0x15
-
-    #MINSTRETH read value, expected 0x15
-    csrr x14, 0xb82
-
-    #MINSTRETH Write clear/set value 0xa
-    csrrci x14, 0xb82, 0x15
-    csrrsi x14, 0xb82, 0xa
-
-    #MINSTRETH read value, expected 0xa
-    csrr x14, 0xb82
-
-    #MINSTRETH Write clear/set value 0x1f
-    csrrci x14, 0xb82, 0x0
-    csrrsi x14, 0xb82, 0x1f
-
-    #MINSTRETH read value, expected 0x1f
-    csrr x14, 0xb82
-
-    ##########################
-    #MIP testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h10}
-    ##########################
-    #MIP Write clear/set value 0x1f
-    csrrci x14, 0x344, 0x0
-    csrrsi x14, 0x344, 0x1f
-
-    #MIP read value, expected 0x1b
-    csrr x14, 0x344
-
-    #MIP Write clear/set value 0x0
-    csrrci x14, 0x344, 0x17
-    csrrsi x14, 0x344, 0x0
-
-    #MIP read value, expected 0x0
-    csrr x14, 0x344
-
-    #MIP Write clear/set value 0x15
-    csrrci x14, 0x344, 0x2
-    csrrsi x14, 0x344, 0x15
-
-    #MIP read value, expected 0x11
-    csrr x14, 0x344
-
-    #MIP Write clear/set value 0xa
-    csrrci x14, 0x344, 0x15
-    csrrsi x14, 0x344, 0xa
-
-    #MIP read value, expected 0xa
-    csrr x14, 0x344
-
-    #MIP Write clear/set value 0x10
-    csrrci x14, 0x344, 0x7
-    csrrsi x14, 0x344, 0x10
-
-    #MIP read value, expected 0x10
-    csrr x14, 0x344
-
-    ##########################
-    #MISA testing W/R values '{'h1b, 'h4, 'h15, 'ha, 'h3}
-    ##########################
-    #MISA Write clear/set value 0x1b
-    csrrci x14, 0x301, 0x4
-    csrrsi x14, 0x301, 0x1b
-
-    #MISA read value, expected 0x1b
-    csrr x14, 0x301
-
-    #MISA Write clear/set value 0x4
-    csrrci x14, 0x301, 0x1b
-    csrrsi x14, 0x301, 0x4
-
-    #MISA read value, expected 0x4
-    csrr x14, 0x301
-
-    #MISA Write clear/set value 0x15
-    csrrci x14, 0x301, 0xa
-    csrrsi x14, 0x301, 0x15
-
-    #MISA read value, expected 0x15
-    csrr x14, 0x301
-
-    #MISA Write clear/set value 0xa
-    csrrci x14, 0x301, 0x15
-    csrrsi x14, 0x301, 0xa
-
-    #MISA read value, expected 0xa
-    csrr x14, 0x301
-
-    #MISA Write clear/set value 0x3
-    csrrci x14, 0x301, 0x1c
-    csrrsi x14, 0x301, 0x3
-
-    #MISA read value, expected 0x3
-    csrr x14, 0x301
-
-    ##########################
-    #MSTATUSH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h2}
-    ##########################
-    #MSTATUSH Write clear/set value 0x1f
-    csrrci x14, 0x310, 0x0
-    csrrsi x14, 0x310, 0x1f
-
-    #MSTATUSH read value, expected 0x10
-    csrr x14, 0x310
-
-    #MSTATUSH Write clear/set value 0x0
-    csrrci x14, 0x310, 0x1f
-    csrrsi x14, 0x310, 0x0
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    #MSTATUSH Write clear/set value 0x15
-    csrrci x14, 0x310, 0xa
-    csrrsi x14, 0x310, 0x15
-
-    #MSTATUSH read value, expected 0x10
-    csrr x14, 0x310
-
-    #MSTATUSH Write clear/set value 0xa
-    csrrci x14, 0x310, 0x15
-    csrrsi x14, 0x310, 0xa
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    #MSTATUSH Write clear/set value 0x2
-    csrrci x14, 0x310, 0x1d
-    csrrsi x14, 0x310, 0x2
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    ##########################
-    #MCYCLEH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'hd}
-    ##########################
-    #MCYCLEH Write clear/set value 0x1f
-    csrrci x14, 0xb80, 0x0
-    csrrsi x14, 0xb80, 0x1f
-
-    #MCYCLEH read value, expected 0x1f
-    csrr x14, 0xb80
-
-    #MCYCLEH Write clear/set value 0x0
-    csrrci x14, 0xb80, 0x1f
-    csrrsi x14, 0xb80, 0x0
-
-    #MCYCLEH read value, expected 0x0
-    csrr x14, 0xb80
-
-    #MCYCLEH Write clear/set value 0x15
-    csrrci x14, 0xb80, 0xa
-    csrrsi x14, 0xb80, 0x15
-
-    #MCYCLEH read value, expected 0x15
-    csrr x14, 0xb80
-
-    #MCYCLEH Write clear/set value 0xa
-    csrrci x14, 0xb80, 0x15
-    csrrsi x14, 0xb80, 0xa
-
-    #MCYCLEH read value, expected 0xa
-    csrr x14, 0xb80
-
-    #MCYCLEH Write clear/set value 0xd
-    csrrci x14, 0xb80, 0x12
-    csrrsi x14, 0xb80, 0xd
-
-    #MCYCLEH read value, expected 0xd
-    csrr x14, 0xb80
-
-    ##########################
-    #MIE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h6}
-    ##########################
-    #MIE Write clear/set value 0x1f
-    csrrci x14, 0x304, 0x0
-    csrrsi x14, 0x304, 0x1f
-
-    #MIE read value, expected 0x1b
-    csrr x14, 0x304
-
-    #MIE Write clear/set value 0x0
-    csrrci x14, 0x304, 0x1f
-    csrrsi x14, 0x304, 0x0
-
-    #MIE read value, expected 0x0
-    csrr x14, 0x304
-
-    #MIE Write clear/set value 0x15
-    csrrci x14, 0x304, 0xa
-    csrrsi x14, 0x304, 0x15
-
-    #MIE read value, expected 0x11
-    csrr x14, 0x304
-
-    #MIE Write clear/set value 0xa
-    csrrci x14, 0x304, 0x15
-    csrrsi x14, 0x304, 0xa
-
-    #MIE read value, expected 0xa
-    csrr x14, 0x304
-
-    #MIE Write clear/set value 0x6
-    csrrci x14, 0x304, 0x19
-    csrrsi x14, 0x304, 0x6
-
-    #MIE read value, expected 0x2
-    csrr x14, 0x304
-
-    ##########################
-    #MEPC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1c}
-    ##########################
-    #MEPC Write clear/set value 0x1f
-    csrrci x14, 0x341, 0x0
-    csrrsi x14, 0x341, 0x1f
-
-    #MEPC read value, expected 0x1f
-    csrr x14, 0x341
-
-    #MEPC Write clear/set value 0x0
-    csrrci x14, 0x341, 0x1f
-    csrrsi x14, 0x341, 0x0
-
-    #MEPC read value, expected 0x0
-    csrr x14, 0x341
-
-    #MEPC Write clear/set value 0x15
-    csrrci x14, 0x341, 0xa
-    csrrsi x14, 0x341, 0x15
-
-    #MEPC read value, expected 0x15
-    csrr x14, 0x341
-
-    #MEPC Write clear/set value 0xa
-    csrrci x14, 0x341, 0x15
-    csrrsi x14, 0x341, 0xa
-
-    #MEPC read value, expected 0xa
-    csrr x14, 0x341
-
-    #MEPC Write clear/set value 0x1c
-    csrrci x14, 0x341, 0x3
-    csrrsi x14, 0x341, 0x1c
-
-    #MEPC read value, expected 0x1c
-    csrr x14, 0x341
-
-    ##########################
-    #MINSTRET testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1}
-    ##########################
-    #MINSTRET Write clear/set value 0x1f
-    csrrci x14, 0xb02, 0x0
-    csrrsi x14, 0xb02, 0x1f
-
-    #MINSTRET read value, expected 0x1f
-    csrr x14, 0xb02
-
-    #MINSTRET Write clear/set value 0x0
-    csrrci x14, 0xb02, 0x1f
-    csrrsi x14, 0xb02, 0x0
-
-    #MINSTRET read value, expected 0x0
-    csrr x14, 0xb02
-
-    #MINSTRET Write clear/set value 0x15
-    csrrci x14, 0xb02, 0xa
-    csrrsi x14, 0xb02, 0x15
-
-    #MINSTRET read value, expected 0x15
-    csrr x14, 0xb02
-
-    #MINSTRET Write clear/set value 0xa
-    csrrci x14, 0xb02, 0x15
-    csrrsi x14, 0xb02, 0xa
-
-    #MINSTRET read value, expected 0xa
-    csrr x14, 0xb02
-
-    #MINSTRET Write clear/set value 0x1
-    csrrci x14, 0xb02, 0x1e
-    csrrsi x14, 0xb02, 0x1
-
-    #MINSTRET read value, expected 0x1
-    csrr x14, 0xb02
-
-    ret

verif/tests/custom/isacov/csrrw_test.S

@@ -1,544 +0,0 @@
-# Copyright 2023 Thales DIS France SAS
-#
-# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-# You may obtain a copy of the License at https://solderpad.org/licenses/
-#
-
-csrrw:
-    #Start CSR tests: Write/Read all registers
-    #User ignored registers: MHPMEVENT3 ,MHPMEVENT4 ,MHPMEVENT5 ,MHPMEVENT6 ,MHPMEVENT7 ,MHPMEVENT8 ,MHPMEVENT9 ,MHPMEVENT10 ,MHPMEVENT11 ,MHPMEVENT12 ,MHPMEVENT13 ,MHPMEVENT14 ,MHPMEVENT15 ,MHPMEVENT16 ,MHPMEVENT17 ,MHPMEVENT18 ,MHPMEVENT19 ,MHPMEVENT20 ,MHPMEVENT21 ,MHPMEVENT22 ,MHPMEVENT23 ,MHPMEVENT24 ,MHPMEVENT25 ,MHPMEVENT26 ,MHPMEVENT27 ,MHPMEVENT28 ,MHPMEVENT29 ,MHPMEVENT30 ,MHPMEVENT31 ,PMPCFG0 ,PMPCFG1 ,PMPCFG2 ,PMPCFG3 ,PMPADDR0 ,PMPADDR1 ,PMPADDR2 ,PMPADDR3 ,PMPADDR4 ,PMPADDR5 ,PMPADDR6 ,PMPADDR7 ,PMPADDR8 ,PMPADDR9 ,PMPADDR10 ,PMPADDR11 ,PMPADDR12 ,PMPADDR13 ,PMPADDR14 ,PMPADDR15 ,ICACHE ,MHPMCOUNTER3 ,MHPMCOUNTER4 ,MHPMCOUNTER5 ,MHPMCOUNTER6 ,MHPMCOUNTER7 ,MHPMCOUNTER8 ,MHPMCOUNTER9 ,MHPMCOUNTER10 ,MHPMCOUNTER11 ,MHPMCOUNTER12 ,MHPMCOUNTER13 ,MHPMCOUNTER14 ,MHPMCOUNTER15 ,MHPMCOUNTER16 ,MHPMCOUNTER17 ,MHPMCOUNTER18 ,MHPMCOUNTER19 ,MHPMCOUNTER20 ,MHPMCOUNTER21 ,MHPMCOUNTER22 ,MHPMCOUNTER23 ,MHPMCOUNTER24 ,MHPMCOUNTER25 ,MHPMCOUNTER26 ,MHPMCOUNTER27 ,MHPMCOUNTER28 ,MHPMCOUNTER29 ,MHPMCOUNTER30 ,MHPMCOUNTER31 ,MHPMCOUNTERH3 ,MHPMCOUNTERH4 ,MHPMCOUNTERH5 ,MHPMCOUNTERH6 ,MHPMCOUNTERH7 ,MHPMCOUNTERH8 ,MHPMCOUNTERH9 ,MHPMCOUNTERH10 ,MHPMCOUNTERH11 ,MHPMCOUNTERH12 ,MHPMCOUNTERH13 ,MHPMCOUNTERH14 ,MHPMCOUNTERH15 ,MHPMCOUNTERH16 ,MHPMCOUNTERH17 ,MHPMCOUNTERH18 ,MHPMCOUNTERH19 ,MHPMCOUNTERH20 ,MHPMCOUNTERH21 ,MHPMCOUNTERH22 ,MHPMCOUNTERH23 ,MHPMCOUNTERH24 ,MHPMCOUNTERH25 ,MHPMCOUNTERH26 ,MHPMCOUNTERH27 ,MHPMCOUNTERH28 ,MHPMCOUNTERH29 ,MHPMCOUNTERH30 ,MHPMCOUNTERH31 ,
-    ##########################
-    #MSTATUS testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hd13933c1}
-    ##########################
-    #MSTATUS Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x300, x3
-
-    #MSTATUS read value, expected 0x807fffea
-    csrr x14, 0x300
-
-    #MSTATUS Write value 0x0
-    li x3, 0x0
-    csrw 0x300, x3
-
-    #MSTATUS read value, expected 0x0
-    csrr x14, 0x300
-
-    #MSTATUS Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x300, x3
-
-    #MSTATUS read value, expected 0x555540
-    csrr x14, 0x300
-
-    #MSTATUS Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x300, x3
-
-    #MSTATUS read value, expected 0x802aaaaa
-    csrr x14, 0x300
-
-    #MSTATUS Write value 0xd13933c1
-    li x3, 0xd13933c1
-    csrw 0x300, x3
-
-    #MSTATUS read value, expected 0x803933c0
-    csrr x14, 0x300
-
-    ##########################
-    #MTVEC testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h30d053db}
-    ##########################
-    #MTVEC Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x305, x3
-
-    #MTVEC read value, expected 0xffffffff
-    csrr x14, 0x305
-
-    #MTVEC Write value 0x0
-    li x3, 0x0
-    csrw 0x305, x3
-
-    #MTVEC read value, expected 0x0
-    csrr x14, 0x305
-
-    #MTVEC Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x305, x3
-
-    #MTVEC read value, expected 0x55555555
-    csrr x14, 0x305
-
-    #MTVEC Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x305, x3
-
-    #MTVEC read value, expected 0xaaaaaaaa
-    csrr x14, 0x305
-
-    #MTVEC Write value 0x30d053db
-    li x3, 0x30d053db
-    csrw 0x305, x3
-
-    #MTVEC read value, expected 0x30d053db
-    csrr x14, 0x305
-
-    ##########################
-    #MINSTRET testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hb88086b0}
-    ##########################
-    #MINSTRET Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0xb02, x3
-
-    #MINSTRET read value, expected 0xffffffff
-    csrr x14, 0xb02
-
-    #MINSTRET Write value 0x0
-    li x3, 0x0
-    csrw 0xb02, x3
-
-    #MINSTRET read value, expected 0x0
-    csrr x14, 0xb02
-
-    #MINSTRET Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0xb02, x3
-
-    #MINSTRET read value, expected 0x55555555
-    csrr x14, 0xb02
-
-    #MINSTRET Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0xb02, x3
-
-    #MINSTRET read value, expected 0xaaaaaaaa
-    csrr x14, 0xb02
-
-    #MINSTRET Write value 0xb88086b0
-    li x3, 0xb88086b0
-    csrw 0xb02, x3
-
-    #MINSTRET read value, expected 0xb88086b0
-    csrr x14, 0xb02
-
-    ##########################
-    #MIE testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hfef91206}
-    ##########################
-    #MIE Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x304, x3
-
-    #MIE read value, expected 0xbbb
-    csrr x14, 0x304
-
-    #MIE Write value 0x0
-    li x3, 0x0
-    csrw 0x304, x3
-
-    #MIE read value, expected 0x0
-    csrr x14, 0x304
-
-    #MIE Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x304, x3
-
-    #MIE read value, expected 0x111
-    csrr x14, 0x304
-
-    #MIE Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x304, x3
-
-    #MIE read value, expected 0xaaa
-    csrr x14, 0x304
-
-    #MIE Write value 0xfef91206
-    li x3, 0xfef91206
-    csrw 0x304, x3
-
-    #MIE read value, expected 0x202
-    csrr x14, 0x304
-
-    ##########################
-    #MIP testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hd3052355}
-    ##########################
-    #MIP Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x344, x3
-
-    #MIP read value, expected 0xbbb
-    csrr x14, 0x344
-
-    #MIP Write value 0x0
-    li x3, 0x0
-    csrw 0x344, x3
-
-    #MIP read value, expected 0x0
-    csrr x14, 0x344
-
-    #MIP Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x344, x3
-
-    #MIP read value, expected 0x111
-    csrr x14, 0x344
-
-    #MIP Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x344, x3
-
-    #MIP read value, expected 0xaaa
-    csrr x14, 0x344
-
-    #MIP Write value 0xd3052355
-    li x3, 0xd3052355
-    csrw 0x344, x3
-
-    #MIP read value, expected 0x311
-    csrr x14, 0x344
-
-    ##########################
-    #MEPC testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h7238da3e}
-    ##########################
-    #MEPC Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x341, x3
-
-    #MEPC read value, expected 0xffffffff
-    csrr x14, 0x341
-
-    #MEPC Write value 0x0
-    li x3, 0x0
-    csrw 0x341, x3
-
-    #MEPC read value, expected 0x0
-    csrr x14, 0x341
-
-    #MEPC Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x341, x3
-
-    #MEPC read value, expected 0x55555555
-    csrr x14, 0x341
-
-    #MEPC Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x341, x3
-
-    #MEPC read value, expected 0xaaaaaaaa
-    csrr x14, 0x341
-
-    #MEPC Write value 0x7238da3e
-    li x3, 0x7238da3e
-    csrw 0x341, x3
-
-    #MEPC read value, expected 0x7238da3e
-    csrr x14, 0x341
-
-    ##########################
-    #MCYCLEH testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h7572495f}
-    ##########################
-    #MCYCLEH Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0xb80, x3
-
-    #MCYCLEH read value, expected 0xffffffff
-    csrr x14, 0xb80
-
-    #MCYCLEH Write value 0x0
-    li x3, 0x0
-    csrw 0xb80, x3
-
-    #MCYCLEH read value, expected 0x0
-    csrr x14, 0xb80
-
-    #MCYCLEH Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0xb80, x3
-
-    #MCYCLEH read value, expected 0x55555555
-    csrr x14, 0xb80
-
-    #MCYCLEH Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0xb80, x3
-
-    #MCYCLEH read value, expected 0xaaaaaaaa
-    csrr x14, 0xb80
-
-    #MCYCLEH Write value 0x7572495f
-    li x3, 0x7572495f
-    csrw 0xb80, x3
-
-    #MCYCLEH read value, expected 0x7572495f
-    csrr x14, 0xb80
-
-    ##########################
-    #MINSTRETH testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'he0f0095e}
-    ##########################
-    #MINSTRETH Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0xb82, x3
-
-    #MINSTRETH read value, expected 0xffffffff
-    csrr x14, 0xb82
-
-    #MINSTRETH Write value 0x0
-    li x3, 0x0
-    csrw 0xb82, x3
-
-    #MINSTRETH read value, expected 0x0
-    csrr x14, 0xb82
-
-    #MINSTRETH Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0xb82, x3
-
-    #MINSTRETH read value, expected 0x55555555
-    csrr x14, 0xb82
-
-    #MINSTRETH Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0xb82, x3
-
-    #MINSTRETH read value, expected 0xaaaaaaaa
-    csrr x14, 0xb82
-
-    #MINSTRETH Write value 0xe0f0095e
-    li x3, 0xe0f0095e
-    csrw 0xb82, x3
-
-    #MINSTRETH read value, expected 0xe0f0095e
-    csrr x14, 0xb82
-
-    ##########################
-    #MCAUSE testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hd43e7a20}
-    ##########################
-    #MCAUSE Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x342, x3
-
-    #MCAUSE read value, expected 0xffffffff
-    csrr x14, 0x342
-
-    #MCAUSE Write value 0x0
-    li x3, 0x0
-    csrw 0x342, x3
-
-    #MCAUSE read value, expected 0x0
-    csrr x14, 0x342
-
-    #MCAUSE Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x342, x3
-
-    #MCAUSE read value, expected 0x55555555
-    csrr x14, 0x342
-
-    #MCAUSE Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x342, x3
-
-    #MCAUSE read value, expected 0xaaaaaaaa
-    csrr x14, 0x342
-
-    #MCAUSE Write value 0xd43e7a20
-    li x3, 0xd43e7a20
-    csrw 0x342, x3
-
-    #MCAUSE read value, expected 0xd43e7a20
-    csrr x14, 0x342
-
-    ##########################
-    #MISA testing W/R values '{'hfdbf7bfb, 'h2408404, 'h55555555, 'haaaaaaaa, 'h2f0d4a6b}
-    ##########################
-    #MISA Write value 0xfdbf7bfb
-    li x3, 0xfdbf7bfb
-    csrw 0x301, x3
-
-    #MISA read value, expected 0xc1bf7bfb
-    csrr x14, 0x301
-
-    #MISA Write value 0x2408404
-    li x3, 0x2408404
-    csrw 0x301, x3
-
-    #MISA read value, expected 0x2408404
-    csrr x14, 0x301
-
-    #MISA Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x301, x3
-
-    #MISA read value, expected 0x41555555
-    csrr x14, 0x301
-
-    #MISA Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x301, x3
-
-    #MISA read value, expected 0x82aaaaaa
-    csrr x14, 0x301
-
-    #MISA Write value 0x2f0d4a6b
-    li x3, 0x2f0d4a6b
-    csrw 0x301, x3
-
-    #MISA read value, expected 0x30d4a6b
-    csrr x14, 0x301
-
-    ##########################
-    #MCYCLE testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hbfbcce35}
-    ##########################
-    #MCYCLE Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0xb00, x3
-
-    #MCYCLE read value, expected 0xffffffff
-    csrr x14, 0xb00
-
-    #MCYCLE Write value 0x0
-    li x3, 0x0
-    csrw 0xb00, x3
-
-    #MCYCLE read value, expected 0x0
-    csrr x14, 0xb00
-
-    #MCYCLE Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0xb00, x3
-
-    #MCYCLE read value, expected 0x55555555
-    csrr x14, 0xb00
-
-    #MCYCLE Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0xb00, x3
-
-    #MCYCLE read value, expected 0xaaaaaaaa
-    csrr x14, 0xb00
-
-    #MCYCLE Write value 0xbfbcce35
-    li x3, 0xbfbcce35
-    csrw 0xb00, x3
-
-    #MCYCLE read value, expected 0xbfbcce35
-    csrr x14, 0xb00
-
-    ##########################
-    #MSCRATCH testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h5334c7f3}
-    ##########################
-    #MSCRATCH Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x340, x3
-
-    #MSCRATCH read value, expected 0xffffffff
-    csrr x14, 0x340
-
-    #MSCRATCH Write value 0x0
-    li x3, 0x0
-    csrw 0x340, x3
-
-    #MSCRATCH read value, expected 0x0
-    csrr x14, 0x340
-
-    #MSCRATCH Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x340, x3
-
-    #MSCRATCH read value, expected 0x55555555
-    csrr x14, 0x340
-
-    #MSCRATCH Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x340, x3
-
-    #MSCRATCH read value, expected 0xaaaaaaaa
-    csrr x14, 0x340
-
-    #MSCRATCH Write value 0x5334c7f3
-    li x3, 0x5334c7f3
-    csrw 0x340, x3
-
-    #MSCRATCH read value, expected 0x5334c7f3
-    csrr x14, 0x340
-
-    ##########################
-    #MSTATUSH testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h6391f8b7}
-    ##########################
-    #MSTATUSH Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x310, x3
-
-    #MSTATUSH read value, expected 0x30
-    csrr x14, 0x310
-
-    #MSTATUSH Write value 0x0
-    li x3, 0x0
-    csrw 0x310, x3
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    #MSTATUSH Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x310, x3
-
-    #MSTATUSH read value, expected 0x10
-    csrr x14, 0x310
-
-    #MSTATUSH Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x310, x3
-
-    #MSTATUSH read value, expected 0x20
-    csrr x14, 0x310
-
-    #MSTATUSH Write value 0x6391f8b7
-    li x3, 0x6391f8b7
-    csrw 0x310, x3
-
-    #MSTATUSH read value, expected 0x30
-    csrr x14, 0x310
-
-    ##########################
-    #MTVAL testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h973a306b}
-    ##########################
-    #MTVAL Write value 0xffffffff
-    li x3, 0xffffffff
-    csrw 0x343, x3
-
-    #MTVAL read value, expected 0xffffffff
-    csrr x14, 0x343
-
-    #MTVAL Write value 0x0
-    li x3, 0x0
-    csrw 0x343, x3
-
-    #MTVAL read value, expected 0x0
-    csrr x14, 0x343
-
-    #MTVAL Write value 0x55555555
-    li x3, 0x55555555
-    csrw 0x343, x3
-
-    #MTVAL read value, expected 0x55555555
-    csrr x14, 0x343
-
-    #MTVAL Write value 0xaaaaaaaa
-    li x3, 0xaaaaaaaa
-    csrw 0x343, x3
-
-    #MTVAL read value, expected 0xaaaaaaaa
-    csrr x14, 0x343
-
-    #MTVAL Write value 0x973a306b
-    li x3, 0x973a306b
-    csrw 0x343, x3
-
-    #MTVAL read value, expected 0x973a306b
-    csrr x14, 0x343
-
-    ret

verif/tests/custom/isacov/csrrwi_test.S

@@ -1,474 +0,0 @@
-# Copyright 2023 Thales DIS France SAS
-#
-# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-# You may obtain a copy of the License at https://solderpad.org/licenses/
-#
-
-csrrwi:
-    #Start CSR tests: Write/Read all registers using immediate instructions
-    #User ignored registers: MHPMEVENT3 ,MHPMEVENT4 ,MHPMEVENT5 ,MHPMEVENT6 ,MHPMEVENT7 ,MHPMEVENT8 ,MHPMEVENT9 ,MHPMEVENT10 ,MHPMEVENT11 ,MHPMEVENT12 ,MHPMEVENT13 ,MHPMEVENT14 ,MHPMEVENT15 ,MHPMEVENT16 ,MHPMEVENT17 ,MHPMEVENT18 ,MHPMEVENT19 ,MHPMEVENT20 ,MHPMEVENT21 ,MHPMEVENT22 ,MHPMEVENT23 ,MHPMEVENT24 ,MHPMEVENT25 ,MHPMEVENT26 ,MHPMEVENT27 ,MHPMEVENT28 ,MHPMEVENT29 ,MHPMEVENT30 ,MHPMEVENT31 ,PMPCFG0 ,PMPCFG1 ,PMPCFG2 ,PMPCFG3 ,PMPADDR0 ,PMPADDR1 ,PMPADDR2 ,PMPADDR3 ,PMPADDR4 ,PMPADDR5 ,PMPADDR6 ,PMPADDR7 ,PMPADDR8 ,PMPADDR9 ,PMPADDR10 ,PMPADDR11 ,PMPADDR12 ,PMPADDR13 ,PMPADDR14 ,PMPADDR15 ,ICACHE ,MHPMCOUNTER3 ,MHPMCOUNTER4 ,MHPMCOUNTER5 ,MHPMCOUNTER6 ,MHPMCOUNTER7 ,MHPMCOUNTER8 ,MHPMCOUNTER9 ,MHPMCOUNTER10 ,MHPMCOUNTER11 ,MHPMCOUNTER12 ,MHPMCOUNTER13 ,MHPMCOUNTER14 ,MHPMCOUNTER15 ,MHPMCOUNTER16 ,MHPMCOUNTER17 ,MHPMCOUNTER18 ,MHPMCOUNTER19 ,MHPMCOUNTER20 ,MHPMCOUNTER21 ,MHPMCOUNTER22 ,MHPMCOUNTER23 ,MHPMCOUNTER24 ,MHPMCOUNTER25 ,MHPMCOUNTER26 ,MHPMCOUNTER27 ,MHPMCOUNTER28 ,MHPMCOUNTER29 ,MHPMCOUNTER30 ,MHPMCOUNTER31 ,MHPMCOUNTERH3 ,MHPMCOUNTERH4 ,MHPMCOUNTERH5 ,MHPMCOUNTERH6 ,MHPMCOUNTERH7 ,MHPMCOUNTERH8 ,MHPMCOUNTERH9 ,MHPMCOUNTERH10 ,MHPMCOUNTERH11 ,MHPMCOUNTERH12 ,MHPMCOUNTERH13 ,MHPMCOUNTERH14 ,MHPMCOUNTERH15 ,MHPMCOUNTERH16 ,MHPMCOUNTERH17 ,MHPMCOUNTERH18 ,MHPMCOUNTERH19 ,MHPMCOUNTERH20 ,MHPMCOUNTERH21 ,MHPMCOUNTERH22 ,MHPMCOUNTERH23 ,MHPMCOUNTERH24 ,MHPMCOUNTERH25 ,MHPMCOUNTERH26 ,MHPMCOUNTERH27 ,MHPMCOUNTERH28 ,MHPMCOUNTERH29 ,MHPMCOUNTERH30 ,MHPMCOUNTERH31 ,
-    ##########################
-    #MSTATUSH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1e}
-    ##########################
-    #MSTATUSH Write immediate value 0x1f
-    csrrwi x14, 0x310, 0x1f
-
-    #MSTATUSH read value, expected 0x10
-    csrr x14, 0x310
-
-    #MSTATUSH Write immediate value 0x0
-    csrrwi x14, 0x310, 0x0
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    #MSTATUSH Write immediate value 0x15
-    csrrwi x14, 0x310, 0x15
-
-    #MSTATUSH read value, expected 0x10
-    csrr x14, 0x310
-
-    #MSTATUSH Write immediate value 0xa
-    csrrwi x14, 0x310, 0xa
-
-    #MSTATUSH read value, expected 0x0
-    csrr x14, 0x310
-
-    #MSTATUSH Write immediate value 0x1e
-    csrrwi x14, 0x310, 0x1e
-
-    #MSTATUSH read value, expected 0x10
-    csrr x14, 0x310
-
-    ##########################
-    #MIE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1c}
-    ##########################
-    #MIE Write immediate value 0x1f
-    csrrwi x14, 0x304, 0x1f
-
-    #MIE read value, expected 0x1b
-    csrr x14, 0x304
-
-    #MIE Write immediate value 0x0
-    csrrwi x14, 0x304, 0x0
-
-    #MIE read value, expected 0x0
-    csrr x14, 0x304
-
-    #MIE Write immediate value 0x15
-    csrrwi x14, 0x304, 0x15
-
-    #MIE read value, expected 0x11
-    csrr x14, 0x304
-
-    #MIE Write immediate value 0xa
-    csrrwi x14, 0x304, 0xa
-
-    #MIE read value, expected 0xa
-    csrr x14, 0x304
-
-    #MIE Write immediate value 0x1c
-    csrrwi x14, 0x304, 0x1c
-
-    #MIE read value, expected 0x18
-    csrr x14, 0x304
-
-    ##########################
-    #MCYCLEH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'hc}
-    ##########################
-    #MCYCLEH Write immediate value 0x1f
-    csrrwi x14, 0xb80, 0x1f
-
-    #MCYCLEH read value, expected 0x1f
-    csrr x14, 0xb80
-
-    #MCYCLEH Write immediate value 0x0
-    csrrwi x14, 0xb80, 0x0
-
-    #MCYCLEH read value, expected 0x0
-    csrr x14, 0xb80
-
-    #MCYCLEH Write immediate value 0x15
-    csrrwi x14, 0xb80, 0x15
-
-    #MCYCLEH read value, expected 0x15
-    csrr x14, 0xb80
-
-    #MCYCLEH Write immediate value 0xa
-    csrrwi x14, 0xb80, 0xa
-
-    #MCYCLEH read value, expected 0xa
-    csrr x14, 0xb80
-
-    #MCYCLEH Write immediate value 0xc
-    csrrwi x14, 0xb80, 0xc
-
-    #MCYCLEH read value, expected 0xc
-    csrr x14, 0xb80
-
-    ##########################
-    #MSCRATCH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1c}
-    ##########################
-    #MSCRATCH Write immediate value 0x1f
-    csrrwi x14, 0x340, 0x1f
-
-    #MSCRATCH read value, expected 0x1f
-    csrr x14, 0x340
-
-    #MSCRATCH Write immediate value 0x0
-    csrrwi x14, 0x340, 0x0
-
-    #MSCRATCH read value, expected 0x0
-    csrr x14, 0x340
-
-    #MSCRATCH Write immediate value 0x15
-    csrrwi x14, 0x340, 0x15
-
-    #MSCRATCH read value, expected 0x15
-    csrr x14, 0x340
-
-    #MSCRATCH Write immediate value 0xa
-    csrrwi x14, 0x340, 0xa
-
-    #MSCRATCH read value, expected 0xa
-    csrr x14, 0x340
-
-    #MSCRATCH Write immediate value 0x1c
-    csrrwi x14, 0x340, 0x1c
-
-    #MSCRATCH read value, expected 0x1c
-    csrr x14, 0x340
-
-    ##########################
-    #MINSTRET testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h14}
-    ##########################
-    #MINSTRET Write immediate value 0x1f
-    csrrwi x14, 0xb02, 0x1f
-
-    #MINSTRET read value, expected 0x1f
-    csrr x14, 0xb02
-
-    #MINSTRET Write immediate value 0x0
-    csrrwi x14, 0xb02, 0x0
-
-    #MINSTRET read value, expected 0x0
-    csrr x14, 0xb02
-
-    #MINSTRET Write immediate value 0x15
-    csrrwi x14, 0xb02, 0x15
-
-    #MINSTRET read value, expected 0x15
-    csrr x14, 0xb02
-
-    #MINSTRET Write immediate value 0xa
-    csrrwi x14, 0xb02, 0xa
-
-    #MINSTRET read value, expected 0xa
-    csrr x14, 0xb02
-
-    #MINSTRET Write immediate value 0x14
-    csrrwi x14, 0xb02, 0x14
-
-    #MINSTRET read value, expected 0x14
-    csrr x14, 0xb02
-
-    ##########################
-    #MIP testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h2}
-    ##########################
-    #MIP Write immediate value 0x1f
-    csrrwi x14, 0x344, 0x1f
-
-    #MIP read value, expected 0x1b
-    csrr x14, 0x344
-
-    #MIP Write immediate value 0x0
-    csrrwi x14, 0x344, 0x0
-
-    #MIP read value, expected 0x0
-    csrr x14, 0x344
-
-    #MIP Write immediate value 0x15
-    csrrwi x14, 0x344, 0x15
-
-    #MIP read value, expected 0x11
-    csrr x14, 0x344
-
-    #MIP Write immediate value 0xa
-    csrrwi x14, 0x344, 0xa
-
-    #MIP read value, expected 0xa
-    csrr x14, 0x344
-
-    #MIP Write immediate value 0x2
-    csrrwi x14, 0x344, 0x2
-
-    #MIP read value, expected 0x2
-    csrr x14, 0x344
-
-    ##########################
-    #MTVEC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h19}
-    ##########################
-    #MTVEC Write immediate value 0x1f
-    csrrwi x14, 0x305, 0x1f
-
-    #MTVEC read value, expected 0x1f
-    csrr x14, 0x305
-
-    #MTVEC Write immediate value 0x0
-    csrrwi x14, 0x305, 0x0
-
-    #MTVEC read value, expected 0x0
-    csrr x14, 0x305
-
-    #MTVEC Write immediate value 0x15
-    csrrwi x14, 0x305, 0x15
-
-    #MTVEC read value, expected 0x15
-    csrr x14, 0x305
-
-    #MTVEC Write immediate value 0xa
-    csrrwi x14, 0x305, 0xa
-
-    #MTVEC read value, expected 0xa
-    csrr x14, 0x305
-
-    #MTVEC Write immediate value 0x19
-    csrrwi x14, 0x305, 0x19
-
-    #MTVEC read value, expected 0x19
-    csrr x14, 0x305
-
-    ##########################
-    #MEPC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18}
-    ##########################
-    #MEPC Write immediate value 0x1f
-    csrrwi x14, 0x341, 0x1f
-
-    #MEPC read value, expected 0x1f
-    csrr x14, 0x341
-
-    #MEPC Write immediate value 0x0
-    csrrwi x14, 0x341, 0x0
-
-    #MEPC read value, expected 0x0
-    csrr x14, 0x341
-
-    #MEPC Write immediate value 0x15
-    csrrwi x14, 0x341, 0x15
-
-    #MEPC read value, expected 0x15
-    csrr x14, 0x341
-
-    #MEPC Write immediate value 0xa
-    csrrwi x14, 0x341, 0xa
-
-    #MEPC read value, expected 0xa
-    csrr x14, 0x341
-
-    #MEPC Write immediate value 0x18
-    csrrwi x14, 0x341, 0x18
-
-    #MEPC read value, expected 0x18
-    csrr x14, 0x341
-
-    ##########################
-    #MCYCLE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1}
-    ##########################
-    #MCYCLE Write immediate value 0x1f
-    csrrwi x14, 0xb00, 0x1f
-
-    #MCYCLE read value, expected 0x1f
-    csrr x14, 0xb00
-
-    #MCYCLE Write immediate value 0x0
-    csrrwi x14, 0xb00, 0x0
-
-    #MCYCLE read value, expected 0x0
-    csrr x14, 0xb00
-
-    #MCYCLE Write immediate value 0x15
-    csrrwi x14, 0xb00, 0x15
-
-    #MCYCLE read value, expected 0x15
-    csrr x14, 0xb00
-
-    #MCYCLE Write immediate value 0xa
-    csrrwi x14, 0xb00, 0xa
-
-    #MCYCLE read value, expected 0xa
-    csrr x14, 0xb00
-
-    #MCYCLE Write immediate value 0x1
-    csrrwi x14, 0xb00, 0x1
-
-    #MCYCLE read value, expected 0x1
-    csrr x14, 0xb00
-
-    ##########################
-    #MINSTRETH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h6}
-    ##########################
-    #MINSTRETH Write immediate value 0x1f
-    csrrwi x14, 0xb82, 0x1f
-
-    #MINSTRETH read value, expected 0x1f
-    csrr x14, 0xb82
-
-    #MINSTRETH Write immediate value 0x0
-    csrrwi x14, 0xb82, 0x0
-
-    #MINSTRETH read value, expected 0x0
-    csrr x14, 0xb82
-
-    #MINSTRETH Write immediate value 0x15
-    csrrwi x14, 0xb82, 0x15
-
-    #MINSTRETH read value, expected 0x15
-    csrr x14, 0xb82
-
-    #MINSTRETH Write immediate value 0xa
-    csrrwi x14, 0xb82, 0xa
-
-    #MINSTRETH read value, expected 0xa
-    csrr x14, 0xb82
-
-    #MINSTRETH Write immediate value 0x6
-    csrrwi x14, 0xb82, 0x6
-
-    #MINSTRETH read value, expected 0x6
-    csrr x14, 0xb82
-
-    ##########################
-    #MCAUSE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h7}
-    ##########################
-    #MCAUSE Write immediate value 0x1f
-    csrrwi x14, 0x342, 0x1f
-
-    #MCAUSE read value, expected 0x1f
-    csrr x14, 0x342
-
-    #MCAUSE Write immediate value 0x0
-    csrrwi x14, 0x342, 0x0
-
-    #MCAUSE read value, expected 0x0
-    csrr x14, 0x342
-
-    #MCAUSE Write immediate value 0x15
-    csrrwi x14, 0x342, 0x15
-
-    #MCAUSE read value, expected 0x15
-    csrr x14, 0x342
-
-    #MCAUSE Write immediate value 0xa
-    csrrwi x14, 0x342, 0xa
-
-    #MCAUSE read value, expected 0xa
-    csrr x14, 0x342
-
-    #MCAUSE Write immediate value 0x7
-    csrrwi x14, 0x342, 0x7
-
-    #MCAUSE read value, expected 0x7
-    csrr x14, 0x342
-
-    ##########################
-    #MISA testing W/R values '{'h1b, 'h4, 'h15, 'ha, 'h4}
-    ##########################
-    #MISA Write immediate value 0x1b
-    csrrwi x14, 0x301, 0x1b
-
-    #MISA read value, expected 0x1b
-    csrr x14, 0x301
-
-    #MISA Write immediate value 0x4
-    csrrwi x14, 0x301, 0x4
-
-    #MISA read value, expected 0x4
-    csrr x14, 0x301
-
-    #MISA Write immediate value 0x15
-    csrrwi x14, 0x301, 0x15
-
-    #MISA read value, expected 0x15
-    csrr x14, 0x301
-
-    #MISA Write immediate value 0xa
-    csrrwi x14, 0x301, 0xa
-
-    #MISA read value, expected 0xa
-    csrr x14, 0x301
-
-    #MISA Write immediate value 0x4
-    csrrwi x14, 0x301, 0x4
-
-    #MISA read value, expected 0x4
-    csrr x14, 0x301
-
-    ##########################
-    #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h3}
-    ##########################
-    #MTVAL Write immediate value 0x1f
-    csrrwi x14, 0x343, 0x1f
-
-    #MTVAL read value, expected 0x1f
-    csrr x14, 0x343
-
-    #MTVAL Write immediate value 0x0
-    csrrwi x14, 0x343, 0x0
-
-    #MTVAL read value, expected 0x0
-    csrr x14, 0x343
-
-    #MTVAL Write immediate value 0x15
-    csrrwi x14, 0x343, 0x15
-
-    #MTVAL read value, expected 0x15
-    csrr x14, 0x343
-
-    #MTVAL Write immediate value 0xa
-    csrrwi x14, 0x343, 0xa
-
-    #MTVAL read value, expected 0xa
-    csrr x14, 0x343
-
-    #MTVAL Write immediate value 0x3
-    csrrwi x14, 0x343, 0x3
-
-    #MTVAL read value, expected 0x3
-    csrr x14, 0x343
-
-    ##########################
-    #MSTATUS testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18}
-    ##########################
-    #MSTATUS Write immediate value 0x1f
-    csrrwi x14, 0x300, 0x1f
-
-    #MSTATUS read value, expected 0xa
-    csrr x14, 0x300
-
-    #MSTATUS Write immediate value 0x0
-    csrrwi x14, 0x300, 0x0
-
-    #MSTATUS read value, expected 0x0
-    csrr x14, 0x300
-
-    #MSTATUS Write immediate value 0x15
-    csrrwi x14, 0x300, 0x15
-
-    #MSTATUS read value, expected 0x0
-    csrr x14, 0x300
-
-    #MSTATUS Write immediate value 0xa
-    csrrwi x14, 0x300, 0xa
-
-    #MSTATUS read value, expected 0xa
-    csrr x14, 0x300
-
-    #MSTATUS Write immediate value 0x18
-    csrrwi x14, 0x300, 0x18
-
-    #MSTATUS read value, expected 0x8
-    csrr x14, 0x300
-
-    ret

verif/tests/testlist_csr_embedded.yaml

@@ -0,0 +1,51 @@
+# Copyright 2023 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https:#solderpad.org/licenses/
+#
+# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com)
+
+# ================================================================================
+#                  Regression test list format
+# --------------------------------------------------------------------------------
+# test            : Assembly test name
+# description     : Description of this test
+# gen_opts        : Instruction generator options
+# iterations      : Number of iterations of this test
+# no_iss          : Enable/disable ISS simulator (Optional)
+# gen_test        : Test name used by the instruction generator
+# asm_tests       : Path to directed, hand-coded assembly test file or directory
+# rtl_test        : RTL simulation test name
+# cmp_opts        : Compile options passed to the instruction generator
+# sim_opts        : Simulation options passed to the instruction generator
+# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
+# compare_opts    : Options for the RTL & ISS trace comparison
+# gcc_opts        : gcc compile options
+# --------------------------------------------------------------------------------
+
+
+- test: csr_test
+  iterations: 1
+  path_var: TESTS_PATH
+  gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc"
+  asm_tests: <path_var>/custom/csr_embedded/csr_test.S
+
+- test: csrrw_fullrandom_test
+  iterations: 0
+  path_var: TESTS_PATH
+  gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc"
+  asm_tests: <path_var>/custom/csr_embedded/csrrw_fullrandom_test.S
+
+- test: csrrw_ro_test
+  iterations: 1
+  path_var: TESTS_PATH
+  gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc"
+  asm_tests: <path_var>/custom/csr_embedded/csrrw_ro_test.S
+
+- test: csrrw_unmapped_test
+  iterations: 1
+  path_var: TESTS_PATH
+  gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc"
+  asm_tests: <path_var>/custom/csr_embedded/csrrw_unmapped_test.S

verif/tests/testlist_isacov.yaml

@@ -43,12 +43,6 @@
   gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc"
   asm_tests: <path_var>/custom/isacov/load_store_test.S
 
-- test: csr_test
-  iterations: 1
-  path_var: TESTS_PATH
-  gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc"
-  asm_tests: <path_var>/custom/isacov/csr_test.S
-
 - test: seq_test
   iterations: 1
   path_var: TESTS_PATH