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Workaround for Verilator ordering issue in OpenPiton cache adapter (#2809)
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This code hits verilator/verilator#5829 due to the use of partial assignments to dcache_rtrn_o in this always block, while reading other bits of the same packed struct elsewhere in the block.

The actual effect of this is that with a Verilator simulation, invalidation requests incoming from the coherence network are sometimes ignored breaking AMOs.

Moving the assignments to the bits read in the always block into the same always block avoids this issue.

---------

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
This commit is contained in:
Geza Lore 2025-03-06 16:16:13 +00:00 • committed by GitHub
parent aae9b2eb66
commit c511b21911
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1 changed files with 6 additions and 6 deletions
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12
core/cache_subsystem/wt_l15_adapter.sv
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@ -303,8 +303,12 @@ module wt_l15_adapter
always_comb begin : p_rtrn_logic
icache_rtrn_o.rtype = ICACHE_IFILL_ACK;
dcache_rtrn_o.rtype = DCACHE_LOAD_ACK;
icache_rtrn_vld_o = 1'b0;
dcache_rtrn_vld_o = 1'b0;
icache_rtrn_vld_o = 1'b0;
dcache_rtrn_vld_o = 1'b0;
icache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_icache_inval;
icache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_icache_all_way;
dcache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_dcache_inval;
dcache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_dcache_all_way;
if (!rtrn_fifo_empty) begin
unique case (rtrn_fifo_data.l15_returntype)
L15_LOAD_RET: begin
@ -370,13 +374,9 @@ module wt_l15_adapter
// invalidation signal mapping
assign icache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address_15_4, 4'b0000};
assign icache_rtrn_o.inv.way = rtrn_fifo_data.l15_inval_way;
assign icache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_icache_inval;
assign icache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_icache_all_way;
assign dcache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address_15_4, 4'b0000};
assign dcache_rtrn_o.inv.way = rtrn_fifo_data.l15_inval_way;
assign dcache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_dcache_inval;
assign dcache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_dcache_all_way;
fifo_v2 #(
.dtype(l15_rtrn_t),