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👾 Fix synthesis warnings

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This commit is contained in:
Florian Zaruba 2017-05-07 22:52:25 +02:00
parent 442db02e6f
commit c62683ed32
5 changed files with 73 additions and 66 deletions
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29
src/ariane.sv
View file

@ -90,10 +90,11 @@ module ariane
logic [31:0] fetch_rdata_id_if;
logic instr_valid_if_id;
logic [31:0] instr_rdata_if_id;
logic is_compressed_id_if;
logic illegal_c_insn_if_id;
logic is_compressed_if_id;
logic illegal_c_insn_id_if;
logic [63:0] pc_if_id_if;
logic [63:0] pc_id_id_if;
logic [63:0] pc_if_if_id;
logic [63:0] pc_id_if_id;
exception exception_if_id;
// --------------
// ID <-> EX
@ -119,7 +120,7 @@ module ariane
exception lsu_exception_ex_id;
// MULT
logic mult_ready_ex_id;
logic mult_valid_ex_id;
logic mult_valid_id_ex;
// CSR
logic csr_ready_ex_id;
logic csr_valid_id_ex;
@ -149,7 +150,8 @@ module ariane
// --------------
logic fetch_req_if_ex;
logic fetch_gnt_ex_if;
logic fetch_valid_if_ex;
logic fetch_valid_ex_if;
logic [31:0] fetch_rdata_ex_if;
logic fetch_err_ex_if;
logic [63:0] fetch_vaddr_if_ex;
// --------------
@ -170,7 +172,7 @@ module ariane
logic [63:0] csr_wdata_commit_csr;
logic [63:0] csr_rdata_csr_commit;
logic [63:0] pc_commit_csr;
logic [3:0] irq_enable_csr_commit;
logic [4:0] irq_enable_csr_commit;
exception csr_exception_csr_commit;
// --------------
// EX <-> CSR
@ -181,7 +183,6 @@ module ariane
assign flush_tlb = 1'b0;
assign flush = 1'b0;
assign id_ready_i = 1'b1;
assign halt_if = 1'b0;
// --------------
// NPC Generation
@ -242,15 +243,15 @@ module ariane
.lsu_ready_i ( lsu_ready_ex_id ),
.lsu_valid_o ( lsu_valid_id_ex ),
.mult_ready_i ( ),
.mult_valid_o ( ),
.mult_ready_i ( mult_ready_ex_id ),
.mult_valid_o ( mult_valid_id_ex ),
.csr_ready_i ( csr_ready_ex_id ),
.csr_valid_o ( csr_valid_id_ex ),
.trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id , csr_trans_id_ex_id} ),
.wdata_i ( {alu_result_ex_id, lsu_result_ex_id, csr_result_ex_id} ),
.ex_ex_i ( {'b0, lsu_exception_ex_id, 'b0 } ),
.ex_ex_i ( {{$bits(exception){1'b0}}, lsu_exception_ex_id, {$bits(exception){1'b0}} } ),
.wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id, csr_valid_ex_id} ),
.waddr_a_i ( waddr_a_commit_id ),
@ -295,11 +296,11 @@ module ariane
.csr_addr_o ( csr_addr_ex_csr ),
.csr_commit_i ( csr_commit_commit_ex ), // from commit
// memory management
.enable_translation_i ( enable_translation_csr_ex ), // from CSR
.enable_translation_i ( enable_translation_csr_ex ), // from CSR
.fetch_req_i ( fetch_req_if_ex ),
.fetch_gnt_o ( fetch_gnt_ex_if ),
.fetch_valid_o ( fetch_valid_ex_if ),
.fetch_err_o ( fetch_err_o ),
.fetch_err_o ( fetch_err_ex_if ),
.fetch_vaddr_i ( fetch_vaddr_if_ex ),
.fetch_rdata_o ( fetch_rdata_ex_if ),
.priv_lvl_i ( priv_lvl ), // from CSR
@ -348,8 +349,8 @@ module ariane
.csr_wdata_i ( csr_wdata_commit_csr ),
.csr_rdata_o ( csr_rdata_csr_commit ),
.pc_i ( pc_commit_csr ),
.csr_exception_o ( csr_exception_o ),
.irq_enable_o ( irq_enable_o ),
.csr_exception_o ( csr_exception_csr_commit ),
.irq_enable_o ( ),
.epc_o ( ),
.trap_vector_base_o ( ),
.priv_lvl_o ( priv_lvl ),

16
src/csr_buffer.sv
View file

@ -38,8 +38,15 @@ module csr_buffer (
input logic commit_i, // commit the pending CSR OP
// to CSR file
input logic [11:0] csr_addr_o // CSR address to commit stage
output logic [11:0] csr_addr_o // CSR address to commit stage
);
// this is a single entry store buffer for the address of the CSR
// which we are going to need in the commit stage
struct packed {
logic [11:0] csr_address;
logic valid;
} csr_reg_n, csr_reg_q;
// control logic, scoreboard signals
assign csr_trans_id_o = trans_id_i;
assign csr_valid_o = csr_reg_q.valid | csr_valid_i;
@ -47,13 +54,6 @@ module csr_buffer (
assign csr_ready_o = (csr_reg_q.valid && ~commit_i) ? 1'b0 : 1'b1;
assign csr_addr_o = csr_reg_q.csr_address;
// this is a single entry store buffer for the address of the CSR
// which we are going to need in the commit stage
struct {
logic [11:0] csr_address;
logic valid;
} csr_reg_n, csr_reg_q;
// write logic
always_comb begin : write
csr_reg_n = csr_reg_q;

90
src/csr_regfile.sv
View file

@ -185,53 +185,55 @@ module csr_regfile #(
satp_n = satp_q;
// check for correct access rights and that we are writing
if (((priv_lvl_q & csr_addr.csr_decode.priv_lvl) == csr_addr.csr_decode.priv_lvl) && csr_we) begin
case (csr_addr.address)
// sstatus is a subset of mstatus - mask it accordingly
CSR_SSTATUS: mstatus_n = csr_wdata & 64'h3fffe1fee;
// even machine mode interrupts can be visible and set-able to supervisor
// if the corresponding bit in mideleg is set
CSR_SIE: mie_n = csr_wdata & (~64'h111) & mideleg_q;
CSR_SIP: mip_n = csr_wdata & (~64'h111) & mideleg_q;
CSR_STVEC: stvec_n = {csr_wdata[63:2], 1'b0, csr_wdata[0]};
CSR_SSCRATCH: sscratch_n = csr_wdata;
CSR_SEPC: sepc_n = {csr_wdata[63:1], 1'b0};
CSR_SCAUSE: scause_n = csr_wdata;
CSR_STVAL: stval_n = csr_wdata;
// supervisor address translation and protection
CSR_SATP: satp_n = sapt_t'(csr_wdata);
if(csr_we) begin
if (((priv_lvl_q & csr_addr.csr_decode.priv_lvl) == csr_addr.csr_decode.priv_lvl)) begin
case (csr_addr.address)
// sstatus is a subset of mstatus - mask it accordingly
CSR_SSTATUS: mstatus_n = csr_wdata & 64'h3fffe1fee;
// even machine mode interrupts can be visible and set-able to supervisor
// if the corresponding bit in mideleg is set
CSR_SIE: mie_n = csr_wdata & (~64'h111) & mideleg_q;
CSR_SIP: mip_n = csr_wdata & (~64'h111) & mideleg_q;
CSR_STVEC: stvec_n = {csr_wdata[63:2], 1'b0, csr_wdata[0]};
CSR_SSCRATCH: sscratch_n = csr_wdata;
CSR_SEPC: sepc_n = {csr_wdata[63:1], 1'b0};
CSR_SCAUSE: scause_n = csr_wdata;
CSR_STVAL: stval_n = csr_wdata;
// supervisor address translation and protection
CSR_SATP: satp_n = sapt_t'(csr_wdata);
CSR_MSTATUS: begin
mstatus_n = csr_wdata;
mstatus_n.sxl = 2'b0;
mstatus_n.uxl = 2'b0;
// hardwired zero registers
mstatus_n.sd = 1'b0;
mstatus_n.xs = 2'b0;
mstatus_n.fs = 2'b0;
mstatus_n.upie = 1'b0;
mstatus_n.uie = 1'b0;
end
// machine exception delegation register
// 0 - 12 exceptions supported
CSR_MEDELEG: medeleg_n = csr_wdata & (~64'hBFF);
// machine interrupt delegation register
// we do not support user interrupt delegation
CSR_MIDELEG: mideleg_n = csr_wdata & (~64'hAAA);
CSR_MSTATUS: begin
mstatus_n = csr_wdata;
mstatus_n.sxl = 2'b0;
mstatus_n.uxl = 2'b0;
// hardwired zero registers
mstatus_n.sd = 1'b0;
mstatus_n.xs = 2'b0;
mstatus_n.fs = 2'b0;
mstatus_n.upie = 1'b0;
mstatus_n.uie = 1'b0;
end
// machine exception delegation register
// 0 - 12 exceptions supported
CSR_MEDELEG: medeleg_n = csr_wdata & (~64'hBFF);
// machine interrupt delegation register
// we do not support user interrupt delegation
CSR_MIDELEG: mideleg_n = csr_wdata & (~64'hAAA);
// mask the register so that user interrupts can never be set
CSR_MIE: mie_n = csr_wdata & (~64'h111);
CSR_MIP: mip_n = csr_wdata & (~64'h111);
// mask the register so that user interrupts can never be set
CSR_MIE: mie_n = csr_wdata & (~64'h111);
CSR_MIP: mip_n = csr_wdata & (~64'h111);
CSR_MTVEC: mtvec_n = {csr_wdata[63:2], 1'b0, csr_wdata[0]};
CSR_MSCRATCH: mscratch_n = csr_wdata;
CSR_MEPC: mepc_n = {csr_wdata[63:1], 1'b0};
CSR_MCAUSE: mcause_n = csr_wdata;
CSR_MTVAL: mtval_n = csr_wdata;
default: update_access_exception = 1'b1;
endcase
end else begin
update_access_exception = 1'b1;
CSR_MTVEC: mtvec_n = {csr_wdata[63:2], 1'b0, csr_wdata[0]};
CSR_MSCRATCH: mscratch_n = csr_wdata;
CSR_MEPC: mepc_n = {csr_wdata[63:1], 1'b0};
CSR_MCAUSE: mcause_n = csr_wdata;
CSR_MTVAL: mtval_n = csr_wdata;
default: update_access_exception = 1'b1;
endcase
end else begin
update_access_exception = 1'b1;
end
end
// update exception CSRs
// we got an exception update cause, pc and stval register

2
src/fetch_fifo.sv
View file

@ -233,8 +233,10 @@ module fetch_fifo
//----------------------------------------------------------------------------
// Assertions
//----------------------------------------------------------------------------
`ifndef SYNTHESIS
`ifndef VERILATOR
assert property (
@(posedge clk) (in_valid_i) |-> ((valid_Q[DEPTH-1] == 1'b0) || (clear_i == 1'b1)) );
`endif
`endif
endmodule

2
src/if_stage.sv
View file

@ -214,10 +214,12 @@ module if_stage (
//-------------
// Assertions
//-------------
`ifndef SYNTHESIS
`ifndef VERILATOR
// there should never be a grant when there was no request
assert property (
@(posedge clk_i) (instr_gnt_i) |-> (instr_req_o) )
else $warning("There was a grant without a request");
`endif
`endif
endmodule