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Instantiated dummy LSU, wired to MMU
This commit is contained in:
Florian Zaruba
parent
30edf32c98
commit
c64ffaffe9
3 changed files with 90 additions and 67 deletions
74
ariane.sv
74
ariane.sv
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@ -53,10 +53,7 @@ module ariane
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logic [63:0] operand_b_o;
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logic alu_ready_i;
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logic alu_valid_i;
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logic lsu_ready_i;
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logic lsu_valid_o;
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logic mult_ready_i;
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logic mult_valid_o;
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logic [4:0] waddr_a_i;
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logic [63:0] wdata_a_i;
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logic we_a_i;
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@ -69,11 +66,6 @@ module ariane
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logic if_busy_o;
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logic id_ready_i;
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logic halt_if_i;
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logic instr_req_o;
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logic [63:0] instr_addr_o;
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logic instr_gnt_i;
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logic instr_rvalid_i;
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logic [31:0] instr_rdata_i;
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logic [31:0] fetch_rdata_o;
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logic instr_valid_id_o;
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logic [31:0] instr_rdata_id_o;
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@ -98,13 +90,6 @@ module ariane
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logic fetch_valid_o;
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logic fetch_err_o;
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logic [63:0] fetch_vaddr_i;
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logic lsu_req_i;
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logic lsu_gnt_o;
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logic lsu_we_i;
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logic [7:0] lsu_be_i;
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logic lsu_err_o;
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logic [63:0] lsu_vaddr_i;
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priv_lvl_t priv_lvl_i;
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logic flag_pum_i;
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logic flag_mxr_i;
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@ -113,8 +98,14 @@ module ariane
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logic flush_tlb_i;
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logic lsu_ready_wb_i;
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logic [63:0] lsu_wdata_i;
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logic [63:0] lsu_rdata_o;
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logic data_req_o;
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logic data_gnt_i;
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logic data_err_i;
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logic [63:0] data_addr_o;
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logic data_we_o;
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logic [7:0] data_be_o;
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logic [63:0] data_wdata_o;
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logic [63:0] data_rdata_i;
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assign id_ready_i = 1'b1;
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assign halt_if_i = 1'b0;
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@ -169,7 +160,7 @@ module ariane
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.mult_valid_o ( ),
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.trans_id_i ( {alu_trans_id, lsu_trans_id} ),
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.wdata_i ( {alu_result, lsu_result} ),
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.wb_valid_i ( {alu_valid_o, l su_valid_o} ),
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.wb_valid_i ( {alu_valid_o, lsu_valid_o} ),
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.waddr_a_i ( waddr_a_i ),
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.wdata_a_i ( wdata_a_i ),
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@ -199,21 +190,30 @@ module ariane
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.lsu_result_o ( lsu_result ),
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.lsu_trans_id_o ( lsu_trans_id ),
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.lsu_valid_o ( lsu_valid_o ),
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.data_req_o ( data_req_o ),
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.data_gnt_i ( data_gnt_i ),
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.data_rvalid_i ( data_rvalid_i ),
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.data_err_i ( data_err_i ),
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.data_addr_o ( data_addr_o ),
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.data_we_o ( data_we_o ),
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.data_be_o ( data_be_o ),
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.data_wdata_o ( data_wdata_o ),
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.data_rdata_i ( data_rdata_i ),
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.mult_ready_o ( mult_ready_o ),
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.mult_valid_i ( mult_valid_i )
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);
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commit_stage commit_stage (
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.clk_i ( clk_i ),
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.rst_ni ( rst_n ),
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.priv_lvl_o ( priv_lvl_o ),
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.exception_o ( exception_o ),
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.commit_instr_i ( commit_instr_o ),
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.commit_ack_o ( commit_ack_i ),
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.waddr_a_o ( waddr_a_i ),
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.wdata_a_o ( wdata_a_i ),
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.we_a_o ( we_a_i )
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commit_stage commit_stage_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_n ),
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.priv_lvl_o ( priv_lvl_o ),
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.exception_o ( exception_o ),
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.commit_instr_i ( commit_instr_o ),
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.commit_ack_o ( commit_ack_i ),
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.waddr_a_o ( waddr_a_i ),
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.wdata_a_o ( wdata_a_i ),
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.we_a_o ( we_a_i )
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);
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mmu mmu_i (
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@ -226,15 +226,15 @@ module ariane
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.fetch_err_o ( fetch_err_o ),
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.fetch_vaddr_i ( fetch_vaddr_i ),
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.fetch_rdata_o ( fetch_rdata_o ),
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.lsu_req_i ( lsu_req_i ),
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.lsu_gnt_o ( lsu_gnt_o ),
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.lsu_valid_o ( ),
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.lsu_we_i ( lsu_we_i ),
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.lsu_be_i ( lsu_be_i ),
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.lsu_err_o ( lsu_err_o ),
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.lsu_vaddr_i ( lsu_vaddr_i ),
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.lsu_wdata_i ( lsu_wdata_i ),
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.lsu_rdata_o ( lsu_rdata_o ),
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.lsu_req_i ( data_req_o ),
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.lsu_gnt_o ( data_gnt_i ),
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.lsu_valid_o ( data_rvalid_i ),
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.lsu_we_i ( data_we_o ),
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.lsu_be_i ( data_be_o ),
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.lsu_err_o ( data_err_i ),
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.lsu_vaddr_i ( data_addr_o ),
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.lsu_wdata_i ( data_wdata_o ),
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.lsu_rdata_o ( data_rdata_i ),
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.priv_lvl_i ( priv_lvl_i ), // from CSR
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.flag_pum_i ( flag_pum_i ), // from CSR
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.flag_mxr_i ( flag_mxr_i ), // from CSR
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79
ex_stage.sv
79
ex_stage.sv
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@ -22,48 +22,71 @@ module ex_stage (
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output logic lsu_valid_o, // Output is valid
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output logic [63:0] lsu_result_o,
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output logic [TRANS_ID_BITS-1:0] lsu_trans_id_o,
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output logic data_req_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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input logic data_err_i,
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output logic [63:0] data_addr_o,
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output logic data_we_o,
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output logic [7:0] data_be_o,
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output logic [63:0] data_wdata_o,
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input logic [63:0] data_rdata_i,
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// MULT
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output logic mult_ready_o, // FU is ready
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input logic mult_valid_i // Output is valid
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);
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// ALU is a single cycle instructions, hence it is always ready
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assign alu_ready_o = 1'b1;
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assign alu_valid_o = alu_valid_i;
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assign alu_trans_id_o = trans_id_i;
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// ALU is a single cycle instructions, hence it is always ready
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assign alu_ready_o = 1'b1;
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assign alu_valid_o = alu_valid_i;
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assign alu_trans_id_o = trans_id_i;
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alu alu_i (
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.operator_i ( operator_i ),
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.operand_a_i ( operand_a_i ),
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.operand_b_i ( operand_b_i ),
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.adder_result_o ( ),
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.adder_result_ext_o ( ),
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.result_o ( alu_result_o ),
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.comparison_result_o ( comparison_result_o ),
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.is_equal_result_o ( )
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);
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alu alu_i (
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.operator_i ( operator_i ),
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.operand_a_i ( operand_a_i ),
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.operand_b_i ( operand_b_i ),
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.adder_result_o ( ),
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.adder_result_ext_o ( ),
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.result_o ( alu_result_o ),
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.comparison_result_o ( comparison_result_o ),
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.is_equal_result_o ( )
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);
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// Multiplication
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// Multiplication
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// Load-Store Unit
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// Load-Store Unit
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assign lsu_valid_o = 1'b0;
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assign lsu_trans_id_o = trans_id_i;
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logic rst_n;
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logic data_req_o;
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logic data_gnt_i;
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logic data_rvalid_i;
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logic data_err_i;
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logic [63:0] data_addr_o;
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logic data_we_o;
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logic [7:0] data_be_o;
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logic [63:0] data_wdata_o;
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logic [63:0] data_rdata_i;
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logic lsu_trans_id_i;
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exception lsu_exception_o;
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// pass through
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lsu i_lsu (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.data_req_o ( data_req_o ),
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.data_gnt_i ( data_gnt_i ),
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.data_rvalid_i ( data_rvalid_i ),
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.data_err_i ( data_err_i ),
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.data_addr_o ( data_addr_o ),
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.data_we_o ( data_we_o ),
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.data_be_o ( data_be_o ),
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.data_wdata_o ( data_wdata_o ),
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.data_rdata_i ( data_rdata_i ),
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.operator_i ( operator_i ),
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.operand_a_i ( operand_a_i ),
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.operand_b_i ( operand_b_i ),
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.lsu_ready_o ( lsu_ready_o ),
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.lsu_valid_i ( lsu_valid_i ),
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.lsu_trans_id_i ( trans_id_i ),
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.lsu_trans_id_o ( lsu_trans_id_o ),
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.lsu_valid_o ( lsu_valid_o ),
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.lsu_exception_o ( lsu_exception_o ) // TODO: exception
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);
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// pass through
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endmodule
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4
lsu.sv
4
lsu.sv
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@ -1,8 +1,8 @@
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import ariane_pkg::*;
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module lsu (
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input logic clk,
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input logic rst_n,
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input logic clk_i,
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input logic rst_ni,
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// output to data memory
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output logic data_req_o,
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