mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-22 21:27:10 -04:00
CV32A6 CSR Access Verification (#1380)
This commit is contained in:
sai krishna pidugu
GitHub
parent
16f58c8e8a
commit
c6877587ea
32 changed files with 8327 additions and 94 deletions
|
|
@ -0,0 +1,2 @@
|
|||
This directory contain RISCV CVA6 CSR access mode failing tests.
|
||||
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
csrw 0x341, x0
|
||||
csrw 0x342, x0
|
||||
|
||||
# CSR_MARCHID
|
||||
csrr x31, 3858
|
||||
li x6, 0x00000003
|
||||
bne x31, x4, csr_fail
|
||||
li x4, 0xa5a5a5a5
|
||||
csrrw x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
li x4, 0x5a5a5a5a
|
||||
csrrw x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
li x4, 0x82cebeaf
|
||||
csrrw x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
li x4, 0xa5a5a5a5
|
||||
csrrs x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
li x4, 0x5a5a5a5a
|
||||
csrrs x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
li x4, 0xd6ecdb19
|
||||
csrrs x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
li x4, 0xa5a5a5a5
|
||||
csrrc x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
li x4, 0x5a5a5a5a
|
||||
csrrc x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
li x4, 0x6a7b6028
|
||||
csrrc x14, 3858, x4
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrwi x14, 3858, 0b00101
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrwi x14, 3858, 0b11010
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrwi x14, 3858, 0b01001
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrsi x14, 3858, 0b00101
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrsi x14, 3858, 0b11010
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrsi x14, 3858, 0b01110
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrci x14, 3858, 0b00101
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrci x14, 3858, 0b11010
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrrci x14, 3858, 0b10110
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
csrr x14, 3858
|
||||
li x4, 0x00000003
|
||||
bne x4, x14, csr_fail
|
||||
|
||||
j csr_pass
|
||||
|
||||
exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
addi x2, x2,2
|
||||
beq x31, x2, next ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next:
|
||||
addi x1, x1, 0
|
||||
bne x30, x1, next_iter ## If MEPC has non-zero value then jump to next_iter
|
||||
j csr_fail
|
||||
|
||||
next_iter:
|
||||
li x2, 0 ## Initilizing 0 in x2 register where MCAUSE value is previously stored
|
||||
addi x7, x30, 4
|
||||
jr x7 ## Jump to MEPC + 4 Address location
|
||||
|
||||
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
|
||||
# CSR_MSTATUS
|
||||
li x6, 0xFFFFFFFF
|
||||
csrrw x4, 768, x6
|
||||
li x6, 0x00000000
|
||||
bne x6, x4, csr_fail
|
||||
li x6, 0x5a5a5a5a
|
||||
csrrw x4, 768, x6
|
||||
li x6, 0x8025a1a0
|
||||
bne x6, x4, csr_fail
|
||||
li x6, 0x6d11b01d
|
||||
csrrw x4, 768, x6
|
||||
li x6, 0x005a580a
|
||||
bne x6, x4, csr_fail
|
||||
li x6, 0xa5a5a5a5
|
||||
csrrs x4, 768, x6
|
||||
li x6, 0x0011b008
|
||||
bne x6, x4, csr_fail
|
||||
li x6, 0x5a5a5a5a
|
||||
csrrs x4, 768, x6
|
||||
li x6, 0x8035b1a8
|
||||
bne x6, x4, csr_fail
|
||||
li x6, 0x4eac03c8
|
||||
csrrs x4, 768, x6
|
||||
li x6, 0x807ff9aa
|
||||
bne x6, x4, csr_fail
|
||||
li x6, 0xa5a5a5a5
|
||||
csrrc x4, 768, x6
|
||||
li x6, 0x807ff9aa
|
||||
bne x6, x4, csr_fail
|
||||
li x6, 0x5a5a5a5a
|
||||
csrrc x4, 768, x6
|
||||
li x6, 0x005a580a
|
||||
bne x6, x4, csr_fail
|
||||
li x6, 0x05f68555
|
||||
csrrc x4, 768, x6
|
||||
li x6, 0x00000000
|
||||
bne x6, x4, csr_fail
|
||||
csrrwi x4, 768, 0b00101
|
||||
li x6, 0x00000000
|
||||
bne x6, x4, csr_fail
|
||||
csrrwi x4, 768, 0b11010
|
||||
li x6, 0x00000000
|
||||
bne x6, x4, csr_fail
|
||||
csrrwi x4, 768, 0b11010
|
||||
li x6, 0x0000000a
|
||||
bne x6, x4, csr_fail
|
||||
csrrsi x4, 768, 0b00101
|
||||
li x6, 0x0000000a
|
||||
bne x6, x4, csr_fail
|
||||
csrrsi x4, 768, 0b11010
|
||||
li x6, 0x0000000a
|
||||
bne x6, x4, csr_fail
|
||||
csrrsi x4, 768, 0b11111
|
||||
li x6, 0x0000000a
|
||||
bne x6, x4, csr_fail
|
||||
csrrci x4, 768, 0b00101
|
||||
li x6, 0x0000000a
|
||||
bne x6, x4, csr_fail
|
||||
csrrci x4, 768, 0b11010
|
||||
li x6, 0x0000000a
|
||||
bne x6, x4, csr_fail
|
||||
csrrci x4, 768, 0b11010
|
||||
li x6, 0x00000000
|
||||
bne x6, x4, csr_fail
|
||||
csrr x4, 768
|
||||
li x6, 0x00000000
|
||||
bne x6, x4, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
csrw 0x341, x0
|
||||
csrw 0x342, x0
|
||||
|
||||
|
||||
csrr x31, 3857
|
||||
li x30, 0x00000602
|
||||
# CSR_MVENDORID
|
||||
li x12, 0xa5a5a5a5
|
||||
csrrw x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
li x12, 0x5a5a5a5a
|
||||
csrrw x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
li x12, 0x6165b321
|
||||
csrrw x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
li x12, 0xa5a5a5a5
|
||||
csrrs x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
li x12, 0x5a5a5a5a
|
||||
csrrs x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
li x12, 0x28b3f1dd
|
||||
csrrs x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
li x12, 0xa5a5a5a5
|
||||
csrrc x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
li x12, 0x5a5a5a5a
|
||||
csrrc x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
li x12, 0x12f4a94a
|
||||
csrrc x3, 3857, x12
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrwi x3, 3857, 0b00101
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrwi x3, 3857, 0b11010
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrwi x3, 3857, 0b00000
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrsi x3, 3857, 0b00101
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrsi x3, 3857, 0b11010
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrsi x3, 3857, 0b11110
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrci x3, 3857, 0b00101
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrci x3, 3857, 0b11010
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrrci x3, 3857, 0b00110
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
csrr x3, 3857
|
||||
li x12, 0x00000602
|
||||
bne x12, x3, csr_fail
|
||||
|
||||
j csr_pass
|
||||
|
||||
exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
addi x2, x2,2
|
||||
beq x31, x2, next ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next:
|
||||
addi x1, x1, 0
|
||||
bne x30, x1, next_iter ## If MEPC has non-zero value then jump to next_iter
|
||||
j csr_fail
|
||||
|
||||
next_iter:
|
||||
li x2, 0 ## Initilizing 0 in x2 register where MCAUSE value is previously stored
|
||||
addi x7, x30, 4
|
||||
jr x7 ## Jump to MEPC + 4 Address location
|
||||
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
# CSR_PMPADDR0
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrw x14, 944, x3
|
||||
li x3, 0x00000000
|
||||
bne x3, x14, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrw x14, 944, x3
|
||||
li x3, 0xa5a5a5a4
|
||||
bne x3, x14, csr_fail
|
||||
li x3, 0x0783a3bf
|
||||
csrrw x14, 944, x3
|
||||
li x3, 0x5a5a5a5a
|
||||
bne x3, x14, csr_fail
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrs x14, 944, x3
|
||||
li x3, 0x0783a3be
|
||||
bne x3, x14, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrs x14, 944, x3
|
||||
li x3, 0xa7a7a7be
|
||||
bne x3, x14, csr_fail
|
||||
li x3, 0xa5313bdb
|
||||
csrrs x14, 944, x3
|
||||
li x3, 0xfffffffe
|
||||
bne x3, x14, csr_fail
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrc x14, 944, x3
|
||||
li x3, 0xfffffffe
|
||||
bne x3, x14, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrc x14, 944, x3
|
||||
li x3, 0x5a5a5a5a
|
||||
bne x3, x14, csr_fail
|
||||
li x3, 0xb0729c10
|
||||
csrrc x14, 944, x3
|
||||
li x3, 0x00000000
|
||||
bne x3, x14, csr_fail
|
||||
csrrwi x14, 944, 0b00101
|
||||
li x3, 0x00000000
|
||||
bne x3, x14, csr_fail
|
||||
csrrwi x14, 944, 0b11010
|
||||
li x3, 0x00000004
|
||||
bne x3, x14, csr_fail
|
||||
csrrwi x14, 944, 0b00010
|
||||
li x3, 0x0000001a
|
||||
bne x3, x14, csr_fail
|
||||
csrrsi x14, 944, 0b00101
|
||||
li x3, 0x00000002
|
||||
bne x3, x14, csr_fail
|
||||
csrrsi x14, 944, 0b11010
|
||||
li x3, 0x00000006
|
||||
bne x3, x14, csr_fail
|
||||
csrrsi x14, 944, 0b00111
|
||||
li x3, 0x0000001e
|
||||
bne x3, x14, csr_fail
|
||||
csrrci x14, 944, 0b00101
|
||||
li x3, 0x0000001e
|
||||
bne x3, x14, csr_fail
|
||||
csrrci x14, 944, 0b11010
|
||||
li x3, 0x0000001a
|
||||
bne x3, x14, csr_fail
|
||||
csrrci x14, 944, 0b10010
|
||||
li x3, 0x00000000
|
||||
bne x3, x14, csr_fail
|
||||
csrr x14, 944
|
||||
li x3, 0x00000000
|
||||
bne x3, x14, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
# CSR_PMPADDR1
|
||||
li x1, 0xa5a5a5a5
|
||||
csrrw x2, 945, x1
|
||||
li x1, 0x00000000
|
||||
bne x1, x2, csr_fail
|
||||
li x1, 0x5a5a5a5a
|
||||
csrrw x2, 945, x1
|
||||
li x1, 0xa5a5a5a4
|
||||
bne x1, x2, csr_fail
|
||||
li x1, 0x4329bde7
|
||||
csrrw x2, 945, x1
|
||||
li x1, 0x5a5a5a5a
|
||||
bne x1, x2, csr_fail
|
||||
li x1, 0xa5a5a5a5
|
||||
csrrs x2, 945, x1
|
||||
li x1, 0x4329bde6
|
||||
bne x1, x2, csr_fail
|
||||
li x1, 0x5a5a5a5a
|
||||
csrrs x2, 945, x1
|
||||
li x1, 0xe7adbde6
|
||||
bne x1, x2, csr_fail
|
||||
li x1, 0x53bc8131
|
||||
csrrs x2, 945, x1
|
||||
li x1, 0xfffffffe
|
||||
bne x1, x2, csr_fail
|
||||
li x1, 0xa5a5a5a5
|
||||
csrrc x2, 945, x1
|
||||
li x1, 0xfffffffe
|
||||
bne x1, x2, csr_fail
|
||||
li x1, 0x5a5a5a5a
|
||||
csrrc x2, 945, x1
|
||||
li x1, 0x5a5a5a5a
|
||||
bne x1, x2, csr_fail
|
||||
li x1, 0x51b45d81
|
||||
csrrc x2, 945, x1
|
||||
li x1, 0x00000000
|
||||
bne x1, x2, csr_fail
|
||||
csrrwi x2, 945, 0b00101
|
||||
li x1, 0x00000000
|
||||
bne x1, x2, csr_fail
|
||||
csrrwi x2, 945, 0b11010
|
||||
li x1, 0x00000004
|
||||
bne x1, x2, csr_fail
|
||||
csrrwi x2, 945, 0b01011
|
||||
li x1, 0x0000001a
|
||||
bne x1, x2, csr_fail
|
||||
csrrsi x2, 945, 0b00101
|
||||
li x1, 0x0000000a
|
||||
bne x1, x2, csr_fail
|
||||
csrrsi x2, 945, 0b11010
|
||||
li x1, 0x0000000e
|
||||
bne x1, x2, csr_fail
|
||||
csrrsi x2, 945, 0b11100
|
||||
li x1, 0x0000001e
|
||||
bne x1, x2, csr_fail
|
||||
csrrci x2, 945, 0b00101
|
||||
li x1, 0x0000001e
|
||||
bne x1, x2, csr_fail
|
||||
csrrci x2, 945, 0b11010
|
||||
li x1, 0x0000001a
|
||||
bne x1, x2, csr_fail
|
||||
csrrci x2, 945, 0b00001
|
||||
li x1, 0x00000000
|
||||
bne x1, x2, csr_fail
|
||||
csrr x2, 945
|
||||
li x1, 0x00000000
|
||||
bne x1, x2, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
|
||||
# CSR_PMPADDR2
|
||||
li x14, 0xa5a5a5a5
|
||||
csrrw x15, 946, x14
|
||||
li x14, 0x00000000
|
||||
bne x14, x15, csr_fail
|
||||
li x14, 0x5a5a5a5a
|
||||
csrrw x15, 946, x14
|
||||
li x14, 0xa5a5a5a4
|
||||
bne x14, x15, csr_fail
|
||||
li x14, 0x94154ed1
|
||||
csrrw x15, 946, x14
|
||||
li x14, 0x5a5a5a5a
|
||||
bne x14, x15, csr_fail
|
||||
li x14, 0xa5a5a5a5
|
||||
csrrs x15, 946, x14
|
||||
li x14, 0x94154ed0
|
||||
bne x14, x15, csr_fail
|
||||
li x14, 0x5a5a5a5a
|
||||
csrrs x15, 946, x14
|
||||
li x14, 0xb5b5eff4
|
||||
bne x14, x15, csr_fail
|
||||
li x14, 0x345b61a0
|
||||
csrrs x15, 946, x14
|
||||
li x14, 0xfffffffe
|
||||
bne x14, x15, csr_fail
|
||||
li x14, 0xa5a5a5a5
|
||||
csrrc x15, 946, x14
|
||||
li x14, 0xfffffffe
|
||||
bne x14, x15, csr_fail
|
||||
li x14, 0x5a5a5a5a
|
||||
csrrc x15, 946, x14
|
||||
li x14, 0x5a5a5a5a
|
||||
bne x14, x15, csr_fail
|
||||
li x14, 0x970406f6
|
||||
csrrc x15, 946, x14
|
||||
li x14, 0x00000000
|
||||
bne x14, x15, csr_fail
|
||||
csrrwi x15, 946, 0b00101
|
||||
li x14, 0x00000000
|
||||
bne x14, x15, csr_fail
|
||||
csrrwi x15, 946, 0b11010
|
||||
li x14, 0x00000004
|
||||
bne x14, x15, csr_fail
|
||||
csrrwi x15, 946, 0b10100
|
||||
li x14, 0x0000001a
|
||||
bne x14, x15, csr_fail
|
||||
csrrsi x15, 946, 0b00101
|
||||
li x14, 0x00000014
|
||||
bne x14, x15, csr_fail
|
||||
csrrsi x15, 946, 0b11010
|
||||
li x14, 0x00000014
|
||||
bne x14, x15, csr_fail
|
||||
csrrsi x15, 946, 0b01111
|
||||
li x14, 0x0000001e
|
||||
bne x14, x15, csr_fail
|
||||
csrrci x15, 946, 0b00101
|
||||
li x14, 0x0000001e
|
||||
bne x14, x15, csr_fail
|
||||
csrrci x15, 946, 0b11010
|
||||
li x14, 0x0000001a
|
||||
bne x14, x15, csr_fail
|
||||
csrrci x15, 946, 0b10001
|
||||
li x14, 0x00000000
|
||||
bne x14, x15, csr_fail
|
||||
csrr x15, 946
|
||||
li x14, 0x00000000
|
||||
bne x14, x15, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
|
||||
# CSR_PMPADDR3
|
||||
li x7, 0xa5a5a5a5
|
||||
csrrw x11, 947, x7
|
||||
li x7, 0x00000000
|
||||
bne x7, x11, csr_fail
|
||||
li x7, 0x5a5a5a5a
|
||||
csrrw x11, 947, x7
|
||||
li x7, 0xa5a5a5a4
|
||||
bne x7, x11, csr_fail
|
||||
li x7, 0x71a0ad7b
|
||||
csrrw x11, 947, x7
|
||||
li x7, 0x5a5a5a5a
|
||||
bne x7, x11, csr_fail
|
||||
li x7, 0xa5a5a5a5
|
||||
csrrs x11, 947, x7
|
||||
li x7, 0x71a0ad7a
|
||||
bne x7, x11, csr_fail
|
||||
li x7, 0x5a5a5a5a
|
||||
csrrs x11, 947, x7
|
||||
li x7, 0xf5a5adfe
|
||||
bne x7, x11, csr_fail
|
||||
li x7, 0x7e1bbfe7
|
||||
csrrs x11, 947, x7
|
||||
li x7, 0xfffffffe
|
||||
bne x7, x11, csr_fail
|
||||
li x7, 0xa5a5a5a5
|
||||
csrrc x11, 947, x7
|
||||
li x7, 0xfffffffe
|
||||
bne x7, x11, csr_fail
|
||||
li x7, 0x5a5a5a5a
|
||||
csrrc x11, 947, x7
|
||||
li x7, 0x5a5a5a5a
|
||||
bne x7, x11, csr_fail
|
||||
li x7, 0x313f8057
|
||||
csrrc x11, 947, x7
|
||||
li x7, 0x00000000
|
||||
bne x7, x11, csr_fail
|
||||
csrrwi x11, 947, 0b00101
|
||||
li x7, 0x00000000
|
||||
bne x7, x11, csr_fail
|
||||
csrrwi x11, 947, 0b11010
|
||||
li x7, 0x00000004
|
||||
bne x7, x11, csr_fail
|
||||
csrrwi x11, 947, 0b11101
|
||||
li x7, 0x0000001a
|
||||
bne x7, x11, csr_fail
|
||||
csrrsi x11, 947, 0b00101
|
||||
li x7, 0x0000001c
|
||||
bne x7, x11, csr_fail
|
||||
csrrsi x11, 947, 0b11010
|
||||
li x7, 0x0000001c
|
||||
bne x7, x11, csr_fail
|
||||
csrrsi x11, 947, 0b00000
|
||||
li x7, 0x0000001e
|
||||
bne x7, x11, csr_fail
|
||||
csrrci x11, 947, 0b00101
|
||||
li x7, 0x0000001e
|
||||
bne x7, x11, csr_fail
|
||||
csrrci x11, 947, 0b11010
|
||||
li x7, 0x0000001a
|
||||
bne x7, x11, csr_fail
|
||||
csrrci x11, 947, 0b00111
|
||||
li x7, 0x00000000
|
||||
bne x7, x11, csr_fail
|
||||
csrr x11, 947
|
||||
li x7, 0x00000000
|
||||
bne x7, x11, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
|
||||
# CSR_PMPADDR4
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrw x12, 948, x3
|
||||
li x3, 0x00000000
|
||||
bne x3, x12, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrw x12, 948, x3
|
||||
li x3, 0xa5a5a5a4
|
||||
bne x3, x12, csr_fail
|
||||
li x3, 0x8386e3a1
|
||||
csrrw x12, 948, x3
|
||||
li x3, 0x5a5a5a5a
|
||||
bne x3, x12, csr_fail
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrs x12, 948, x3
|
||||
li x3, 0x8386e3a0
|
||||
bne x3, x12, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrs x12, 948, x3
|
||||
li x3, 0xa7a7e7a4
|
||||
bne x3, x12, csr_fail
|
||||
li x3, 0x20406d1a
|
||||
csrrs x12, 948, x3
|
||||
li x3, 0xfffffffe
|
||||
bne x3, x12, csr_fail
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrc x12, 948, x3
|
||||
li x3, 0xfffffffe
|
||||
bne x3, x12, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrc x12, 948, x3
|
||||
li x3, 0x5a5a5a5a
|
||||
bne x3, x12, csr_fail
|
||||
li x3, 0xa39f6193
|
||||
csrrc x12, 948, x3
|
||||
li x3, 0x00000000
|
||||
bne x3, x12, csr_fail
|
||||
csrrwi x12, 948, 0b00101
|
||||
li x3, 0x00000000
|
||||
bne x3, x12, csr_fail
|
||||
csrrwi x12, 948, 0b11010
|
||||
li x3, 0x00000004
|
||||
bne x3, x12, csr_fail
|
||||
csrrwi x12, 948, 0b10001
|
||||
li x3, 0x0000001a
|
||||
bne x3, x12, csr_fail
|
||||
csrrsi x12, 948, 0b00101
|
||||
li x3, 0x00000010
|
||||
bne x3, x12, csr_fail
|
||||
csrrsi x12, 948, 0b11010
|
||||
li x3, 0x00000014
|
||||
bne x3, x12, csr_fail
|
||||
csrrsi x12, 948, 0b10110
|
||||
li x3, 0x0000001e
|
||||
bne x3, x12, csr_fail
|
||||
csrrci x12, 948, 0b00101
|
||||
li x3, 0x0000001e
|
||||
bne x3, x12, csr_fail
|
||||
csrrci x12, 948, 0b11010
|
||||
li x3, 0x0000001a
|
||||
bne x3, x12, csr_fail
|
||||
csrrci x12, 948, 0b00100
|
||||
li x3, 0x00000000
|
||||
bne x3, x12, csr_fail
|
||||
csrr x12, 948
|
||||
li x3, 0x00000000
|
||||
bne x3, x12, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
|
||||
# CSR_PMPADDR5
|
||||
li x2, 0xa5a5a5a5
|
||||
csrrw x12, 949, x2
|
||||
li x2, 0x00000000
|
||||
bne x2, x12, csr_fail
|
||||
li x2, 0x5a5a5a5a
|
||||
csrrw x12, 949, x2
|
||||
li x2, 0xa5a5a5a4
|
||||
bne x2, x12, csr_fail
|
||||
li x2, 0x2b7f410f
|
||||
csrrw x12, 949, x2
|
||||
li x2, 0x5a5a5a5a
|
||||
bne x2, x12, csr_fail
|
||||
li x2, 0xa5a5a5a5
|
||||
csrrs x12, 949, x2
|
||||
li x2, 0x2b7f410e
|
||||
bne x2, x12, csr_fail
|
||||
li x2, 0x5a5a5a5a
|
||||
csrrs x12, 949, x2
|
||||
li x2, 0xafffe5ae
|
||||
bne x2, x12, csr_fail
|
||||
li x2, 0x0fc944fe
|
||||
csrrs x12, 949, x2
|
||||
li x2, 0xfffffffe
|
||||
bne x2, x12, csr_fail
|
||||
li x2, 0xa5a5a5a5
|
||||
csrrc x12, 949, x2
|
||||
li x2, 0xfffffffe
|
||||
bne x2, x12, csr_fail
|
||||
li x2, 0x5a5a5a5a
|
||||
csrrc x12, 949, x2
|
||||
li x2, 0x5a5a5a5a
|
||||
bne x2, x12, csr_fail
|
||||
li x2, 0xb74dfaa6
|
||||
csrrc x12, 949, x2
|
||||
li x2, 0x00000000
|
||||
bne x2, x12, csr_fail
|
||||
csrrwi x12, 949, 0b00101
|
||||
li x2, 0x00000000
|
||||
bne x2, x12, csr_fail
|
||||
csrrwi x12, 949, 0b11010
|
||||
li x2, 0x00000004
|
||||
bne x2, x12, csr_fail
|
||||
csrrwi x12, 949, 0b10000
|
||||
li x2, 0x0000001a
|
||||
bne x2, x12, csr_fail
|
||||
csrrsi x12, 949, 0b00101
|
||||
li x2, 0x00000010
|
||||
bne x2, x12, csr_fail
|
||||
csrrsi x12, 949, 0b11010
|
||||
li x2, 0x00000014
|
||||
bne x2, x12, csr_fail
|
||||
csrrsi x12, 949, 0b11100
|
||||
li x2, 0x0000001e
|
||||
bne x2, x12, csr_fail
|
||||
csrrci x12, 949, 0b00101
|
||||
li x2, 0x0000001e
|
||||
bne x2, x12, csr_fail
|
||||
csrrci x12, 949, 0b11010
|
||||
li x2, 0x0000001a
|
||||
bne x2, x12, csr_fail
|
||||
csrrci x12, 949, 0b10111
|
||||
li x2, 0x00000000
|
||||
bne x2, x12, csr_fail
|
||||
csrr x12, 949
|
||||
li x2, 0x00000000
|
||||
bne x2, x12, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
|
||||
# CSR_PMPADDR6
|
||||
li x14, 0xa5a5a5a5
|
||||
csrrw x2, 950, x14
|
||||
li x14, 0x00000000
|
||||
bne x14, x2, csr_fail
|
||||
li x14, 0x5a5a5a5a
|
||||
csrrw x2, 950, x14
|
||||
li x14, 0xa5a5a5a4
|
||||
bne x14, x2, csr_fail
|
||||
li x14, 0xbda41260
|
||||
csrrw x2, 950, x14
|
||||
li x14, 0x5a5a5a5a
|
||||
bne x14, x2, csr_fail
|
||||
li x14, 0xa5a5a5a5
|
||||
csrrs x2, 950, x14
|
||||
li x14, 0xbda41260
|
||||
bne x14, x2, csr_fail
|
||||
li x14, 0x5a5a5a5a
|
||||
csrrs x2, 950, x14
|
||||
li x14, 0xbda5b7e4
|
||||
bne x14, x2, csr_fail
|
||||
li x14, 0x5df0e61a
|
||||
csrrs x2, 950, x14
|
||||
li x14, 0xfffffffe
|
||||
bne x14, x2, csr_fail
|
||||
li x14, 0xa5a5a5a5
|
||||
csrrc x2, 950, x14
|
||||
li x14, 0xfffffffe
|
||||
bne x14, x2, csr_fail
|
||||
li x14, 0x5a5a5a5a
|
||||
csrrc x2, 950, x14
|
||||
li x14, 0x5a5a5a5a
|
||||
bne x14, x2, csr_fail
|
||||
li x14, 0x28f157e4
|
||||
csrrc x2, 950, x14
|
||||
li x14, 0x00000000
|
||||
bne x14, x2, csr_fail
|
||||
csrrwi x2, 950, 0b00101
|
||||
li x14, 0x00000000
|
||||
bne x14, x2, csr_fail
|
||||
csrrwi x2, 950, 0b11010
|
||||
li x14, 0x00000004
|
||||
bne x14, x2, csr_fail
|
||||
csrrwi x2, 950, 0b01100
|
||||
li x14, 0x0000001a
|
||||
bne x14, x2, csr_fail
|
||||
csrrsi x2, 950, 0b00101
|
||||
li x14, 0x0000000c
|
||||
bne x14, x2, csr_fail
|
||||
csrrsi x2, 950, 0b11010
|
||||
li x14, 0x0000000c
|
||||
bne x14, x2, csr_fail
|
||||
csrrsi x2, 950, 0b10101
|
||||
li x14, 0x0000001e
|
||||
bne x14, x2, csr_fail
|
||||
csrrci x2, 950, 0b00101
|
||||
li x14, 0x0000001e
|
||||
bne x14, x2, csr_fail
|
||||
csrrci x2, 950, 0b11010
|
||||
li x14, 0x0000001a
|
||||
bne x14, x2, csr_fail
|
||||
csrrci x2, 950, 0b10001
|
||||
li x14, 0x00000000
|
||||
bne x14, x2, csr_fail
|
||||
csrr x2, 950
|
||||
li x14, 0x00000000
|
||||
bne x14, x2, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
|
||||
# CSR_PMPADDR7
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrw x15, 951, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x15, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrw x15, 951, x5
|
||||
li x5, 0xa5a5a5a4
|
||||
bne x5, x15, csr_fail
|
||||
li x5, 0x5ed59bfd
|
||||
csrrw x15, 951, x5
|
||||
li x5, 0x5a5a5a5a
|
||||
bne x5, x15, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrs x15, 951, x5
|
||||
li x5, 0x5ed59bfc
|
||||
bne x5, x15, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrs x15, 951, x5
|
||||
li x5, 0xfff5bffc
|
||||
bne x5, x15, csr_fail
|
||||
li x5, 0x0628e3f0
|
||||
csrrs x15, 951, x5
|
||||
li x5, 0xfffffffe
|
||||
bne x5, x15, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrc x15, 951, x5
|
||||
li x5, 0xfffffffe
|
||||
bne x5, x15, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrc x15, 951, x5
|
||||
li x5, 0x5a5a5a5a
|
||||
bne x5, x15, csr_fail
|
||||
li x5, 0x58e5c2e8
|
||||
csrrc x15, 951, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x15, csr_fail
|
||||
csrrwi x15, 951, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x15, csr_fail
|
||||
csrrwi x15, 951, 0b11010
|
||||
li x5, 0x00000004
|
||||
bne x5, x15, csr_fail
|
||||
csrrwi x15, 951, 0b11101
|
||||
li x5, 0x0000001a
|
||||
bne x5, x15, csr_fail
|
||||
csrrsi x15, 951, 0b00101
|
||||
li x5, 0x0000001c
|
||||
bne x5, x15, csr_fail
|
||||
csrrsi x15, 951, 0b11010
|
||||
li x5, 0x0000001c
|
||||
bne x5, x15, csr_fail
|
||||
csrrsi x15, 951, 0b10000
|
||||
li x5, 0x0000001e
|
||||
bne x5, x15, csr_fail
|
||||
csrrci x15, 951, 0b00101
|
||||
li x5, 0x0000001e
|
||||
bne x5, x15, csr_fail
|
||||
csrrci x15, 951, 0b11010
|
||||
li x5, 0x0000001a
|
||||
bne x5, x15, csr_fail
|
||||
csrrci x15, 951, 0b01000
|
||||
li x5, 0x00000000
|
||||
bne x5, x15, csr_fail
|
||||
csrr x15, 951
|
||||
li x5, 0x00000000
|
||||
bne x5, x15, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
# CSR_PMPCFG0
|
||||
li x1, 0xa5a5a5a5
|
||||
csrrw x8, 928, x1
|
||||
li x1, 0x00000000
|
||||
bne x1, x8, csr_fail
|
||||
li x1, 0x5a5a5a5a
|
||||
csrrw x8, 928, x1
|
||||
li x1, 0xa5a5a5a5
|
||||
bne x1, x8, csr_fail
|
||||
li x1, 0x7a6e1dbc
|
||||
csrrw x8, 928, x1
|
||||
li x1, 0x5a5a5a5a
|
||||
bne x1, x8, csr_fail
|
||||
li x1, 0xa5a5a5a5
|
||||
csrrs x8, 928, x1
|
||||
li x1, 0x7a6e1dbc
|
||||
bne x1, x8, csr_fail
|
||||
li x1, 0x5a5a5a5a
|
||||
csrrs x8, 928, x1
|
||||
li x1, 0xffefbdbd
|
||||
bne x1, x8, csr_fail
|
||||
li x1, 0x89f80ecc
|
||||
csrrs x8, 928, x1
|
||||
li x1, 0xffffffff
|
||||
bne x1, x8, csr_fail
|
||||
li x1, 0xa5a5a5a5
|
||||
csrrc x8, 928, x1
|
||||
li x1, 0xffffffff
|
||||
bne x1, x8, csr_fail
|
||||
li x1, 0x5a5a5a5a
|
||||
csrrc x8, 928, x1
|
||||
li x1, 0x5a5a5a5a
|
||||
bne x1, x8, csr_fail
|
||||
li x1, 0x045d23c7
|
||||
csrrc x8, 928, x1
|
||||
li x1, 0x00000000
|
||||
bne x1, x8, csr_fail
|
||||
csrrwi x8, 928, 0b00101
|
||||
li x1, 0x00000000
|
||||
bne x1, x8, csr_fail
|
||||
csrrwi x8, 928, 0b11010
|
||||
li x1, 0x00000005
|
||||
bne x1, x8, csr_fail
|
||||
csrrwi x8, 928, 0b10111
|
||||
li x1, 0x0000001a
|
||||
bne x1, x8, csr_fail
|
||||
csrrsi x8, 928, 0b00101
|
||||
li x1, 0x00000017
|
||||
bne x1, x8, csr_fail
|
||||
csrrsi x8, 928, 0b11010
|
||||
li x1, 0x00000017
|
||||
bne x1, x8, csr_fail
|
||||
csrrsi x8, 928, 0b00100
|
||||
li x1, 0x0000001f
|
||||
bne x1, x8, csr_fail
|
||||
csrrci x8, 928, 0b00101
|
||||
li x1, 0x0000001f
|
||||
bne x1, x8, csr_fail
|
||||
csrrci x8, 928, 0b11010
|
||||
li x1, 0x0000001a
|
||||
bne x1, x8, csr_fail
|
||||
csrrci x8, 928, 0b00001
|
||||
li x1, 0x00000000
|
||||
bne x1, x8, csr_fail
|
||||
csrr x8, 928
|
||||
li x1, 0x00000000
|
||||
bne x1, x8, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
|
||||
# CSR_PMPCFG1
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrw x9, 929, x3
|
||||
li x3, 0x00000000
|
||||
bne x3, x9, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrw x9, 929, x3
|
||||
li x3, 0xa5a5a5a5
|
||||
bne x3, x9, csr_fail
|
||||
li x3, 0xdf7a99f3
|
||||
csrrw x9, 929, x3
|
||||
li x3, 0x5a5a5a5a
|
||||
bne x3, x9, csr_fail
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrs x9, 929, x3
|
||||
li x3, 0xdf7a99f3
|
||||
bne x3, x9, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrs x9, 929, x3
|
||||
li x3, 0xffffbdf7
|
||||
bne x3, x9, csr_fail
|
||||
li x3, 0xa3347281
|
||||
csrrs x9, 929, x3
|
||||
li x3, 0xffffffff
|
||||
bne x3, x9, csr_fail
|
||||
li x3, 0xa5a5a5a5
|
||||
csrrc x9, 929, x3
|
||||
li x3, 0xffffffff
|
||||
bne x3, x9, csr_fail
|
||||
li x3, 0x5a5a5a5a
|
||||
csrrc x9, 929, x3
|
||||
li x3, 0x5a5a5a5a
|
||||
bne x3, x9, csr_fail
|
||||
li x3, 0x95109abd
|
||||
csrrc x9, 929, x3
|
||||
li x3, 0x00000000
|
||||
bne x3, x9, csr_fail
|
||||
csrrwi x9, 929, 0b00101
|
||||
li x3, 0x00000000
|
||||
bne x3, x9, csr_fail
|
||||
csrrwi x9, 929, 0b11010
|
||||
li x3, 0x00000005
|
||||
bne x3, x9, csr_fail
|
||||
csrrwi x9, 929, 0b11000
|
||||
li x3, 0x0000001a
|
||||
bne x3, x9, csr_fail
|
||||
csrrsi x9, 929, 0b00101
|
||||
li x3, 0x00000018
|
||||
bne x3, x9, csr_fail
|
||||
csrrsi x9, 929, 0b11010
|
||||
li x3, 0x0000001d
|
||||
bne x3, x9, csr_fail
|
||||
csrrsi x9, 929, 0b01011
|
||||
li x3, 0x0000001f
|
||||
bne x3, x9, csr_fail
|
||||
csrrci x9, 929, 0b00101
|
||||
li x3, 0x0000001f
|
||||
bne x3, x9, csr_fail
|
||||
csrrci x9, 929, 0b11010
|
||||
li x3, 0x0000001a
|
||||
bne x3, x9, csr_fail
|
||||
csrrci x9, 929, 0b00111
|
||||
li x3, 0x00000000
|
||||
bne x3, x9, csr_fail
|
||||
csrr x9, 929
|
||||
li x3, 0x00000000
|
||||
bne x3, x9, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
# CSR_SSTATUS
|
||||
li x15, 0xa5a5a5a5
|
||||
csrrw x7, 256, x15
|
||||
li x15, 0x00000000
|
||||
bne x15, x7, csr_fail
|
||||
li x15, 0x5a5a5a5a
|
||||
csrrw x7, 256, x15
|
||||
li x15, 0x00042120
|
||||
bne x15, x7, csr_fail
|
||||
li x15, 0xffbaa8bf
|
||||
csrrw x7, 256, x15
|
||||
li x15, 0x00084002
|
||||
bne x15, x7, csr_fail
|
||||
li x15, 0xa5a5a5a5
|
||||
csrrs x7, 256, x15
|
||||
li x15, 0x00082022
|
||||
bne x15, x7, csr_fail
|
||||
li x15, 0x5a5a5a5a
|
||||
csrrs x7, 256, x15
|
||||
li x15, 0x000c2122
|
||||
bne x15, x7, csr_fail
|
||||
li x15, 0x02fbaad0
|
||||
csrrs x7, 256, x15
|
||||
li x15, 0x000c6122
|
||||
bne x15, x7, csr_fail
|
||||
li x15, 0xa5a5a5a5
|
||||
csrrc x7, 256, x15
|
||||
li x15, 0x000c6122
|
||||
bne x15, x7, csr_fail
|
||||
li x15, 0x5a5a5a5a
|
||||
csrrc x7, 256, x15
|
||||
li x15, 0x00084002
|
||||
bne x15, x7, csr_fail
|
||||
li x15, 0x6058b29c
|
||||
csrrc x7, 256, x15
|
||||
li x15, 0x00000000
|
||||
bne x15, x7, csr_fail
|
||||
csrrwi x7, 256, 0b00101
|
||||
li x15, 0x00000000
|
||||
bne x15, x7, csr_fail
|
||||
csrrwi x7, 256, 0b11010
|
||||
li x15, 0x00000000
|
||||
bne x15, x7, csr_fail
|
||||
csrrwi x7, 256, 0b11100
|
||||
li x15, 0x00000002
|
||||
bne x15, x7, csr_fail
|
||||
csrrsi x7, 256, 0b00101
|
||||
li x15, 0x00000000
|
||||
bne x15, x7, csr_fail
|
||||
csrrsi x7, 256, 0b11010
|
||||
li x15, 0x00000000
|
||||
bne x15, x7, csr_fail
|
||||
csrrsi x7, 256, 0b00000
|
||||
li x15, 0x00000002
|
||||
bne x15, x7, csr_fail
|
||||
csrrci x7, 256, 0b00101
|
||||
li x15, 0x00000002
|
||||
bne x15, x7, csr_fail
|
||||
csrrci x7, 256, 0b11010
|
||||
li x15, 0x00000002
|
||||
bne x15, x7, csr_fail
|
||||
csrrci x7, 256, 0b00110
|
||||
li x15, 0x00000000
|
||||
bne x15, x7, csr_fail
|
||||
csrr x7, 256
|
||||
li x15, 0x00000000
|
||||
bne x15, x7, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
||||
|
||||
9
verif/tests/custom/CSR/csr_access_tests/readme.md
Normal file
9
verif/tests/custom/CSR/csr_access_tests/readme.md
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
Highlights:
|
||||
|
||||
This directory includes test programs for the RISCV CVA6 CSR Access, which are divided into Machine read-write, Machine read-only, Supervisor read-write, and Machine Mode counter CSR tests.
|
||||
|
||||
1.Each CSR access has been verified in all priviliged modes(M,S and U).
|
||||
|
||||
2.The behavior of counter CSRs has been verified in all priviliged modes (M,S and U).
|
||||
|
||||
3.Checked the behavior of the RISC-V Machine mode counter CSRs when it reaches to maximum value.
|
||||
196
verif/tests/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S
Normal file
196
verif/tests/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
|
||||
## configuring mcountern CSRs
|
||||
li x1, 0x1
|
||||
csrw 0x306, x1
|
||||
|
||||
csrw 0x341, x0 ## Writing Zero to MEPC CSR
|
||||
csrw 0x342, x0 ## Writing Zero to MCAUSE CSR
|
||||
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
li x8, 0xFFFFFFFD
|
||||
csrrw x9, 0xB00, x8 ##Configuring MCYCLE CSR with 0xFFFFFFFD
|
||||
|
||||
csrr x7, 0xC00
|
||||
|
||||
read_csr_loop:
|
||||
csrr x6, 0xC00 ## Read the current value of cycle into x6
|
||||
csrr x7, 0xC00 ## Read the current value of cycle again into x7
|
||||
bge x7, x6, next_instr11 ## if x7 > x6, jump to next instr11
|
||||
j csr_fail
|
||||
|
||||
next_instr11 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop ## If counter is not equal to zero then jump back to loop
|
||||
|
||||
j supervisor_mode_code_start
|
||||
j csr_fail
|
||||
|
||||
supervisor_mode_code_start:
|
||||
csrw 0x341, 0 ## Writing zero into MEPC CSR
|
||||
csrw 0x342, 0 ## Reading Zero into MCAUSE CSR
|
||||
|
||||
## Configuring PMP CSRs
|
||||
## set start address range t0 x7
|
||||
la x7, supervisor_code
|
||||
li x28, 0x10000
|
||||
add x7, x7, x28
|
||||
# Enable R,W,X,TOR IN PMPCFG CSR t0 x8
|
||||
li x8, 0x0F
|
||||
#set PMPADDR0 CSR with x7
|
||||
csrw 0x3B0, x7
|
||||
# set PMPCFG0 CSR with x8
|
||||
csrw 0x3A0, x8
|
||||
|
||||
## Configuring MSTATUS MPP bit to 01(supervisor mode)
|
||||
# Save the current mode in x28
|
||||
csrr x28, 0x300
|
||||
# Set the MPP field to supervisor mode (1)
|
||||
li x29, 0b1
|
||||
slli x29, x29, 11
|
||||
addi x28, x29, 0
|
||||
# Write the modified MSTATUS value back to the CSR
|
||||
csrw 0x300, x28
|
||||
## Assigning supervisor code starting PC value to MEPC CSR
|
||||
la x28, supervisor_code
|
||||
csrw 0x341, x28
|
||||
csrr x31, 0x300
|
||||
mret
|
||||
|
||||
# Supervisor code starts here
|
||||
supervisor_code:
|
||||
|
||||
csrr x10, 0xC00 ## Read the current value of cycle into x10
|
||||
csrr x11, 0xC00 ## Read the current value of cycle into x11
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR in loop
|
||||
|
||||
read_csr_loop2:
|
||||
|
||||
csrr x6, 0xC00 ## Read the current value of ccycle into x6
|
||||
csrr x7, 0xC00 ## Read the current value of cycle again into x7
|
||||
bge x7, x6, next_instr12 ## if x7 > x6, jump to next instr
|
||||
|
||||
j csr_fail
|
||||
|
||||
next_instr12 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop2 ## If counter is not equal to zero then jump back to loop
|
||||
|
||||
j user_mode_code_start
|
||||
|
||||
j csr_fail
|
||||
|
||||
|
||||
user_mode_code_start:
|
||||
la x30, user_exception_handler
|
||||
csrw stvec, x30
|
||||
|
||||
la x31, user_mode_code
|
||||
csrw sepc, x31
|
||||
|
||||
csrr x28, 0x100
|
||||
li x29, 0b0
|
||||
slli x29, x29, 8
|
||||
addi x28, x29, 0
|
||||
csrw 0x100, x28
|
||||
csrr x29, 0x100
|
||||
|
||||
sret
|
||||
|
||||
## USER Mode code starts here
|
||||
user_mode_code:
|
||||
|
||||
csrr x10, 0xC00 ## Read the current value of cycle into x0
|
||||
csrr x11, 0xC00 ## Read the current value of cycle into x10
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop3:
|
||||
csrr x6, 0xC00 ## Read the current value of cycle into x6
|
||||
csrr x7, 0xC00 ## Read the current value of cycle again into x7
|
||||
bge x7, x6, next_instr13 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr13 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop3 ## If counter is not equal to zero then jump back to loop
|
||||
j csr_pass
|
||||
|
||||
exception_handler:
|
||||
csrr x3, 0x300
|
||||
srli x3, x3, 11
|
||||
andi x3, x3, 0b11
|
||||
li x8, 3
|
||||
li x9, 1
|
||||
beqz x3, user_exception_handler
|
||||
beq x3, x8, machine_exception_handler
|
||||
beq x3, x9, supervisor_exception_handler
|
||||
|
||||
machine_exception_handler:
|
||||
csrr x6, 0x300
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr:
|
||||
csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_fail
|
||||
|
||||
supervisor_exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr1 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr1:
|
||||
beq x30, x0, csr_fail
|
||||
j user_mode_code_start
|
||||
|
||||
user_exception_handler:
|
||||
csrr x3, 0x100
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr2 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr2:
|
||||
csrw 0x342,0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_fail
|
||||
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
|
||||
## configuring mcountern CSR
|
||||
li x1, 0x4
|
||||
csrw 0x306, x1
|
||||
|
||||
csrw 0x341, x0 ## Writing Zero to MEPC CSR
|
||||
csrw 0x342, x0 ## Writing Zero to MCAUSE CSR
|
||||
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
li x8, 0xFFFFFFFD
|
||||
csrrw x9, 0xB02, x8 ## Configuring minstret to 0xFFFFFFFD
|
||||
|
||||
csrr x7, 0xB02
|
||||
csrr x8, 0xC02
|
||||
csrr x9, 0xC02
|
||||
|
||||
read_csr_loop:
|
||||
csrr x6, 0xC02 ## Read the current value of instret into x6
|
||||
csrr x7, 0xC02 ## Read the current value of instret again into x7
|
||||
bge x7, x6, next_instr11 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr11 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop ## If counter is not equal to zero then jump back to loop
|
||||
|
||||
j supervisor_mode_code_start
|
||||
j csr_fail
|
||||
|
||||
supervisor_mode_code_start:
|
||||
csrw 0x341, 0 ## Writing zero into MEPC CSR
|
||||
csrw 0x342, 0 ## Reading Zero into MCAUSE CSR
|
||||
|
||||
## Configuring PMP CSRs
|
||||
## set start address range t0 x7
|
||||
la x7, supervisor_code
|
||||
li x28, 0x10000
|
||||
add x7, x7, x28
|
||||
# Enable R,W,X,TOR IN PMPCFG CSR t0 x8
|
||||
li x8, 0x0F
|
||||
#set PMPADDR0 CSR with x7
|
||||
csrw 0x3B0, x7
|
||||
# set PMPCFG0 CSR with x8
|
||||
csrw 0x3A0, x8
|
||||
|
||||
## Configuring MSTATUS MPP bit to 01(supervisor mode)
|
||||
# Save the current mode in x28
|
||||
csrr x28, 0x300
|
||||
# Set the MPP field to supervisor mode (1)
|
||||
li x29, 0b1
|
||||
slli x29, x29, 11
|
||||
addi x28, x29, 0
|
||||
# Write the modified MSTATUS value back to the CSR
|
||||
csrw 0x300, x28
|
||||
## Assigning supervisor code starting PC value to MEPC CSR
|
||||
la x28, supervisor_code
|
||||
csrw 0x341, x28
|
||||
csrr x31, 0x300
|
||||
mret
|
||||
|
||||
# Supervisor code starts here
|
||||
supervisor_code:
|
||||
|
||||
csrr x6, 0xC02
|
||||
csrr x7, 0xC02
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop2:
|
||||
|
||||
csrr x6, 0xC02 ## Read the current value of instret into x6
|
||||
csrr x7, 0xC02 ## Read the current value of instret again into x7
|
||||
bge x7, x6, next_instr12 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr12 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop2 ## If counter is not equal to zero then jump back to loop
|
||||
|
||||
j user_mode_code_start
|
||||
j csr_fail
|
||||
|
||||
|
||||
user_mode_code_start:
|
||||
la x30, user_exception_handler
|
||||
csrw stvec, x30
|
||||
|
||||
la x31, user_mode_code
|
||||
csrw sepc, x31
|
||||
|
||||
csrr x28, 0x100
|
||||
li x29, 0b0
|
||||
slli x29, x29, 8
|
||||
addi x28, x29, 0
|
||||
csrw 0x100, x28
|
||||
csrr x29, 0x100
|
||||
|
||||
sret
|
||||
|
||||
## USER Mode code starts here
|
||||
user_mode_code:
|
||||
|
||||
csrr x6, 0xC02
|
||||
csrr x7, 0xC02
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
|
||||
read_csr_loop3:
|
||||
csrr x6, 0xC02 ## Read the current value of instret into x6
|
||||
csrr x7, 0xC02 ## Read the current value of instret again into x7
|
||||
bge x7, x6, next_instr13 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr13 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop3 ## If x28 is not equal to zero then jump back to loop
|
||||
j csr_pass
|
||||
|
||||
exception_handler:
|
||||
csrr x3, 0x300
|
||||
srli x3, x3, 11
|
||||
andi x3, x3, 0b11
|
||||
li x8, 3
|
||||
li x9, 1
|
||||
beqz x3, user_exception_handler
|
||||
beq x3, x8, machine_exception_handler
|
||||
beq x3, x9, supervisor_exception_handler
|
||||
|
||||
machine_exception_handler:
|
||||
csrr x6, 0x300
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr:
|
||||
csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_fail
|
||||
|
||||
supervisor_exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr1 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr1:
|
||||
beq x30, x0, csr_fail
|
||||
j user_mode_code_start
|
||||
|
||||
user_exception_handler:
|
||||
csrr x3, 0x100
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr2 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr2:
|
||||
csrw 0x342,0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_fail
|
||||
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
577
verif/tests/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S
Normal file
577
verif/tests/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S
Normal file
|
|
@ -0,0 +1,577 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
|
||||
csrw 0x341, x0 ## Writing Zero to MEPC CSR
|
||||
csrw 0x342, x0 ## Writing Zero to MCAUSE CSR
|
||||
|
||||
# CSR_MIMPID
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x067ec813
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x52f12149
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xd8bf28b7
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b11000
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b10100
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b10111
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrr x1, 3859
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
|
||||
|
||||
# CSR_MHARTID
|
||||
csrr x6, 3860
|
||||
li x7, 0x00000000
|
||||
bne x6, x7, csr_fail
|
||||
li x13, 0xa5a5a5a5
|
||||
csrrw x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x5a5a5a5a
|
||||
csrrw x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x5a706c83
|
||||
csrrw x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0xa5a5a5a5
|
||||
csrrs x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x5a5a5a5a
|
||||
csrrs x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x3a3e1cdf
|
||||
csrrs x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0xa5a5a5a5
|
||||
csrrc x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x5a5a5a5a
|
||||
csrrc x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x407aaf2b
|
||||
csrrc x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrwi x10, 3860, 0b00101
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrwi x10, 3860, 0b11010
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrwi x10, 3860, 0b11101
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrsi x10, 3860, 0b00101
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrsi x10, 3860, 0b11010
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrsi x10, 3860, 0b10100
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrci x10, 3860, 0b00101
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrci x10, 3860, 0b11010
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrci x10, 3860, 0b11111
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrr x10, 3860
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
|
||||
j supervisor_mode_code_start
|
||||
j csr_fail
|
||||
|
||||
supervisor_mode_code_start:
|
||||
csrw 0x341, 0 ## Writing zero into MEPC CSR
|
||||
csrw 0x342, 0 ## Reading Zero into MCAUSE CSR
|
||||
|
||||
la x28, user_mode_code_start
|
||||
csrw 0x341, x28
|
||||
|
||||
## Configuring PMP CSRs
|
||||
## set start address range t0 x7
|
||||
la x7, supervisor_code
|
||||
li x28, 0x10000
|
||||
add x7, x7, x28
|
||||
# Enable R,W,X,TOR IN PMPCFG CSR t0 x8
|
||||
li x8, 0x0F
|
||||
#set PMPADDR0 CSR with x7
|
||||
csrw 0x3B0, x7
|
||||
# set PMPCFG0 CSR with x8
|
||||
csrw 0x3A0, x8
|
||||
|
||||
## Configuring MSTATUS MPP bit to 01(supervisor mode)
|
||||
# Save the current mode in x28
|
||||
csrr x28, 0x300
|
||||
# Set the MPP field to supervisor mode (1)
|
||||
li x29, 0b1
|
||||
slli x29, x29, 11
|
||||
addi x28, x29, 0
|
||||
# Write the modified MSTATUS value back to the CSR
|
||||
csrw 0x300, x28
|
||||
## Assigning supervisor code starting PC value to MEPC CSR
|
||||
la x28, supervisor_code
|
||||
csrw 0x341, x28
|
||||
|
||||
csrr x31, 0x300
|
||||
mret
|
||||
|
||||
# Supervisor code starts here
|
||||
supervisor_code:
|
||||
|
||||
# CSR_MIMPID
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x067ec813
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x52f12149
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xd8bf28b7
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b11000
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b10100
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b10111
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrr x1, 3859
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
|
||||
# CSR_MHARTID
|
||||
csrr x6, 3860
|
||||
li x7, 0x00000000
|
||||
bne x6, x7, csr_fail
|
||||
li x13, 0xa5a5a5a5
|
||||
csrrw x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x5a5a5a5a
|
||||
csrrw x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x5a706c83
|
||||
csrrw x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0xa5a5a5a5
|
||||
csrrs x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x5a5a5a5a
|
||||
csrrs x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x3a3e1cdf
|
||||
csrrs x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0xa5a5a5a5
|
||||
csrrc x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x5a5a5a5a
|
||||
csrrc x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
li x13, 0x407aaf2b
|
||||
csrrc x10, 3860, x13
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrwi x10, 3860, 0b00101
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrwi x10, 3860, 0b11010
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrwi x10, 3860, 0b11101
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrsi x10, 3860, 0b00101
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrsi x10, 3860, 0b11010
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrsi x10, 3860, 0b10100
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrci x10, 3860, 0b00101
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrci x10, 3860, 0b11010
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrrci x10, 3860, 0b11111
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
csrr x10, 3860
|
||||
li x13, 0x00000000
|
||||
bne x13, x10, csr_fail
|
||||
|
||||
j user_mode_code_start
|
||||
|
||||
j csr_fail
|
||||
user_mode_code_start:
|
||||
|
||||
|
||||
csrw stvec, 0
|
||||
csrw sepc, 0
|
||||
|
||||
la x31, user_mode_code
|
||||
csrw sepc, x31
|
||||
csrr x28, 0x100
|
||||
|
||||
li x29, 0b0
|
||||
slli x29, x29, 8
|
||||
addi x28, x29, 0
|
||||
csrw 0x100, x28
|
||||
csrr x29, 0x100
|
||||
|
||||
sret
|
||||
|
||||
## USER Mode code starts here
|
||||
user_mode_code:
|
||||
|
||||
# CSR_MIMPID
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x067ec813
|
||||
csrrw x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x52f12149
|
||||
csrrs x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xd8bf28b7
|
||||
csrrc x1, 3859, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3859, 0b11000
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3859, 0b10100
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3859, 0b10111
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrr x1, 3859
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
|
||||
# CSR_MHARTID
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrw x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrw x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x067ec813
|
||||
csrrw x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrs x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrs x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x52f12149
|
||||
csrrs x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xa5a5a5a5
|
||||
csrrc x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0x5a5a5a5a
|
||||
csrrc x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
li x5, 0xd8bf28b7
|
||||
csrrc x1, 3860, x5
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3860, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3860, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrwi x1, 3860, 0b11000
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3860, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3860, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrsi x1, 3860, 0b10100
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3860, 0b00101
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3860, 0b11010
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrrci x1, 3860, 0b10111
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
csrr x1, 3860
|
||||
li x5, 0x00000000
|
||||
bne x5, x1, csr_fail
|
||||
|
||||
j csr_pass
|
||||
|
||||
exception_handler:
|
||||
csrr x3, 0x300
|
||||
srli x3, x3, 11
|
||||
andi x3, x3, 0b11
|
||||
li x8, 3
|
||||
li x9, 1
|
||||
beqz x3, user_exception_handler
|
||||
beq x3, x8, machine_exception_handler
|
||||
beq x3, x9, supervisor_exception_handler
|
||||
machine_exception_handler:
|
||||
|
||||
csrr x6, 0x300
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr:
|
||||
csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
addi x7, x30, 12
|
||||
jr x7 ## Jump to MEPC + 12 Address location
|
||||
j csr_fail
|
||||
supervisor_exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr1 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr1:
|
||||
csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
#Return to supervisor mode after handling the exception
|
||||
csrr x1, 0x300
|
||||
addi x7, x30, 12
|
||||
csrw 0x341, x7
|
||||
mret
|
||||
|
||||
user_exception_handler:
|
||||
csrr x3, 0x100
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr2 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr2:
|
||||
|
||||
beq x30, x0, csr_fail
|
||||
#Return to user mode after handling the exception
|
||||
|
||||
csrr x1, 0x100
|
||||
addi x7, x30, 12
|
||||
csrw 0x341, x7
|
||||
csrr x8, 0x341
|
||||
csrw 0x141, x8
|
||||
sret
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
2051
verif/tests/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S
Normal file
2051
verif/tests/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,197 @@
|
|||
#include "model_test.h"
|
||||
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
|
||||
csrw 0x341, x0 ## Writing Zero to MEPC CSR
|
||||
csrw 0x342, x0 ## Writing Zero to MCAUSE CSR
|
||||
|
||||
li x31, 0xFFFFFFFC
|
||||
csrrw x30, 0xB00, x31
|
||||
csrr x6, 0xB00 ## Read the current value of mcycle into x6
|
||||
csrr x7, 0xB00
|
||||
li x28, 10 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop:
|
||||
csrr x6, 0xB00 ## Read the current value of mcycle into x6
|
||||
csrr x7, 0xB00 ## Read the current value of mcycle again into x7
|
||||
bge x7, x6, next_instr9 ## if x7 >= x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr9 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
auipc x26, 0
|
||||
bnez x28, read_csr_loop ## If x28 is not equal to zero then jump back to loop
|
||||
|
||||
j supervisor_mode_code_start
|
||||
j csr_fail
|
||||
|
||||
supervisor_mode_code_start:
|
||||
csrw 0x341, 0 ## Writing zero into MEPC CSR
|
||||
csrw 0x342, 0 ## Reading Zero into MCAUSE CSR
|
||||
|
||||
## Configuring PMP CSRs
|
||||
## set start address range t0 x7
|
||||
la x7, supervisor_code
|
||||
li x28, 0x10000
|
||||
add x7, x7, x28
|
||||
# Enable R,W,X,TOR IN PMPCFG CSR t0 x8
|
||||
li x8, 0x0F
|
||||
#set PMPADDR0 CSR with x7
|
||||
csrw 0x3B0, x7
|
||||
# set PMPCFG0 CSR with x8
|
||||
csrw 0x3A0, x8
|
||||
|
||||
## Configuring MSTATUS MPP bit to 01(supervisor mode)
|
||||
# Save the current mode in x28
|
||||
csrr x28, 0x300
|
||||
# Set the MPP field to supervisor mode (1)
|
||||
li x29, 0b1
|
||||
slli x29, x29, 11
|
||||
addi x28, x29, 0
|
||||
# Write the modified MSTATUS value back to the CSR
|
||||
csrw 0x300, x28
|
||||
## Assigning supervisor code starting PC value to MEPC CSR
|
||||
la x28, supervisor_code
|
||||
csrw 0x341, x28
|
||||
csrr x31, 0x300
|
||||
mret
|
||||
|
||||
# Supervisor code starts here
|
||||
supervisor_code:
|
||||
csrr x8, 0xB00
|
||||
li x31, 0xFFFFFFFC
|
||||
csrrw x30, 0xB00, x31
|
||||
csrr x6, 0xB00 ## Read the current value of mcycle into x6
|
||||
csrr x7, 0xB00
|
||||
|
||||
li x28, 2 ## set x28 to the number of times to read the CSR
|
||||
li x8, 10
|
||||
read_csr_loop2:
|
||||
|
||||
csrr x6, 0xB00 ## Read the current value of mcycle into x6
|
||||
csrr x7, 0xB00 ## Read the current value of mcycle again into x7
|
||||
bgt x7, x6, next_instr98 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr98 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop2 ## If x28 is not equal to zero then jump back to loo
|
||||
j csr_fail
|
||||
|
||||
user_mode_code_start:
|
||||
|
||||
la x30, user_exception_handler
|
||||
csrw stvec, x30
|
||||
|
||||
la x31, user_mode_code
|
||||
csrw sepc, x31
|
||||
|
||||
csrr x28, 0x100
|
||||
|
||||
li x29, 0b0
|
||||
slli x29, x29, 8
|
||||
addi x28, x29, 0
|
||||
csrw 0x100, x28
|
||||
csrr x29, 0x100
|
||||
|
||||
sret
|
||||
|
||||
## USER Mode code starts here
|
||||
user_mode_code:
|
||||
|
||||
li x31, 0xFFFFFFFC
|
||||
csrrw x30, 0xB00, x31
|
||||
csrr x6, 0xB00 ## Read the current value of mcycle into x6
|
||||
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
loop:
|
||||
|
||||
read_csr_loop3:
|
||||
|
||||
csrr x6, 0xB00 ## Read the current value of mcycle into x6
|
||||
csrr x7, 0xB00 ## Read the current value of mcycle again into x7
|
||||
bgt x7, x6, next_instr99 ## if x7 >= x6, jump to next instr
|
||||
|
||||
j csr_fail
|
||||
|
||||
next_instr99 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop3 ## If x28 is not equal to zero then jump back to loop
|
||||
j csr_fail
|
||||
|
||||
exception_handler:
|
||||
csrr x3, 0x300
|
||||
srli x3, x3, 11
|
||||
andi x3, x3, 0b11
|
||||
li x8, 3
|
||||
li x9, 1
|
||||
beqz x3, user_exception_handler
|
||||
beq x3, x8, machine_exception_handler
|
||||
beq x3, x9, supervisor_exception_handler
|
||||
|
||||
machine_exception_handler:
|
||||
csrr x6, 0x300
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr:
|
||||
csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_fail
|
||||
|
||||
supervisor_exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr1 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr1:
|
||||
beq x30, x0, csr_fail
|
||||
j user_mode_code_start
|
||||
|
||||
user_exception_handler:
|
||||
csrr x3, 0x100
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr2 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr2:
|
||||
csrw 0x342,0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_pass
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
csrr x30, 0xB00
|
||||
csrr x31, 0xB80
|
||||
|
||||
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
|
||||
csrw 0x341, x0 ## Writing Zero to MEPC CSR
|
||||
csrw 0x342, x0 ## Writing Zero to MCAUSE CSR
|
||||
|
||||
li x30, 0XFFFFFFFF ## Hardcoding MCYCLE CSR value to maximum
|
||||
csrw 0xB00, x30
|
||||
|
||||
li x30, 0XFFFFFFFD
|
||||
csrw 0xB80, x30
|
||||
csrr x6, 0xB80 ## Read the current value of mcycleh into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30
|
||||
|
||||
csrr x7, 0xB80
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop:
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30 ## Hardcoding MCYCLE CSR value to maximum
|
||||
|
||||
csrr x6, 0xB80 ## Read the current value of mcycleh into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30
|
||||
|
||||
csrr x7, 0xB80 ## Read the current value of mcycleh again into x7
|
||||
bgt x7, x6, next_instr9 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr9 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop ## If x28 is not equal to zero then jump back to loop
|
||||
j supervisor_mode_code_start
|
||||
j csr_fail
|
||||
supervisor_mode_code_start:
|
||||
csrw 0x341, 0 ## Writing zero into MEPC CSR
|
||||
csrw 0x342, 0 ## Reading Zero into MCAUSE CSR
|
||||
|
||||
## Configuring PMP CSRs
|
||||
## set start address range t0 x7
|
||||
la x7, supervisor_code
|
||||
li x28, 0x10000
|
||||
add x7, x7, x28
|
||||
# Enable R,W,X,TOR IN PMPCFG CSR t0 x8
|
||||
li x8, 0x0F
|
||||
#set PMPADDR0 CSR with x7
|
||||
csrw 0x3B0, x7
|
||||
# set PMPCFG0 CSR with x8
|
||||
csrw 0x3A0, x8
|
||||
|
||||
## Configuring MSTATUS MPP bit to 01(supervisor mode)
|
||||
# Save the current mode in x28
|
||||
csrr x28, 0x300
|
||||
# Set the MPP field to supervisor mode (1)
|
||||
li x29, 0b1
|
||||
slli x29, x29, 11
|
||||
addi x28, x29, 0
|
||||
# Write the modified MSTATUS value back to the CSR
|
||||
csrw 0x300, x28
|
||||
## Assigning supervisor code starting PC value to MEPC CSR
|
||||
la x28, supervisor_code
|
||||
csrw 0x341, x28
|
||||
|
||||
csrr x31, 0x300
|
||||
mret
|
||||
|
||||
# Supervisor code starts here
|
||||
supervisor_code:
|
||||
|
||||
csrr x31, 0xB80
|
||||
li x30, 0XFFFFFFFF ## Hardcoding MCYCLE CSR value to maximum
|
||||
csrw 0xB00, x30
|
||||
|
||||
li x30, 0XFFFFFFFD
|
||||
csrw 0xB80, x30
|
||||
csrr x6, 0xB80 ## Read the current value of mcycleh into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30
|
||||
|
||||
csrr x7, 0xB80
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop2:
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30
|
||||
csrr x6, 0xB80 ## Read the current value of mcycleh into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30
|
||||
csrr x7, 0xB80 ## Read the current value of mcycleh again into x7
|
||||
|
||||
bgt x7, x6, next_instr10 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr10 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop2 ## If x28 is not equal to zero then jump back to loop
|
||||
j csr_fail
|
||||
|
||||
user_mode_code_start:
|
||||
|
||||
la x30, user_exception_handler
|
||||
csrw stvec, x30
|
||||
|
||||
la x31, user_mode_code
|
||||
csrw sepc, x31
|
||||
|
||||
csrr x28, 0x100
|
||||
|
||||
li x29, 0b0
|
||||
slli x29, x29, 8
|
||||
addi x28, x29, 0
|
||||
csrw 0x100, x28
|
||||
csrr x29, 0x100
|
||||
|
||||
sret
|
||||
|
||||
## USER Mode code starts here
|
||||
user_mode_code:
|
||||
|
||||
csrr x31, 0xB80
|
||||
|
||||
li x30, 0XFFFFFFFF ## Hardcoding MCYCLE CSR value to maximum
|
||||
csrw 0xB00, x30
|
||||
|
||||
li x30, 0XFFFFFFFD
|
||||
csrw 0xB80, x30
|
||||
csrr x6, 0xB80 ## Read the current value of mcycleh into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30
|
||||
|
||||
csrr x7, 0xB80
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop3:
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30
|
||||
|
||||
csrr x6, 0xB80 ## Read the current value of mcycleh into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB00, x30
|
||||
|
||||
csrr x7, 0xB80 ## Read the current value of mcycleh again into x7
|
||||
bgt x7, x6, next_instr11 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr11:
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop3 ## If x28 is not equal to zero then jump back to loop
|
||||
j csr_fail
|
||||
|
||||
exception_handler:
|
||||
csrr x3, 0x300
|
||||
srli x3, x3, 11
|
||||
andi x3, x3, 0b11
|
||||
li x8, 3
|
||||
li x9, 1
|
||||
beqz x3, user_exception_handler
|
||||
beq x3, x8, machine_exception_handler
|
||||
beq x3, x9, supervisor_exception_handler
|
||||
|
||||
machine_exception_handler:
|
||||
csrr x6, 0x300
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr:
|
||||
csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_fail
|
||||
|
||||
supervisor_exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr1 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr1:
|
||||
beq x30, x0, csr_fail
|
||||
j user_mode_code_start
|
||||
|
||||
user_exception_handler:
|
||||
csrr x3, 0x100
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr2 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr2:
|
||||
csrw 0x342,0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_pass
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
#include "model_test.h"
|
||||
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
|
||||
csrw 0x341, x0 ## Writing Zero to MEPC CSR
|
||||
csrw 0x342, x0 ## Writing Zero to MCAUSE CSR
|
||||
|
||||
li x31, 0xFFFFFFFC
|
||||
csrrw x30, 0xB02, x31
|
||||
csrr x6, 0xB02 ## Read the current value of minstret into x6
|
||||
|
||||
li x28, 10 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop:
|
||||
csrr x6, 0xB02 ## Read the current value of minstret into x6
|
||||
csrr x7, 0xB02 ## Read the current value of minstret again into x7
|
||||
bge x7, x6, next_instr9 ## if x7 >= x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr9 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop ## If x28 is not equal to zero then jump back to loop
|
||||
|
||||
j supervisor_mode_code_start
|
||||
j csr_fail
|
||||
|
||||
supervisor_mode_code_start:
|
||||
csrw 0x341, 0 ## Writing zero into MEPC CSR
|
||||
csrw 0x342, 0 ## Reading Zero into MCAUSE CSR
|
||||
|
||||
## Configuring PMP CSRs
|
||||
## set start address range t0 x7
|
||||
la x7, supervisor_code
|
||||
li x28, 0x10000
|
||||
add x7, x7, x28
|
||||
# Enable R,W,X,TOR IN PMPCFG CSR t0 x8
|
||||
li x8, 0x0F
|
||||
#set PMPADDR0 CSR with x7
|
||||
csrw 0x3B0, x7
|
||||
# set PMPCFG0 CSR with x8
|
||||
csrw 0x3A0, x8
|
||||
|
||||
## Configuring MSTATUS MPP bit to 01(supervisor mode)
|
||||
# Save the current mode in x28
|
||||
csrr x28, 0x300
|
||||
# Set the MPP field to supervisor mode (1)
|
||||
li x29, 0b1
|
||||
slli x29, x29, 11
|
||||
addi x28, x29, 0
|
||||
# Write the modified MSTATUS value back to the CSR
|
||||
csrw 0x300, x28
|
||||
## Assigning supervisor code starting PC value to MEPC CSR
|
||||
la x28, supervisor_code
|
||||
csrw 0x341, x28
|
||||
csrr x31, 0x300
|
||||
mret
|
||||
|
||||
# Supervisor code starts here
|
||||
supervisor_code:
|
||||
li x31, 0xFFFFFFFC
|
||||
csrrw x30, 0xB02, x31
|
||||
csrr x6, 0xB02 ## Read the current value of minstret into x6
|
||||
|
||||
li x28, 2 ## set x28 to the number of times to read the CSR
|
||||
li x8, 10
|
||||
read_csr_loop2:
|
||||
|
||||
addi x6,x26, 8
|
||||
csrr x6, 0xB02 ## Read the current value of minstret into x6
|
||||
csrr x7, 0xB02 ## Read the current value of minstret again into x7
|
||||
csrr x9, 0x342
|
||||
beq x8, x9, user_mode_code_start
|
||||
bgt x7, x6, next_instr98 ## if x7 >= x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr98 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
auipc x26, 0
|
||||
bnez x28, read_csr_loop2 ## If x28 is not equal to zero then jump back to loo
|
||||
j csr_fail
|
||||
|
||||
user_mode_code_start:
|
||||
|
||||
la x30, user_exception_handler
|
||||
csrw stvec, x30
|
||||
|
||||
la x31, user_mode_code
|
||||
csrw sepc, x31
|
||||
|
||||
csrr x28, 0x100
|
||||
|
||||
li x29, 0b0
|
||||
slli x29, x29, 8
|
||||
addi x28, x29, 0
|
||||
csrw 0x100, x28
|
||||
csrr x29, 0x100
|
||||
|
||||
sret
|
||||
|
||||
## USER Mode code starts here
|
||||
user_mode_code:
|
||||
|
||||
li x31, 0xFFFFFFFC
|
||||
csrrw x30, 0xB02, x31
|
||||
csrr x6, 0xB02 ## Read the current value of minstret into x6
|
||||
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
loop:
|
||||
|
||||
read_csr_loop3:
|
||||
|
||||
csrr x6, 0xB02 ## Read the current value of minstret into x6
|
||||
csrr x7, 0xB02 ## Read the current value of minstret again into x7
|
||||
csrr x9, 0x342
|
||||
beq x8, x9, user_mode_code_start
|
||||
bgt x7, x6, next_instr99 ## if x7 >= x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr99 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
auipc x26, 0
|
||||
bnez x28, read_csr_loop2 ## If x28 is not equal to zero then jump back to loo
|
||||
|
||||
j csr_fail
|
||||
|
||||
exception_handler:
|
||||
csrr x3, 0x300
|
||||
srli x3, x3, 11
|
||||
andi x3, x3, 0b11
|
||||
li x8, 3
|
||||
li x9, 1
|
||||
beqz x3, user_exception_handler
|
||||
beq x3, x8, machine_exception_handler
|
||||
beq x3, x9, supervisor_exception_handler
|
||||
|
||||
machine_exception_handler:
|
||||
csrr x6, 0x300
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr:
|
||||
csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_fail
|
||||
|
||||
supervisor_exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr1 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr1:
|
||||
beq x30, x0, csr_fail
|
||||
j user_mode_code_start
|
||||
|
||||
user_exception_handler:
|
||||
csrr x3, 0x100
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr2 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr2:
|
||||
csrw 0x342,0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_pass
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
csrr x30, 0xB02
|
||||
csrr x31, 0xB82
|
||||
|
||||
|
||||
la x6, exception_handler
|
||||
csrw mtvec, x6 ## Load the address of the exception handler into MTVEC
|
||||
|
||||
csrw 0x341, x0 ## Writing Zero to MEPC CSR
|
||||
csrw 0x342, x0 ## Writing Zero to MCAUSE CSR
|
||||
|
||||
li x30, 0XFFFFFFFF ## Hardcoding MINSTRET CSR value to maximum
|
||||
csrw 0xB02, x30
|
||||
|
||||
li x30, 0XFFFFFFFD
|
||||
csrw 0xB82, x30
|
||||
csrr x6, 0xB82 ## Read the current value of minstreth into x6
|
||||
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30
|
||||
|
||||
csrr x7, 0xB82
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop:
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30 ## Hardcoding minstreth CSR value to maximum
|
||||
csrr x6, 0xB82 ## Read the current value of minstreth into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30
|
||||
csrr x7, 0xB82 ## Read the current value of minstreth again into x7
|
||||
|
||||
bgt x7, x6, next_instr9 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr9 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop ## If x28 is not equal to zero then jump back to loop
|
||||
j supervisor_mode_code_start
|
||||
j csr_fail
|
||||
|
||||
supervisor_mode_code_start:
|
||||
csrw 0x341, 0 ## Writing zero into MEPC CSR
|
||||
csrw 0x342, 0 ## Reading Zero into MCAUSE CSR
|
||||
|
||||
## Configuring PMP CSRs
|
||||
## set start address range t0 x7
|
||||
la x7, supervisor_code
|
||||
li x28, 0x10000
|
||||
add x7, x7, x28
|
||||
# Enable R,W,X,TOR IN PMPCFG CSR t0 x8
|
||||
li x8, 0x0F
|
||||
#set PMPADDR0 CSR with x7
|
||||
csrw 0x3B0, x7
|
||||
# set PMPCFG0 CSR with x8
|
||||
csrw 0x3A0, x8
|
||||
|
||||
## Configuring MSTATUS MPP bit to 01(supervisor mode)
|
||||
# Save the current mode in x28
|
||||
csrr x28, 0x300
|
||||
# Set the MPP field to supervisor mode (1)
|
||||
li x29, 0b1
|
||||
slli x29, x29, 11
|
||||
addi x28, x29, 0
|
||||
# Write the modified MSTATUS value back to the CSR
|
||||
csrw 0x300, x28
|
||||
## Assigning supervisor code starting PC value to MEPC CSR
|
||||
la x28, supervisor_code
|
||||
csrw 0x341, x28
|
||||
csrr x31, 0x300
|
||||
mret
|
||||
|
||||
# Supervisor code starts here
|
||||
supervisor_code:
|
||||
|
||||
csrr x31, 0xB82
|
||||
li x30, 0XFFFFFFFF ## Hardcoding MINSTRET CSR value to maximum
|
||||
csrw 0xB02, x30
|
||||
|
||||
li x30, 0XFFFFFFFD
|
||||
csrw 0xB82, x30
|
||||
csrr x6, 0xB82 ## Read the current value of minstreth into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30
|
||||
|
||||
csrr x7, 0xB82
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop2:
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30
|
||||
csrr x6, 0xB82 ## Read the current value of minstreth into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30
|
||||
csrr x7, 0xB82 ## Read the current value of minstreth again into x7
|
||||
|
||||
bgt x7, x6, next_instr10 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr10 :
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop2 ## If x28 is not equal to zero then jump back to loop
|
||||
j csr_fail
|
||||
|
||||
user_mode_code_start:
|
||||
|
||||
la x30, user_exception_handler
|
||||
csrw stvec, x30
|
||||
|
||||
la x31, user_mode_code
|
||||
csrw sepc, x31
|
||||
|
||||
csrr x28, 0x100
|
||||
|
||||
li x29, 0b0
|
||||
slli x29, x29, 8
|
||||
addi x28, x29, 0
|
||||
csrw 0x100, x28
|
||||
csrr x29, 0x100
|
||||
|
||||
sret
|
||||
|
||||
## USER Mode code starts here
|
||||
user_mode_code:
|
||||
|
||||
|
||||
csrr x31, 0xB82
|
||||
|
||||
li x30, 0XFFFFFFFF ## Hardcoding MINSTRET CSR value to maximum
|
||||
csrw 0xB02, x30
|
||||
|
||||
li x30, 0XFFFFFFFD
|
||||
csrw 0xB82, x30
|
||||
csrr x6, 0xB82 ## Read the current value of minstreth into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30
|
||||
|
||||
csrr x7, 0xB82
|
||||
li x28, 5 ## set x28 to the number of times to read the CSR
|
||||
|
||||
read_csr_loop3:
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30
|
||||
csrr x6, 0xB82 ## Read the current value of minstreth into x6
|
||||
|
||||
li x30, 0XFFFFFFFF
|
||||
csrw 0xB02, x30
|
||||
csrr x7, 0xB82 ## Read the current value of minstreth again into x7
|
||||
|
||||
bgt x7, x6, next_instr11 ## if x7 > x6, jump to next instr
|
||||
j csr_fail
|
||||
|
||||
next_instr11:
|
||||
addi x28, x28, -1 ## Decrement counter value
|
||||
bnez x28, read_csr_loop3 ## If x28 is not equal to zero then jump back to loop
|
||||
j csr_fail
|
||||
|
||||
exception_handler:
|
||||
csrr x3, 0x300
|
||||
srli x3, x3, 11
|
||||
andi x3, x3, 0b11
|
||||
li x8, 3
|
||||
li x9, 1
|
||||
beqz x3, user_exception_handler
|
||||
beq x3, x8, machine_exception_handler
|
||||
beq x3, x9, supervisor_exception_handler
|
||||
|
||||
machine_exception_handler:
|
||||
csrr x6, 0x300
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr:
|
||||
csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_fail
|
||||
|
||||
supervisor_exception_handler:
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr1 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr1:
|
||||
beq x30, x0, csr_fail
|
||||
j user_mode_code_start
|
||||
|
||||
user_exception_handler:
|
||||
csrr x3, 0x100
|
||||
csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
|
||||
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception
|
||||
|
||||
li x2 ,2
|
||||
beq x31, x2, next_instr2 ## Checking is exception is expected exception or not
|
||||
j csr_fail
|
||||
|
||||
next_instr2:
|
||||
csrw 0x342,0 ## Reseting MCAUSE value to 0 before handling new exception
|
||||
beq x30, x0, csr_fail
|
||||
j csr_pass
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, t5
|
||||
self_loop: j self_loop
|
||||
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
||||
1586
verif/tests/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S
Normal file
1586
verif/tests/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S
Normal file
File diff suppressed because it is too large
Load diff
1
verif/tests/custom/CSR/csr_access_yaml/README.md
Normal file
1
verif/tests/custom/CSR/csr_access_yaml/README.md
Normal file
|
|
@ -0,0 +1 @@
|
|||
This directory contains yaml files for RISCV CVA6 32-bit CSRs, which are divided into three categories: Supervisor mode read-write CSRs, Machine mode read-write CSRs, and read-only CSRs.
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
- csr: CSR_MVENDORID
|
||||
description: >
|
||||
Implementation ID
|
||||
address: 0xF11
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Implementation
|
||||
description: >
|
||||
Provides unique encoding of the version of the processor implementation
|
||||
type: R
|
||||
reset_val: 0x602
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MARCHID
|
||||
description: >
|
||||
Architecture ID
|
||||
address: 0xF12
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Architecture ID
|
||||
description: >
|
||||
Provide Encoding the base microarchitecture of the hart
|
||||
type: R
|
||||
reset_val: 3
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MIMPID
|
||||
description: >
|
||||
Implementation ID
|
||||
address: 0xF13
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Implementation
|
||||
description: >
|
||||
Provides unique encoding of the version of the processor implementation
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MHARTID
|
||||
description: >
|
||||
Hardware Thread ID
|
||||
address: 0xF14
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Hart ID
|
||||
description: >
|
||||
contains the integer ID of the hardware thread running the code
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 0
|
||||
934
verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml
Normal file
934
verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml
Normal file
|
|
@ -0,0 +1,934 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
- csr: CSR_MSTATUS
|
||||
description: >
|
||||
Machine Status Register
|
||||
address: 0x300
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: SD
|
||||
description: >
|
||||
SD
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 31
|
||||
- field_name: WPRI
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 30
|
||||
lsb: 23
|
||||
- field_name: TSR
|
||||
description: >
|
||||
Trap SRET: supports intercepting the supervisor exception return instruction
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 22
|
||||
lsb: 22
|
||||
- field_name: TW
|
||||
description: >
|
||||
Timeout Wait: supports intercepting the WFI instruction
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 21
|
||||
lsb: 21
|
||||
- field_name: TVM
|
||||
description: >
|
||||
Trap Virtual Memory,supports intercepting supervisor virtual-memory management operations.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 20
|
||||
lsb: 20
|
||||
- field_name: MXR
|
||||
description: >
|
||||
Make eXecutable Readable: modifies the privilege with which loads access virtual memory.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 19
|
||||
lsb: 19
|
||||
- field_name: SUM
|
||||
description: >
|
||||
permit Supervisor User Memory access
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 18
|
||||
lsb: 18
|
||||
- field_name: MPRV
|
||||
description: >
|
||||
Modify PRiVilege
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 17
|
||||
lsb: 17
|
||||
- field_name: XS
|
||||
description: >
|
||||
use to reduce the cost of context save and restore by setting and tracking the current state
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 16
|
||||
lsb: 15
|
||||
- field_name: FS
|
||||
description: >
|
||||
use to reduce the cost of context save and restore by setting and tracking the current state
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 14
|
||||
lsb: 13
|
||||
- field_name: MPP
|
||||
description: >
|
||||
xPP fields can only hold privilege modes up to x, so MPP is two bits wide, SPP is one bit wide, and UPP is implicitly zero
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 12
|
||||
lsb: 11
|
||||
- field_name: VS
|
||||
description: >
|
||||
Vector Extension state
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 10
|
||||
lsb: 9
|
||||
- field_name: SPP
|
||||
description: >
|
||||
xPP fields can only hold privilege modes up to x, so MPP is two bits wide, SPP is one bit wide, and UPP is implicitly zero
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 8
|
||||
lsb: 8
|
||||
- field_name: MPIE
|
||||
description: >
|
||||
MPIE
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 7
|
||||
lsb: 7
|
||||
- field_name: UBE
|
||||
description: >
|
||||
User break point Enable
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 6
|
||||
lsb: 6
|
||||
- field_name: SPIE
|
||||
description: >
|
||||
indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 5
|
||||
lsb: 5
|
||||
- field_name: UPIE
|
||||
description: >
|
||||
indicates whether user-level interrupts were enabled prior to taking a user-level trap
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 4
|
||||
lsb: 4
|
||||
- field_name: MIE
|
||||
description: >
|
||||
Global interrupt-enable bits
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 3
|
||||
lsb: 3
|
||||
- field_name: WPRI
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 2
|
||||
lsb: 2
|
||||
- field_name: SIE
|
||||
description: >
|
||||
Global interrupt-enable bits
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: UIE
|
||||
description: >
|
||||
Global interrupt-enable bits
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MISA
|
||||
description: >
|
||||
ISA and extensions
|
||||
address: 0x301
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: MXL
|
||||
description: >
|
||||
MXL
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 31
|
||||
- field_name: MXL
|
||||
description: >
|
||||
MXL
|
||||
type: R
|
||||
reset_val: 1
|
||||
msb: 30
|
||||
lsb: 30
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 29
|
||||
lsb: 24
|
||||
- field_name: Non-standard extensions present
|
||||
description: >
|
||||
Non-standard extensions present
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 23
|
||||
lsb: 23
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 22
|
||||
lsb: 21
|
||||
- field_name: User mode implemented
|
||||
description: >
|
||||
User mode implemented
|
||||
type: R
|
||||
reset_val: 1
|
||||
msb: 20
|
||||
lsb: 20
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 19
|
||||
lsb: 19
|
||||
- field_name: Supervisor mode implemented
|
||||
description: >
|
||||
Supervisor mode implemented
|
||||
type: R
|
||||
reset_val: 1
|
||||
msb: 18
|
||||
lsb: 18
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 17
|
||||
lsb: 13
|
||||
- field_name: Integer Multiply/Divide extension
|
||||
description: >
|
||||
Integer Multiply/Divide extension
|
||||
type: R
|
||||
reset_val: 1
|
||||
msb: 12
|
||||
lsb: 12
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 11
|
||||
lsb: 9
|
||||
- field_name: RV32I/64I/128I base ISA
|
||||
description: >
|
||||
RV32I/64I/128I base ISA
|
||||
type: R
|
||||
reset_val: 1
|
||||
msb: 8
|
||||
lsb: 8
|
||||
- field_name: Hypervisoe Extension
|
||||
description: >
|
||||
Hypervisor Extension
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 7
|
||||
lsb: 7
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 6
|
||||
lsb: 6
|
||||
- field_name: Single precision FP Extension
|
||||
description: >
|
||||
Single precision FP extension
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 5
|
||||
lsb: 5
|
||||
- field_name: RV32E base ISA
|
||||
description: >
|
||||
RV32E base ISA
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 4
|
||||
lsb: 4
|
||||
- field_name: Double precision FP Extension
|
||||
description: >
|
||||
Double precision FP Extension
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 3
|
||||
lsb: 3
|
||||
- field_name: Compressed Extension
|
||||
description: >
|
||||
Compressed Extension
|
||||
type: R
|
||||
reset_val: 1
|
||||
msb: 2
|
||||
lsb: 2
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: Atomic Extension
|
||||
description: >
|
||||
Atomic Extension
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MIDELEG
|
||||
description: >
|
||||
Machine interrupt delegation register
|
||||
address: 0x303
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 12
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 11
|
||||
lsb: 11
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 10
|
||||
lsb: 10
|
||||
- field_name: STI
|
||||
description: >
|
||||
Supervisor timer interrupt
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 9
|
||||
lsb: 9
|
||||
- field_name: reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 8
|
||||
lsb: 8
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 7
|
||||
lsb: 7
|
||||
- field_name: reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 6
|
||||
lsb: 6
|
||||
- field_name: STI
|
||||
description: >
|
||||
Supervisor timer interrupt
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 5
|
||||
lsb: 5
|
||||
- field_name: reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 4
|
||||
lsb: 4
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 3
|
||||
lsb: 3
|
||||
- field_name: reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 2
|
||||
lsb: 2
|
||||
- field_name: Supervisor sw interrupts
|
||||
description: >
|
||||
S-mode software interrupts
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MIE
|
||||
description: >
|
||||
Machine Interrupt enable register
|
||||
address: 0x304
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 12
|
||||
- field_name: MEIE
|
||||
description: >
|
||||
enables machine external interrupts when set
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 11
|
||||
lsb: 11
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 10
|
||||
lsb: 10
|
||||
- field_name: SEIE
|
||||
description: >
|
||||
enable S-mode external interrupts,
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 9
|
||||
lsb: 9
|
||||
- field_name: UEIE
|
||||
description: >
|
||||
enables U-mode external interrupts
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 8
|
||||
lsb: 8
|
||||
- field_name: MTIE
|
||||
description: >
|
||||
timer interrupt-enable bit for M-mode
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 7
|
||||
lsb: 7
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 6
|
||||
lsb: 6
|
||||
- field_name: STIE
|
||||
description: >
|
||||
timer interrupt-enable bit for S-mode
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 5
|
||||
lsb: 5
|
||||
- field_name: UTIE
|
||||
description: >
|
||||
timer interrupt-enable bit for U-mode
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 4
|
||||
lsb: 4
|
||||
- field_name: MSIE
|
||||
description: >
|
||||
enable M-mode Software interrupts
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 3
|
||||
lsb: 3
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 2
|
||||
lsb: 2
|
||||
- field_name: SSIE
|
||||
description: >
|
||||
enable S-mode software interrupts
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: USIE
|
||||
description: >
|
||||
enable U-mode software interrrupts
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MTVEC
|
||||
description: >
|
||||
Machine trap-handler base address
|
||||
address: 0x305
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: BASE
|
||||
description: >
|
||||
holds trap vector configuration,
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 2
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: MODE
|
||||
description: >
|
||||
impose additional alignment constraints on the value in the BASE field
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MCOUNTEREN
|
||||
description: >
|
||||
Machine counter enable
|
||||
address: 0x306
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: HPMn
|
||||
description: >
|
||||
When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 3
|
||||
- field_name: IR
|
||||
description: >
|
||||
When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 2
|
||||
lsb: 2
|
||||
- field_name: TM
|
||||
description: >
|
||||
When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: CY
|
||||
description: >
|
||||
When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MSCRATCH
|
||||
description: >
|
||||
Scratch register for machine trap handlers
|
||||
address: 0x340
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: mscratch
|
||||
description: >
|
||||
hold a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MEPC
|
||||
description: >
|
||||
Machine exception program counter
|
||||
address: 0x341
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: mepc
|
||||
description: >
|
||||
holds all valid physical and virtual addresses
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MCAUSE
|
||||
description: >
|
||||
Machine Trap cause
|
||||
address: 0x342
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Interrupt
|
||||
description: >
|
||||
its set if the trap was caused by an interrupt
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 31
|
||||
- field_name: exception code
|
||||
description: >
|
||||
hold supported exception codes
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 30
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MTVAL
|
||||
description: >
|
||||
Machine bad address or Instruction
|
||||
address: 0x343
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: mtval
|
||||
description: >
|
||||
When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_MIP
|
||||
description: >
|
||||
Machine Interrupt enable register
|
||||
address: 0x344
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 12
|
||||
- field_name: MEIP
|
||||
description: >
|
||||
machine external interrupt pending
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 11
|
||||
lsb: 11
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 10
|
||||
lsb: 10
|
||||
- field_name: SEIP
|
||||
description: >
|
||||
enable S-mode external interrupts pending
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 9
|
||||
lsb: 9
|
||||
- field_name: UEIE
|
||||
description: >
|
||||
enables U-mode external interrupts
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 8
|
||||
lsb: 8
|
||||
- field_name: MTIP
|
||||
description: >
|
||||
timer interrupt-pending bit for M-mode
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 7
|
||||
lsb: 7
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 6
|
||||
lsb: 6
|
||||
- field_name: STIP
|
||||
description: >
|
||||
timer interrupt-pending bit for S-mode
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 5
|
||||
lsb: 5
|
||||
- field_name: UTIE
|
||||
description: >
|
||||
timer interrupt-enable bit for U-mode
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 4
|
||||
lsb: 4
|
||||
- field_name: MSIP
|
||||
description: >
|
||||
enable M-mode Software pending
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 3
|
||||
lsb: 3
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 2
|
||||
lsb: 2
|
||||
- field_name: SSIP
|
||||
description: >
|
||||
enable S-mode software pending
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: USIE
|
||||
description: >
|
||||
enable U-mode software interrrupts
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
|
||||
- csr: CSR_PMPADDR0
|
||||
description: >
|
||||
PMP address registers
|
||||
address: 0x3B0
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_PMPADDR1
|
||||
description: >
|
||||
PMP address registers
|
||||
address: 0x3B1
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_PMPADDR2
|
||||
description: >
|
||||
PMP address registers
|
||||
address: 0x3B2
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_PMPADDR3
|
||||
description: >
|
||||
PMP address registers
|
||||
address: 0x3B3
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_PMPADDR4
|
||||
description: >
|
||||
PMP address registers
|
||||
address: 0x3B4
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_PMPADDR5
|
||||
description: >
|
||||
PMP address registers
|
||||
address: 0x3B5
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_PMPADDR6
|
||||
description: >
|
||||
PMP address registers
|
||||
address: 0x3B6
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_PMPADDR7
|
||||
description: >
|
||||
PMP address registers
|
||||
address: 0x3B7
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: address
|
||||
description: >
|
||||
encodes bits 33-2 of a 34-bit physical address
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_ICACHE
|
||||
description: >
|
||||
Custom Register to enable/disable for Icache [bit 0]
|
||||
address: 0x7C0
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: ICACHE
|
||||
description: >
|
||||
Custom Register
|
||||
type: RW
|
||||
reset_val: 1
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_DCACHE
|
||||
description: >
|
||||
Custom Register to enable/disable for Dcache [bit 0]
|
||||
address: 0x7c1
|
||||
privilege_mode: M
|
||||
rv32:
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
Reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 1
|
||||
- field_name: DCACHE
|
||||
description: >
|
||||
Custom Register
|
||||
type: RW
|
||||
reset_val: 1
|
||||
msb: 0
|
||||
lsb: 0
|
||||
381
verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml
Normal file
381
verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml
Normal file
|
|
@ -0,0 +1,381 @@
|
|||
// Copyright 2023 Thales
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
- csr: CSR_SSTATUS
|
||||
description: >
|
||||
Supervisor status register
|
||||
address: 0x100
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: SD
|
||||
description: >
|
||||
SD
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 31
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 30
|
||||
lsb: 20
|
||||
- field_name: MXR
|
||||
description: >
|
||||
The MXR bit modifies the privilege with which loads access virtual memory
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 19
|
||||
lsb: 19
|
||||
- field_name: SUM
|
||||
description: >
|
||||
The SUM bit modifies the privilege with which S-mode loads and stores access virtual memory.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 18
|
||||
lsb: 18
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 17
|
||||
lsb: 17
|
||||
- field_name: XS
|
||||
description: >
|
||||
Extension state
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 16
|
||||
lsb: 15
|
||||
- field_name: FS
|
||||
description: >
|
||||
Floationd point State
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 14
|
||||
lsb: 13
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 12
|
||||
lsb: 9
|
||||
- field_name: SPP
|
||||
description: >
|
||||
SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 8
|
||||
lsb: 8
|
||||
- field_name: Reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 7
|
||||
lsb: 6
|
||||
- field_name: SPIE
|
||||
description: >
|
||||
The SPIE bit indicates whether supervisor interrupts were enabled prior to trappin into supervisor mode.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 5
|
||||
lsb: 5
|
||||
- field_name: UPIE
|
||||
description: >
|
||||
When a URET instruction is executed, UIE is set to UPIE, and UPIE is set to 1.
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 4
|
||||
lsb: 4
|
||||
- field_name: reserved
|
||||
description: >
|
||||
reserved for future use
|
||||
type: WPRI
|
||||
reset_val: 0
|
||||
msb: 3
|
||||
lsb: 2
|
||||
- field_name: SIE
|
||||
description: >
|
||||
The SIE bit enables or disables all interrupts in supervisor mode.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: UIE
|
||||
description: >
|
||||
The UIE bit enables or disables user-mode interrupts.
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_SIE
|
||||
description: >
|
||||
Supervisor Interrupt enable register
|
||||
address: 0x104
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: WPRI
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 10
|
||||
- field_name: SEIE
|
||||
description: >
|
||||
Supervisorlevel external interrupts are disabled when the SEIE bit
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 9
|
||||
lsb: 9
|
||||
- field_name: UEIE
|
||||
description: >
|
||||
User-level external interrupts are disabled when the UEIE bit in the sie register is clear.
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 8
|
||||
lsb: 8
|
||||
- field_name: WPRI
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 7
|
||||
lsb: 6
|
||||
- field_name: STIE
|
||||
description: >
|
||||
Supervisorlevel timer interrupts are disabled when the STIE bit in the sie register is clear.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 5
|
||||
lsb: 5
|
||||
- field_name: UTIE
|
||||
description: >
|
||||
User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 4
|
||||
lsb: 4
|
||||
- field_name: WPRI
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 3
|
||||
lsb: 2
|
||||
- field_name: SSIE
|
||||
description: >
|
||||
Supervisor-level software interrupts are disabled when the SSIE bit in the sie register is clear.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: USIE
|
||||
description: >
|
||||
User-level software interrupts are disabled when the USIE bit in the sie register is clear
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_STVEC
|
||||
description: >
|
||||
Supervisor trap handler base address
|
||||
address: 0x105
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: BASE
|
||||
description: >
|
||||
The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to alignment constraints
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 2
|
||||
- field_name: MODE
|
||||
description: >
|
||||
When MODE=Direct, all traps into supervisor mode cause the pc to be set to the address in the BASE field. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number.
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: MODE
|
||||
description: >
|
||||
When MODE=Direct, all traps into supervisor mode cause the pc to be set to the address in the BASE field. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_SCOUNTEREN
|
||||
description: >
|
||||
Supervisor counter enable
|
||||
address: 0x106
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: HPMn
|
||||
description: >
|
||||
When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 3
|
||||
- field_name: IR
|
||||
description: >
|
||||
When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 2
|
||||
lsb: 2
|
||||
- field_name: TM
|
||||
description: >
|
||||
When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: CY
|
||||
description: >
|
||||
When its is clear, attempts to read the cycle,time, instret, or hpmcountern register while executing in U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_SSCRATCH
|
||||
description: >
|
||||
Scartch Register for supervisor trap handlers
|
||||
address: 0x140
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: SSCRATCH
|
||||
description: >
|
||||
it is used to hold a pointer to the hart-local supervisor context while the hart is executing user code.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_SEPC
|
||||
description: >
|
||||
Supervisor exception program counter
|
||||
address: 0x141
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: SEPC
|
||||
description: >
|
||||
On implementations that support only IALIGN=32, the two low bits (sepc[1:0]) are always zero
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_SCAUSE
|
||||
description: >
|
||||
Supervisor trap cause
|
||||
address: 0x142
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: Interrupt
|
||||
description: >
|
||||
The Interrupt bit in the scause register is set if the trap was caused by an interrupt.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 31
|
||||
- field_name: Exception Code
|
||||
description: >
|
||||
The Exception Code field contains a code identifying the last exception
|
||||
type: rw
|
||||
reset_val: 0
|
||||
msb: 30
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_STVAL
|
||||
description: >
|
||||
Supervisor bad address or instruction
|
||||
address: 0x143
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: Count
|
||||
description: >
|
||||
when a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap.
|
||||
type: RW
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 0
|
||||
|
||||
- csr: CSR_SIP
|
||||
description: >
|
||||
Supervisor interrupt pending
|
||||
address: 0x144
|
||||
privilege_mode: S
|
||||
rv32:
|
||||
- field_name: WPRI
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 31
|
||||
lsb: 10
|
||||
- field_name: SEIP
|
||||
description: >
|
||||
A supervisor-level external interrupt is pending if the SEIP bit in the sip register is set.
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 9
|
||||
lsb: 9
|
||||
- field_name: UEIP
|
||||
description: >
|
||||
UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 8
|
||||
lsb: 8
|
||||
- field_name: WPRI
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 7
|
||||
lsb: 6
|
||||
- field_name: STIP
|
||||
description: >
|
||||
A supervisor-level timer interrupt is pending if the STIP bit in the sip register is set
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 5
|
||||
lsb: 5
|
||||
- field_name: UTIP
|
||||
description: >
|
||||
A user-level timer interrupt is pending if the UTIP bit in the sip register is set
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 4
|
||||
lsb: 4
|
||||
- field_name: WPRI
|
||||
description: >
|
||||
reserved for future use
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 3
|
||||
lsb: 2
|
||||
- field_name: SSIP
|
||||
description: >
|
||||
A supervisor-level software interrupt is triggered on the current hart by writing 1 to its supervisor software interrupt-pending (SSIP) bit
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 1
|
||||
lsb: 1
|
||||
- field_name: USIP
|
||||
description: >
|
||||
A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit
|
||||
type: R
|
||||
reset_val: 0
|
||||
msb: 0
|
||||
lsb: 0
|
||||
|
||||
|
|
@ -1,92 +0,0 @@
|
|||
#include "model_test.h"
|
||||
.macro init
|
||||
.endm
|
||||
.section .text.init
|
||||
.globl _start
|
||||
.option norvc
|
||||
.org 0x00
|
||||
_start:
|
||||
RVMODEL_BOOT
|
||||
# CSR_MSCRATCH
|
||||
li x10, 0xa5a5a5a5
|
||||
csrrw x14, 0x340, x10
|
||||
li x10, 0x00000000
|
||||
bne x10, x14, csr_fail
|
||||
li x10, 0x5a5a5a5a
|
||||
csrrw x14, 0x340, x10
|
||||
li x10, 0xa5a5a5a5
|
||||
bne x10, x14, csr_fail
|
||||
li x10, 0x6c218674
|
||||
csrrw x14, 0x340, x10
|
||||
li x10, 0x5a5a5a5a
|
||||
bne x10, x14, csr_fail
|
||||
li x10, 0xa5a5a5a5
|
||||
csrrs x14, 0x340, x10
|
||||
li x10, 0x6c218674
|
||||
bne x10, x14, csr_fail
|
||||
li x10, 0x5a5a5a5a
|
||||
csrrs x14, 0x340, x10
|
||||
li x10, 0xeda5a7f5
|
||||
bne x10, x14, csr_fail
|
||||
li x10, 0xdd2d25a6
|
||||
csrrs x14, 0x340, x10
|
||||
li x10, 0xffffffff
|
||||
bne x10, x14, csr_fail
|
||||
li x10, 0xa5a5a5a5
|
||||
csrrc x14, 0x340, x10
|
||||
li x10, 0xffffffff
|
||||
bne x10, x14, csr_fail
|
||||
li x10, 0x5a5a5a5a
|
||||
csrrc x14, 0x340, x10
|
||||
li x10, 0x5a5a5a5a
|
||||
bne x10, x14, csr_fail
|
||||
li x10, 0x8959179c
|
||||
csrrc x14, 0x340, x10
|
||||
li x10, 0x00000000
|
||||
bne x10, x14, csr_fail
|
||||
csrrwi x14, 0x340, 0b00101
|
||||
li x10, 0x00000000
|
||||
bne x10, x14, csr_fail
|
||||
csrrwi x14, 0x340, 0b11010
|
||||
li x10, 0x00000005
|
||||
bne x10, x14, csr_fail
|
||||
csrrwi x14, 0x340, 0b01110
|
||||
li x10, 0x0000001a
|
||||
bne x10, x14, csr_fail
|
||||
csrrsi x14, 0x340, 0b00101
|
||||
li x10, 0x0000000e
|
||||
bne x10, x14, csr_fail
|
||||
csrrsi x14, 0x340, 0b11010
|
||||
li x10, 0x0000000f
|
||||
bne x10, x14, csr_fail
|
||||
csrrsi x14, 0x340, 0b00000
|
||||
li x10, 0x0000001f
|
||||
bne x10, x14, csr_fail
|
||||
csrrci x14, 0x340, 0b00101
|
||||
li x10, 0x0000001f
|
||||
bne x10, x14, csr_fail
|
||||
csrrci x14, 0x340, 0b11010
|
||||
li x10, 0x0000001a
|
||||
bne x10, x14, csr_fail
|
||||
csrrci x14, 0x340, 0b00100
|
||||
li x10, 0x00000000
|
||||
bne x10, x14, csr_fail
|
||||
csrr x14, 0x340
|
||||
li x10, 0x00000000
|
||||
bne x10, x14, csr_fail
|
||||
csr_pass:
|
||||
li x1, 0
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, x30
|
||||
self_loop: j self_loop
|
||||
|
||||
csr_fail:
|
||||
li x1, 1
|
||||
slli x1, x1, 1
|
||||
addi x1, x1, 1
|
||||
sw x1, tohost, x30
|
||||
self_loop_2: j self_loop_2
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,9 +1,76 @@
|
|||
- test: MSCRATCH_CSR
|
||||
## // Copyright 2023 Thales
|
||||
## // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
- test: M_RW_CSR
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/csr_access_tests/riscv_mscratch_csr_test_0.S
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S
|
||||
|
||||
- test: S_RW_CSR
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S
|
||||
|
||||
- test: M_RO_CSR
|
||||
iterations: 1
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S
|
||||
|
||||
- test: M_MCYCLE_CSR
|
||||
iterations: 0
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_mcycle_csr_test_0.S
|
||||
|
||||
- test: M_MCYCLEH_CSR
|
||||
iterations: 0
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_mcycleh_csr_test_0.S
|
||||
|
||||
- test: M_MINSTRET_CSR
|
||||
iterations: 0
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_minstret_csr_test_0.S
|
||||
|
||||
- test: M_MINSTRETH_CSR
|
||||
iterations: 0
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_minstreth_csr_test_0.S
|
||||
|
||||
- test: U_CYCLE_CSR
|
||||
iterations: 0
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S
|
||||
|
||||
- test: U_INSTRET_CSR
|
||||
iterations: 0
|
||||
path_var: TESTS_PATH
|
||||
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
|
||||
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
|
||||
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
|
||||
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_instret_csr_test_0.S
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue