github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-20 04:07:36 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Bump register interface to v0.3.1 (#819)

Browse source 
* Bump register interface to v0.3.1

* Upgrade PLIC to upgraded register interface version v0.3.1

* Upgrade rv_plic submodule

* Add rv_plic upgrade to xilinx target. Fix indentations

* Try again (indentation)

* Add register_interface include
This commit is contained in:
Andreas Kuster 2022-02-10 14:19:12 +01:00 • committed by GitHub
parent 1e23ebac71
commit c72a9e5d56
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
6 changed files with 35 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

5
Makefile
View file

@ -95,13 +95,13 @@ ariane_pkg += core/include/riscv_pkg.sv \
core/include/cvxif_pkg.sv \
corev_apu/axi/src/axi_pkg.sv \
corev_apu/register_interface/src/reg_intf.sv \
corev_apu/register_interface/src/reg_intf_pkg.sv \
core/include/axi_intf.sv \
corev_apu/tb/rvfi_pkg.sv \
corev_apu/tb/ariane_soc_pkg.sv \
corev_apu/tb/ariane_axi_soc_pkg.sv \
core/include/ariane_axi_pkg.sv \
core/fpu/src/fpnew_pkg.sv \
common/submodules/common_cells/src/cf_math_pkg.sv \
core/cvxif_example/include/cvxif_instr_pkg.sv \
core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
@ -187,7 +187,6 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
corev_apu/riscv-dbg/debug_rom/debug_rom.sv \
corev_apu/register_interface/src/apb_to_reg.sv \
corev_apu/axi/src/axi_multicut.sv \
common/submodules/common_cells/src/cf_math_pkg.sv \
common/submodules/common_cells/src/deprecated/generic_fifo.sv \
common/submodules/common_cells/src/deprecated/pulp_sync.sv \
common/submodules/common_cells/src/deprecated/find_first_one.sv \
@ -281,7 +280,7 @@ riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
# Search here for include files (e.g.: non-standalone components)
incdir := common/submodules/common_cells/include/ corev_apu/axi/include/
incdir := common/submodules/common_cells/include/ corev_apu/axi/include/ corev_apu/register_interface/include/
# Compile and sim flags
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)

2
corev_apu/fpga/scripts/run.tcl
View file

@ -38,7 +38,7 @@ read_ip { \
}
# read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci
set_property include_dirs { "src/axi_sd_bridge/include" "../../common/submodules/common_cells/include" "../axi/include"} [current_fileset]
set_property include_dirs { "src/axi_sd_bridge/include" "../../common/submodules/common_cells/include" "../axi/include" "../register_interface/include"} [current_fileset]
source scripts/add_sources.tcl

29
corev_apu/fpga/src/ariane_peripherals_xilinx.sv
View file

@ -8,7 +8,10 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Xilinx Peripehrals
// Xilinx Peripherals
`include "register_interface/assign.svh"
`include "register_interface/typedef.svh"
module ariane_peripherals #(
parameter int AxiAddrWidth = -1,
@ -160,28 +163,26 @@ module ariane_peripherals #(
.reg_o ( reg_bus )
);
reg_intf::reg_intf_resp_d32 plic_resp;
reg_intf::reg_intf_req_a32_d32 plic_req;
// define reg type according to REG_BUS above
`REG_BUS_TYPEDEF_ALL(plic, logic[31:0], logic[31:0], logic[3:0])
plic_req_t plic_req;
plic_rsp_t plic_rsp;
assign plic_req.addr = reg_bus.addr;
assign plic_req.write = reg_bus.write;
assign plic_req.wdata = reg_bus.wdata;
assign plic_req.wstrb = reg_bus.wstrb;
assign plic_req.valid = reg_bus.valid;
assign reg_bus.rdata = plic_resp.rdata;
assign reg_bus.error = plic_resp.error;
assign reg_bus.ready = plic_resp.ready;
// assign REG_BUS.out to (req_t, rsp_t) pair
`REG_BUS_ASSIGN_TO_REQ(plic_req, reg_bus)
`REG_BUS_ASSIGN_FROM_RSP(reg_bus, plic_rsp)
plic_top #(
.N_SOURCE ( ariane_soc::NumSources ),
.N_TARGET ( ariane_soc::NumTargets ),
.MAX_PRIO ( ariane_soc::MaxPriority )
.MAX_PRIO ( ariane_soc::MaxPriority ),
.reg_req_t ( plic_req_t ),
.reg_rsp_t ( plic_rsp_t )
) i_plic (
.clk_i,
.rst_ni,
.req_i ( plic_req ),
.resp_o ( plic_resp ),
.resp_o ( plic_rsp ),
.le_i ( '0 ), // 0:level 1:edge
.irq_sources_i ( irq_sources ),
.eip_targets_o ( irq_o )

2
corev_apu/register_interface

@ -1 +1 @@
Subproject commit 48a7d6cae9bd9cac16cebde1920dd2a657a3bdc5
Subproject commit 73de8e51b79f416350229b1d2420b2c527e002b8

2
corev_apu/rv_plic

@ -1 +1 @@
Subproject commit ebe3e9888920f1f757b75bab81dc80f804896f57
Subproject commit 5b5c5a4c1c15c3d7bb833071d344b2c2bc5f599d

29
corev_apu/tb/ariane_peripherals.sv
View file

@ -8,7 +8,10 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Xilinx Peripehrals
`include "register_interface/assign.svh"
`include "register_interface/typedef.svh"
// Xilinx Peripherals
module ariane_peripherals #(
parameter int AxiAddrWidth = -1,
parameter int AxiDataWidth = -1,
@ -153,28 +156,26 @@ module ariane_peripherals #(
.reg_o ( reg_bus )
);
reg_intf::reg_intf_resp_d32 plic_resp;
reg_intf::reg_intf_req_a32_d32 plic_req;
// define reg type according to REG_BUS above
`REG_BUS_TYPEDEF_ALL(plic, logic[31:0], logic[31:0], logic[3:0])
plic_req_t plic_req;
plic_rsp_t plic_rsp;
assign plic_req.addr = reg_bus.addr;
assign plic_req.write = reg_bus.write;
assign plic_req.wdata = reg_bus.wdata;
assign plic_req.wstrb = reg_bus.wstrb;
assign plic_req.valid = reg_bus.valid;
assign reg_bus.rdata = plic_resp.rdata;
assign reg_bus.error = plic_resp.error;
assign reg_bus.ready = plic_resp.ready;
// assign REG_BUS.out to (req_t, rsp_t) pair
`REG_BUS_ASSIGN_TO_REQ(plic_req, reg_bus)
`REG_BUS_ASSIGN_FROM_RSP(reg_bus, plic_rsp)
plic_top #(
.N_SOURCE ( ariane_soc::NumSources ),
.N_TARGET ( ariane_soc::NumTargets ),
.MAX_PRIO ( ariane_soc::MaxPriority )
.MAX_PRIO ( ariane_soc::MaxPriority ),
.reg_req_t ( plic_req_t ),
.reg_rsp_t ( plic_rsp_t )
) i_plic (
.clk_i,
.rst_ni,
.req_i ( plic_req ),
.resp_o ( plic_resp ),
.resp_o ( plic_rsp ),
.le_i ( '0 ), // 0:level 1:edge
.irq_sources_i ( irq_sources ),
.eip_targets_o ( irq_o )