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Bump verif/core-v-verif from fd68dfd to c7d2077 (#1828)

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MarioOpenHWGroup 2024-02-13 14:20:21 +01:00 • committed by GitHub
parent d48c4b5b4e
commit c7f0eaf0d8
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15 changed files with 212 additions and 46 deletions
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9
Makefile
View file

@ -145,7 +145,9 @@ endif
# this list contains the standalone components
src := core/include/$(target)_config_pkg.sv \
$(if $(spike-tandem),verif/tb/core/rvfi_pkg.sv) \
$(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv) \
$(if $(spike-tandem),verif/tb/core/uvma_cva6pkg_utils_pkg.sv) \
$(if $(spike-tandem),verif/tb/core/uvma_rvfi_pkg.sv) \
$(if $(spike-tandem),corev_apu/tb/common/spike.sv) \
corev_apu/src/ariane.sv \
$(wildcard corev_apu/bootrom/*.sv) \
@ -235,7 +237,10 @@ riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-li
# Search here for include files (e.g.: non-standalone components)
incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ \
$(CVA6_REPO_DIR)/corev_apu/register_interface/include/ $(CVA6_REPO_DIR)/corev_apu/tb/common/ \
$(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/
$(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ \
$(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/ \
$(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/ \
$(CVA6_REPO_DIR)/verif/tb/core/
# Compile and sim flags
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat +define+$(defines)

11
corev_apu/tb/common/spike.sv
View file

@ -13,7 +13,9 @@
// Description: Wrapped Spike Model for Tandem Verification
import ariane_pkg::*;
import rvfi_pkg::*;
import uvma_rvfi_pkg::*;
import uvma_core_cntrl_pkg::*;
import uvma_cva6pkg_utils_pkg::*;
module spike #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
@ -54,7 +56,12 @@ module spike #(
string rtl_isa = "";
initial begin
rvfi_initialize_spike('h1);
st_core_cntrl_cfg st = cva6pkg_to_core_cntrl_cfg(st);
st.boot_addr_valid = 1'b1;
st.boot_addr = 64'h0x10000;
rvfi_initialize_spike("cva6", st);
end
st_rvfi s_core, s_reference_model;

2
verif/core-v-verif

@ -1 +1 @@
Subproject commit fd68dfd2c04e9edcca236501e7c074ab1a756f41
Subproject commit c7d2077e8b4a1493aaecb89534562893064d5e0c

1
verif/env/uvme/uvme_cva6_cfg.sv vendored
View file

@ -153,6 +153,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
clknrst_cfg.enabled == 1;
isacov_cfg.enabled == 1;
rvfi_cfg.enabled == 1;
rvfi_cfg.csr_enabled == 0;
}
isacov_cfg.seq_instr_group_x2_enabled == 1;

14
verif/env/uvme/uvme_cva6_env.sv vendored
View file

@ -38,7 +38,7 @@ class uvme_cva6_env_c extends uvm_env;
uvme_cva6_vsqr_c vsequencer;
uvme_cva6_cov_model_c cov_model;
uvmc_rvfi_reference_model m_reference_model;
uvmc_rvfi_reference_model reference_model;
// Agents
uvma_clknrst_agent_c clknrst_agent;
@ -227,7 +227,7 @@ endfunction: connect_phase
function void uvme_cva6_env_c::end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
`uvm_info("UVMECVA6ENV", $sformatf("Configuration:\n%s", cfg.sprint()), UVM_LOW)
`uvm_info("UVMECVA6ENV", $sformatf("Configuration:\n%s", cfg.sprint()), UVM_MEDIUM)
endfunction : end_of_elaboration_phase
@ -247,6 +247,10 @@ function void uvme_cva6_env_c::assign_cfg();
uvm_config_db#(uvma_isacov_cfg_c)::set(this, "*isacov_agent", "cfg", cfg.isacov_cfg);
if (cfg.scoreboard_enabled) begin
uvm_config_db#(uvma_core_cntrl_cfg_c)::set(this, "reference_model", "cfg", cfg);
end
endfunction: assign_cfg
@ -277,7 +281,7 @@ function void uvme_cva6_env_c::create_env_components();
if (cfg.scoreboard_enabled) begin
predictor = uvme_cva6_prd_c::type_id::create("predictor", this);
sb = uvme_cva6_sb_c ::type_id::create("sb" , this);
m_reference_model = uvmc_rvfi_reference_model#(ILEN,XLEN)::type_id::create("m_reference_model", this);
reference_model = uvmc_rvfi_reference_model#(ILEN,XLEN)::type_id::create("reference_model", this);
end
if (cfg.cov_model_enabled) begin
@ -328,8 +332,8 @@ function void uvme_cva6_env_c::connect_scoreboard();
// Ex: predictor.debug_ap.connect(sb.debug_sb.exp_export);
rvfi_agent.rvfi_core_ap.connect(sb.m_rvfi_scoreboard.m_imp_core);
rvfi_agent.rvfi_core_ap.connect(m_reference_model.m_analysis_imp);
m_reference_model.m_analysis_port.connect(sb.m_rvfi_scoreboard.m_imp_reference_model);
rvfi_agent.rvfi_core_ap.connect(reference_model.m_analysis_imp);
reference_model.m_analysis_port.connect(sb.m_rvfi_scoreboard.m_imp_reference_model);
endfunction: connect_scoreboard

1
verif/sim/Makefile
View file

@ -166,6 +166,7 @@ VCS_WORK_DIR = $(CVA6_REPO_DIR)/verif/sim/vcs_results/default/vcs.d
SIMV = $(VCS_WORK_DIR)/simv
export CVA6_UVMT_DIR = $(CVA6_REPO_DIR)/verif/tb/uvmt
export CVA6_CORET_DIR = $(CVA6_REPO_DIR)/verif/tb/core
export CVA6_UVMT_PATH = $(CVA6_REPO_DIR)/verif/tb/uvmt
export CVA6_UVME_PATH = $(CVA6_REPO_DIR)/verif/env/uvme
export CV_CORE_LC = cva6

76
verif/tb/core/custom_uvm_macros.svh Normal file
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@ -0,0 +1,76 @@
`ifdef UVM_REPORT_DISABLE_FILE
`define uvm_file ""
`else
`define uvm_file `__FILE__
`endif
`ifdef UVM_REPORT_DISABLE_LINE
`define uvm_line 0
`else
`define uvm_line `__LINE__
`endif
typedef enum
{
UVM_NONE = 0,
UVM_LOW = 100,
UVM_MEDIUM = 200,
UVM_HIGH = 300,
UVM_FULL = 400,
UVM_DEBUG = 500
} uvm_verbosity;
`define uvm_info(TOP, MSG, LVL) \
begin \
uvm_report_info(TOP, MSG, LVL, `uvm_file, `uvm_line); \
end
`define uvm_warning(TOP, MSG, LVL) \
begin \
uvm_report_warning(TOP, MSG, LVL, `uvm_file, `uvm_line); \
end
`define uvm_error(TOP, MSG) \
begin \
uvm_report_error(TOP, MSG, UVM_NONE, `uvm_file, `uvm_line); \
end
`define uvm_fatal(TOP, MSG) \
begin \
uvm_report_fatal(TOP, MSG, UVM_NONE, `uvm_file, `uvm_line); \
end
function void uvm_report_info(string id,
string message,
int verbosity = UVM_MEDIUM,
string filename = "",
int line = 0);
$display($sformatf("UVM_INFO @ %t ns : %s %s", $time, id, message));
endfunction
function void uvm_report_warning(string id,
string message,
int verbosity = UVM_MEDIUM,
string filename = "",
int line = 0);
$display($sformatf("UVM_WARNING @ %t ns : %s %s", $time, id , message));
endfunction
function void uvm_report_error(string id,
string message,
int verbosity = UVM_LOW,
string filename = "",
int line = 0);
$display($sformatf("UVM_ERROR @ %t ns : %s %s", $time, id , message));
endfunction
function void uvm_report_fatal(string id,
string message,
int verbosity = UVM_NONE,
string filename = "",
int line = 0);
$display($sformatf("UVM_FATAL @ %t ns : %s %s", $time, id , message));
$finish();
endfunction

34
verif/tb/core/rvfi_pkg.sv
View file

@ -1,34 +0,0 @@
`ifndef __UVMA_RVFI_PKG_SV__
`define __UVMA_RVFI_PKG_SV__
// Pre-processor macros
`ifdef VERILATOR
`define uvm_info(TOP,MSG,LVL) \
begin \
string tmp = MSG; \
$display($sformatf("UVM_INFO @ %t ns : %s %s", $time, TOP ,tmp)); \
end
`define uvm_fatal(TOP,MSG) \
begin \
string tmp = MSG; \
$display($sformatf("UVM_FATAL @ %t ns : %s %s", $time, TOP ,tmp)); $finish(); \
end
`else
`include "uvm_macros.svh"
`endif
package rvfi_pkg;
`ifndef VERILATOR
import uvm_pkg ::*;
`endif
`include "uvma_rvfi_constants.sv"
`include "uvma_rvfi_tdefs.sv"
`include "uvma_rvfi_utils.sv"
endpackage
`endif

12
verif/tb/core/uvma_core_cntrl_pkg.sv Normal file
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@ -0,0 +1,12 @@
`ifndef __UVMA_CORE_CNTRL_PKG_SV__
`define __UVMA_CORE_CNTRL_PKG_SV__
package uvma_core_cntrl_pkg;
// Constants / Structs / Enums
`include "uvma_core_cntrl_constants.sv"
`include "uvma_core_cntrl_tdefs.sv"
endpackage : uvma_core_cntrl_pkg
`endif

41
verif/tb/core/uvma_cva6pkg_utils.sv Normal file
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@ -0,0 +1,41 @@
function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg base);
$cast(base.xlen, cva6_config_pkg::CVA6ConfigXlen);
base.ilen = cva6_config_pkg::CVA6ConfigXlen;
base.ext_i_supported = 1;
base.ext_a_supported = cva6_config_pkg::cva6_cfg.RVA;
base.ext_m_supported = 1;
base.ext_c_supported = cva6_config_pkg::cva6_cfg.RVC;
base.ext_p_supported = 1;
base.ext_v_supported = cva6_config_pkg::cva6_cfg.RVV;
base.ext_f_supported = cva6_config_pkg::cva6_cfg.RVF | cva6_config_pkg::cva6_cfg.FpuEn;
base.ext_d_supported = cva6_config_pkg::cva6_cfg.RVD;
base.ext_zba_supported = cva6_config_pkg::CVA6ConfigBExtEn;
base.ext_zbb_supported = cva6_config_pkg::CVA6ConfigBExtEn;
base.ext_zbc_supported = cva6_config_pkg::CVA6ConfigBExtEn;
base.ext_zbe_supported = cva6_config_pkg::CVA6ConfigBExtEn;
base.ext_zbf_supported = 0;
base.ext_zbm_supported = 0;
base.ext_zbp_supported = 0;
base.ext_zbr_supported = 0;
base.ext_zbs_supported = cva6_config_pkg::CVA6ConfigBExtEn;
base.ext_zbt_supported = 0;
base.ext_zcb_supported = cva6_config_pkg::cva6_cfg.RVZCB;
base.ext_zifencei_supported = 1;
base.ext_zicsr_supported = 1;
base.ext_zicntr_supported = 1;
base.mode_s_supported = cva6_config_pkg::cva6_cfg.RVS;
base.mode_u_supported = cva6_config_pkg::cva6_cfg.RVU;
base.pmp_supported = (cva6_config_pkg::cva6_cfg.NrPMPEntries > 0);
base.pmp_regions = cva6_config_pkg::cva6_cfg.NrPMPEntries;
base.debug_supported = cva6_config_pkg::cva6_cfg.DebugEn;
return base;
endfunction : cva6pkg_to_core_cntrl_cfg

12
verif/tb/core/uvma_cva6pkg_utils_pkg.sv Normal file
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@ -0,0 +1,12 @@
`ifndef __UVMA_CVA6PKG_UTILS_PKG_SV__
`define __UVMA_CVA6PKG_UTILS_PKG_SV__
package uvma_cva6pkg_utils_pkg;
import cva6_config_pkg::*;
import uvma_core_cntrl_pkg::*;
`include "uvma_cva6pkg_utils.sv"
endpackage : uvma_cva6pkg_utils_pkg
`endif

24
verif/tb/core/uvma_rvfi_pkg.sv Normal file
View file

@ -0,0 +1,24 @@
`ifndef __UVMA_RVFI_PKG_SV__
`define __UVMA_RVFI_PKG_SV__
// Pre-processor macros
`ifdef VERILATOR
`include "custom_uvm_macros.svh"
`else
`include "uvm_macros.svh"
`endif
package uvma_rvfi_pkg;
`ifndef VERILATOR
import uvm_pkg ::*;
`endif
import uvma_core_cntrl_pkg::*;
`include "uvma_rvfi_constants.sv"
`include "uvma_rvfi_tdefs.sv"
`include "uvma_rvfi_utils.sv"
endpackage : uvma_rvfi_pkg
`endif

2
verif/tb/uvmt/uvmt_cva6.flist
View file

@ -42,6 +42,8 @@
+incdir+${CVA6_UVMT_PATH}/../../tests/uvmt/vseq
// CVA6 tests (includes constants/macros/types meant for test bench)
+incdir+${CVA6_CORET_DIR}
${CVA6_CORET_DIR}/uvma_cva6pkg_utils_pkg.sv
+incdir+${TBSRC_HOME}
${CVA6_UVMT_DIR}/uvmt_cva6_pkg.sv

2
verif/tb/uvmt/uvmt_cva6_pkg.sv
View file

@ -37,8 +37,10 @@
package uvmt_cva6_pkg;
import uvm_pkg::*;
import uvma_core_cntrl_pkg::*;
import uvme_cva6_pkg::*;
import uvmc_rvfi_reference_model_pkg::*;
import uvma_cva6pkg_utils_pkg::*;
import uvml_hrtbt_pkg::*;
import uvml_logs_pkg::*;

17
verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv
View file

@ -137,6 +137,8 @@ class uvmt_cva6_base_test_c extends uvm_test;
*/
extern virtual function void create_cfg();
extern virtual function void pkg_to_cfg();
/**
* 1. Calls test_cfg's process_cli_args()
* 2. Calls randomize on 'this' and fatals out if it fails.
@ -213,6 +215,7 @@ function void uvmt_cva6_base_test_c::build_phase(uvm_phase phase);
retrieve_vifs ();
create_cfg ();
randomize_test ();
pkg_to_cfg ();
cfg_hrtbt_monitor();
assign_cfg ();
create_cntxt ();
@ -319,6 +322,16 @@ function void uvmt_cva6_base_test_c::create_cfg();
endfunction : create_cfg
function void uvmt_cva6_base_test_c::pkg_to_cfg();
st_core_cntrl_cfg st = env_cfg.to_struct();
st = cva6pkg_to_core_cntrl_cfg(st);
env_cfg.from_struct(st);
env_cfg.post_randomize();
endfunction : pkg_to_cfg
function void uvmt_cva6_base_test_c::randomize_test();
@ -326,8 +339,8 @@ function void uvmt_cva6_base_test_c::randomize_test();
if (!this.randomize()) begin
`uvm_fatal("BASE TEST", "Failed to randomize test");
end
`uvm_info("BASE TEST", $sformatf("Top-level environment configuration:\n%s", env_cfg.sprint()), UVM_NONE)
`uvm_info("BASE TEST", $sformatf("Testcase configuration:\n%s", test_cfg.sprint()), UVM_NONE)
`uvm_info("BASE TEST", $sformatf("Top-level environment configuration:\n%s", env_cfg.sprint()), UVM_HIGH)
`uvm_info("BASE TEST", $sformatf("Testcase configuration:\n%s", test_cfg.sprint()), UVM_HIGH)
endfunction : randomize_test