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Basic jump and branch prediction test passing

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This commit is contained in:
Florian Zaruba 2017-05-15 19:00:57 +02:00
parent 7e4bdfb11c
commit c8de1aaae9
5 changed files with 12 additions and 37 deletions
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7
src/ariane.sv
View file

@ -105,16 +105,11 @@ module ariane
// IF <-> ID
// --------------
logic busy_if_id;
fetch_entry fetch_entry_if_id;
logic ready_id_if;
logic [31:0] fetch_rdata_id_if;
logic fetch_valid_if_id;
logic [31:0] instr_rdata_if_id;
logic decode_ack_id_if;
logic is_compressed_if_id;
logic [63:0] pc_if_id;
exception exception_if_id;
branchpredict_sbe branch_predict_if_id;
logic instr_is_compressed_if_id;
// --------------
// ID <-> EX
// --------------

16
src/fetch_fifo.sv
View file

@ -69,8 +69,8 @@ module fetch_fifo
assign full = (status_cnt_q >= DEPTH - 3);
assign empty = (status_cnt_q == 0);
/* verilator lint_on WIDTH */
// the output is valid if we are either empty or just got a valid
assign out_valid_o = !empty || in_valid_q;
// the output is valid if we are are not empty
assign out_valid_o = !empty;
// we need space for at least two instructions: the full flag is conditioned on that
// but if we pop in the current cycle and we have one place left we can still fit two instructions alt
assign in_ready_o = !full;
@ -155,7 +155,7 @@ module fetch_fifo
status_cnt++;
write_pointer++;
$display("Instruction: [ c | c ] @ %t", $time);
// $display("Instruction: [ c | c ] @ %t", $time);
// or is it an unaligned 32 bit instruction like
// ____________________________________________________
// |instr [15:0] | instr [31:16] | compressed 1[15:0] |
@ -167,7 +167,7 @@ module fetch_fifo
unaligned_n = 1'b1;
// save the address as well
unaligned_address_n = {in_addr_q[63:2], 2'b10};
$display("Instruction: [ i0 | c ] @ %t", $time);
// $display("Instruction: [ i0 | c ] @ %t", $time);
// this does not consume space in the FIFO
end
end else begin
@ -180,7 +180,7 @@ module fetch_fifo
};
status_cnt++;
write_pointer++;
$display("Instruction: [ i ] @ %t", $time);
// $display("Instruction: [ i ] @ %t", $time);
end
end
// we have an outstanding unaligned instruction
@ -208,7 +208,7 @@ module fetch_fifo
write_pointer++;
// unaligned access served
unaligned_n = 1'b0;
$display("Instruction: [ c | i1 ] @ %t", $time);
// $display("Instruction: [ c | i1 ] @ %t", $time);
// or is it an unaligned 32 bit instruction like
// ____________________________________________________
// |instr [15:0] | instr [31:16] | compressed 1[15:0] |
@ -220,7 +220,7 @@ module fetch_fifo
unaligned_n = 1'b1;
// save the address as well
unaligned_address_n = {in_addr_q[63:2], 2'b10};
$display("Instruction: [ i0 | i1 ] @ %t", $time);
// $display("Instruction: [ i0 | i1 ] @ %t", $time);
// this does not consume space in the FIFO
end
end
@ -231,7 +231,7 @@ module fetch_fifo
// we are ready to accept a new request if we still have two places in the queue
// Output assignments
fetch_entry_o = mem_q[read_pointer_q].branch_predict;
fetch_entry_o = mem_q[read_pointer_q];
if (out_ready_i) begin
read_pointer_n = read_pointer_q + 1;

2
src/id_stage.sv
View file

@ -132,7 +132,7 @@ module id_stage #(
.pc_i ( fetch_entry_i.address ),
.is_compressed_i ( fetch_entry_i.is_compressed ),
.instruction_i ( fetch_entry_i.instruction ),
.branch_predict_i ( fetch_entry_ibranch_predict ),
.branch_predict_i ( fetch_entry_i.branch_predict ),
.ex_i ( ex_if_i ),
.instruction_o ( decoded_instr_dc_sb ),
.is_control_flow_instr_o ( is_control_flow_instr ),

22
src/if_stage.sv
View file

@ -41,37 +41,19 @@ module if_stage (
input logic instr_ack_i,
output exception ex_o
);
// output logic illegal_compressed_instr_o -> in exception
logic fetch_valid;
logic prefetch_busy;
// ---------------------
// IF <-> ID Registers
// ---------------------
logic instr_valid_n, instr_valid_q;
// Pre-fetch buffer, caches a fixed number of instructions
prefetch_buffer prefetch_buffer_i (
.ready_i ( instr_ack_i ),
.valid_o ( fetch_valid ),
.valid_o ( fetch_entry_valid_i ),
// Prefetch Buffer Status
.busy_o ( prefetch_busy ),
.*
);
assign if_busy_o = prefetch_busy;
assign fetch_entry_valid_i = instr_valid_q;
// Pipeline registers
always_comb begin
// Instruction is valid, latch new data
instr_valid_n = fetch_valid;
if (flush_i) begin
instr_valid_n = 1'b0;
end
// TODO: exception forwarding in here
end
// --------------------------------------------------------------
// IF-ID pipeline registers, frozen when the ID stage is stalled
@ -79,9 +61,7 @@ module if_stage (
always_ff @(posedge clk_i, negedge rst_ni) begin : IF_ID_PIPE_REGISTERS
if (~rst_ni) begin
ex_o <= '{default: 0};
instr_valid_q <= 1'b0;
end else begin
instr_valid_q <= instr_valid_n;
ex_o.cause <= 64'b0; // TODO: Output exception
ex_o.tval <= 64'b0; // TODO: Output exception
ex_o.valid <= 1'b0; //illegal_compressed_instr; // TODO: Output exception

2
tb/fetch_fifo_tb.sv
View file

@ -36,7 +36,7 @@ module fetch_fifo_tb;
.in_rdata_i ( fetch_fifo_if.in_rdata ),
.in_valid_i ( fetch_fifo_if.in_valid ),
.in_ready_o ( fetch_fifo_if.in_ready ),
.fetch_entry_o ( fetch_fifo_if.fetch_entry ),
.fetch_entry_o ( fetch_fifo_if.fetch_entry ),
.out_valid_o ( fetch_fifo_if.out_valid ),
.out_ready_i ( fetch_fifo_if.out_ready )
);