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Disable FPU for the verilator target by default
This commit is contained in:
Florian Zaruba 2018-10-13 16:15:56 +02:00
parent 891579aaab
commit ca51c8ed48
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GPG key ID: E742FFE8EC38A792
4 changed files with 28 additions and 26 deletions
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33
Makefile
View file

@ -29,24 +29,23 @@ torture-logs := -log
# Sources
# Package files -> compile first
ariane_pkg := include/riscv_pkg.sv \
src/debug/dm_pkg.sv \
include/ariane_pkg.sv \
include/std_cache_pkg.sv \
src/axi/src/axi_pkg.sv \
include/axi_intf.sv \
src/fpu/src/pkg/fpnew_pkg.vhd \
src/fpu/src/pkg/fpnew_fmts_pkg.vhd \
src/fpu/src/pkg/fpnew_comps_pkg.vhd \
src/fpu/src/pkg/fpnew_pkg_constants.vhd
ariane_pkg := include/riscv_pkg.sv \
src/debug/dm_pkg.sv \
include/ariane_pkg.sv \
include/std_cache_pkg.sv \
src/axi/src/axi_pkg.sv \
include/axi_intf.sv \
src/fpu/src/pkg/fpnew_pkg.vhd \
src/fpu/src/pkg/fpnew_fmts_pkg.vhd \
src/fpu/src/pkg/fpnew_comps_pkg.vhd \
src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
src/fpu/src/pkg/fpnew_pkg_constants.vhd
# utility modules
util := $(wildcard src/util/*.svh) \
src/util/instruction_tracer_pkg.sv \
src/util/instruction_tracer_if.sv \
src/tech_cells_generic/src/cluster_clock_gating.sv \
src/tech_cells_generic/src/cluster_clock_inverter.sv \
src/tech_cells_generic/src/pulp_clock_mux2.sv \
src/util/sram.sv
# Test packages
@ -60,8 +59,8 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
$(wildcard src/fpu/src/utils/*.vhd) \
$(wildcard src/fpu/src/ops/*.vhd) \
$(wildcard src/fpu/src/subunits/*.vhd) \
src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
$(wildcard src/fpu_div_sqrt_mvp/hdl/*.sv) \
$(filter-out src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \
$(wildcard src/fpu_div_sqrt_mvp/hdl/*.sv)) \
$(wildcard src/frontend/*.sv) \
$(wildcard src/cache_subsystem/*.sv) \
$(wildcard bootrom/*.sv) \
@ -90,6 +89,8 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
src/common_cells/src/lzc.sv \
src/common_cells/src/rrarbiter.sv \
src/common_cells/src/lfsr_8bit.sv \
src/tech_cells_generic/src/cluster_clock_inverter.sv \
src/tech_cells_generic/src/pulp_clock_mux2.sv \
tb/ariane_testharness.sv \
tb/common/SimDTM.sv \
tb/common/SimJTAG.sv
@ -210,8 +211,8 @@ check-benchmarks:
# verilator-specific
verilate_command := $(verilator) \
$(ariane_pkg) \
$(filter-out tb/ariane_bt.sv,$(src)) \
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
+define+$(defines) \
src/util/sram.sv \
+incdir+src/axi_node \

14
include/ariane_pkg.sv
View file

@ -35,15 +35,15 @@ package ariane_pkg;
localparam ENABLE_RENAME = 1'b1;
// Floating-point extensions configuration
localparam bit RVF = 1'b1; // Is F extension enabled
localparam bit RVD = 1'b1; // Is D extension enabled
localparam bit RVA = 1'b0; // Is A extension enabled
localparam bit RVF = 1'b0; // Is F extension enabled
localparam bit RVD = 1'b0; // Is D extension enabled
localparam bit RVA = 1'b1; // Is A extension enabled
// Transprecision floating-point extensions configuration
localparam bit XF16 = 1'b1; // Is half-precision float extension (Xf16) enabled
localparam bit XF16ALT = 1'b1; // Is alternative half-precision float extension (Xf16alt) enabled
localparam bit XF8 = 1'b1; // Is quarter-precision float extension (Xf8) enabled
localparam bit XFVEC = 1'b1; // Is vectorial float extension (Xfvec) enabled
localparam bit XF16 = 1'b0; // Is half-precision float extension (Xf16) enabled
localparam bit XF16ALT = 1'b0; // Is alternative half-precision float extension (Xf16alt) enabled
localparam bit XF8 = 1'b0; // Is quarter-precision float extension (Xf8) enabled
localparam bit XFVEC = 1'b0; // Is vectorial float extension (Xfvec) enabled
// Transprecision float unit
localparam logic [30:0] LAT_COMP_FP32 = 'd3;

2
src/fpu_div_sqrt_mvp

@ -1 +1 @@
Subproject commit 962b37d464de4809b3e56b4c45451f2c459e338f
Subproject commit 3736c4c844074bd64c3c505c017181db71b738b4

5
src/issue_read_operands.sv
View file

@ -365,11 +365,12 @@ module issue_read_operands #(
// pack signals
logic [2:0][4:0] fp_raddr_pack;
logic [NR_COMMIT_PORTS-1:0][63:0] fp_wdata_pack;
assign fp_raddr_pack = {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]};
assign fp_wdata_pack = {wdata_i[1][FLEN-1:0], wdata_i[0][FLEN-1:0]};
generate
if (FP_PRESENT) begin : float_regfile_gen
assign fp_raddr_pack = {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]};
assign fp_wdata_pack = {wdata_i[1][FLEN-1:0], wdata_i[0][FLEN-1:0]};
ariane_regfile #(
.DATA_WIDTH ( FLEN ),
.NR_READ_PORTS ( 3 ),