Wire-up machine mode interrupt request

src/ariane.sv

@@ -55,7 +55,7 @@ module ariane
         AXI_BUS.Master                         data_if,
         AXI_BUS.Master                         bypass_if,
         // Interrupt inputs
-        input  logic                           irq_i,                 // level sensitive IR lines
+        input  logic [1:0]                     irq_i,        // level sensitive IR lines, mip & sip
         input  logic [4:0]                     irq_id_i,
         output logic                           irq_ack_o,
         input  logic                           irq_sec_i,

src/csr_regfile.sv

@@ -67,7 +67,7 @@ module csr_regfile #(
     output logic [43:0]           satp_ppn_o,
     output logic [ASID_WIDTH-1:0] asid_o,
     // external interrupts
-    input  logic                  irq_i,                      // external interrupt in
+    input  logic [1:0]            irq_i,                      // external interrupt in
     // Visualization Support
     output logic                  tvm_o,                      // trap virtual memory
     output logic                  tw_o,                       // timeout wait
@@ -383,7 +383,7 @@ module csr_regfile #(
         // Machine Mode External Interrupt Pending
         // TODO: this is wrong for sure
         mip_d[11] = 1'b0;
-        mip_d[9] = mie_q[9] & irq_i;
+        mip_d[9] = mie_q[9] & irq_i[0];
         // Timer interrupt pending, coming from platform timer
         mip_d[7] = time_irq_i;
 

src_files.yml

@@ -40,6 +40,7 @@ ariane:
     src/nbdcache.sv,
     src/miss_handler.sv,
     src/cache_ctrl.sv,
+    src/perf_counters.sv,
     ]
 riscv_regfile_rtl:
   targets: [
@@ -51,6 +52,7 @@ riscv_regfile_rtl:
   ]
   files: [
     src/regfile.sv,
+    src/util/gf22_sram.sv,
   ]
 
 riscv_regfile_fpga: