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mmu: Fix pmpcfg, pmpaddr width (#2707)
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PR #2692 changed the bus width for `pmpcfg` and `pmpaddr` in most
modules. Do the same in `cva6_mmu` and `cva6_ptw` to fix port width
mismatches.
This commit is contained in:
Nils Wistoff 2025-01-15 21:17:37 +11:00 • committed by GitHub
parent b28545ef78
commit cb5c623e50
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2 changed files with 4 additions and 4 deletions
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4
core/cva6_mmu/cva6_mmu.sv
View file

@ -100,8 +100,8 @@ module cva6_mmu
// PMP
input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i,
input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i
input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i,
input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i
);
// memory management, pte for cva6

4
core/cva6_mmu/cva6_ptw.sv
View file

@ -83,8 +83,8 @@ module cva6_ptw
output logic shared_tlb_miss_o,
// PMP
input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i,
input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i,
input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i,
input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i,
output logic [CVA6Cfg.PLEN-1:0] bad_paddr_o,
output logic [CVA6Cfg.GPLEN-1:0] bad_gpaddr_o
);