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Remove cv32a6_embedded configuration (#2246)

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JeanRochCoulon 2024-06-14 08:30:17 +02:00 • committed by GitHub
parent e26267b220
commit cb6211bbb8
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12 changed files with 8 additions and 2133 deletions
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2
.gitlab-ci/expected_synth.yml
View file

@ -1,4 +1,2 @@
cv32a6_embedded:
gates: 110095
cv32a65x:
gates: 128497

2
.gitlab-ci/scripts/report_benchmark.py
View file

@ -18,7 +18,7 @@ iterations = None
# Will fail if the number of cycles is different from this one
valid_cycles = {
'dhrystone': 217900,
'coremark': 665193,
'coremark': 686479,
}
for arg in sys.argv[1:]:

0
core/include/cv32a6_embedded_config_pkg.sv → core/include/cv32a6_embedded_config_pkg_deprecated.sv
View file

14
util/user_config.py
View file

@ -253,15 +253,9 @@ def write_file(path, lines):
# Command line interface
if __name__ == "__main__":
if len(sys.argv) == 2:
target = sys.argv[1]
config = get_config(f"core/include/{target}_config_pkg.sv")
for k, v in config.items():
print(f"{k} = {v}")
elif len(sys.argv) > 1:
base, changes = parse_derive_args(sys.argv[1:])
base, changes = parse_derive_args(sys.argv[1:])
input_file = f"core/include/{base}_config_pkg.sv"
output_file = "core/include/gen_config_pkg.sv"
input_file = f"core/include/{base}_config_pkg.sv"
output_file = "core/include/gen_config_pkg.sv"
derive_config(input_file, output_file, changes)
derive_config(input_file, output_file, changes)

4
verif/regress/coremark.sh
View file

@ -78,14 +78,14 @@ cflags=(
-DNOPRINT
)
default_config="cv32a6_embedded"
default_config="cv32a65x"
isa="rv32imc_zba_zbb_zbc_zbs"
set -x
python3 cva6.py \
--target hwconfig \
--isa "$isa" \
--hwconfig_opts="$default_config +CVA6ConfigNrLoadPipeRegs=0" \
--hwconfig_opts="$default_config" \
--iss="$DV_SIMULATORS" \
--iss_yaml=cva6.yaml \
--c_tests "$src0" \

2
verif/regress/smoke-gen_tests.sh
View file

@ -24,7 +24,7 @@ source ./verif/regress/install-spike.sh
source verif/sim/setup-env.sh
if ! [ -n "$DV_TARGET" ]; then
DV_TARGET=cv32a6_embedded
DV_TARGET=cv32a65x
fi
if ! [ -n "$DV_SIMULATORS" ]; then

7
verif/regress/smoke-tests.sh
View file

@ -55,13 +55,6 @@ python3 cva6.py --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS --iss_yaml=cva6.y
--gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common" $DV_OPTS
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a6_embedded --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a6_embedded --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a6_embedded --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --target cv32a6_embedded --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../tests/custom/common/test.ld\
--gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common" $DV_OPTS
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld

4
verif/sim/cva6.py
View file

@ -997,10 +997,6 @@ def load_config(args, cwd):
elif args.target == "cv32a60x": # step1 configuration
args.mabi = "ilp32"
args.isa = "rv32imac_zba_zbb_zbs_zbc"
elif args.target == "cv32a6_embedded":
args.mabi = "ilp32"
args.isa = "rv32imc_zba_zbb_zbs_zbc"
args.priv = "m"
elif args.target == "cv32a65x":
args.mabi = "ilp32"
args.isa = "rv32imc_zba_zbb_zbs_zbc"

564
verif/tests/testlist_riscv-arch-test-cv32a6_embedded.yaml
View file

@ -1,564 +0,0 @@
# Copyright Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ================================================================================
# Regression test list format
# --------------------------------------------------------------------------------
# testlist : Assembly test list
# test : Assembly test name
# description : Description of this test
# gen_opts : Instruction generator options
# iterations : Number of iterations of this test
# no_iss : Enable/disable ISS simulator (Optional)
# gen_test : Test name used by the instruction generator
# asm_tests : Path to directed, hand-coded assembly test file or directory
# rtl_test : RTL simulation test name
# cmp_opts : Compile options passed to the instruction generator
# sim_opts : Simulation options passed to the instruction generator
# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
# compare_opts : Options for the RTL & ISS trace comparison
# gcc_opts : gcc compile options
# --------------------------------------------------------------------------------
## C
common_test_config: &common_test_config
path_var: TESTS_PATH
gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/"
testlist:
- test: rv32im-cadd-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S
- test: rv32im-caddi-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi-01.S
- test: rv32im-caddi16sp-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S
- test: rv32im-caddi4spn-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S
- test: rv32im-cand-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cand-01.S
- test: rv32im-candi-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/candi-01.S
- test: rv32im-cbeqz-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S
- test: rv32im-cbnez-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbnez-01.S
- test: rv32im-cebreak-01
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cebreak-01.S
- test: rv32im-cj-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cj-01.S
- test: rv32im-cjal-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjal-01.S
- test: rv32im-cjalr-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjalr-01.S
- test: rv32im-cjr-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjr-01.S
- test: rv32im-cli-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cli-01.S
- test: rv32im-clui-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clui-01.S
- test: rv32im-clw-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clw-01.S
- test: rv32im-clwsp-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clwsp-01.S
- test: rv32im-cmv-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cmv-01.S
- test: rv32im-cnop-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cnop-01.S
- test: rv32im-cor-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cor-01.S
- test: rv32im-cslli-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cslli-01.S
- test: rv32im-csrai-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrai-01.S
- test: rv32im-csrli-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrli-01.S
- test: rv32im-csub-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csub-01.S
- test: rv32im-csw-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csw-01.S
- test: rv32im-cswsp-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cswsp-01.S
- test: rv32im-cxor-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cxor-01.S
# I
- test: rv32im-add-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S
- test: rv32im-addi-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S
- test: rv32im-and-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S
- test: rv32im-andi-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S
- test: rv32im-auipc-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S
- test: rv32im-beq-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S
- test: rv32im-bge-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S
- test: rv32im-bgeu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S
- test: rv32im-blt-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S
- test: rv32im-bltu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S
- test: rv32im-bne-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S
- test: rv32im-fence-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S
- test: rv32im-jal-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S
- test: rv32im-jalr-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S
- test: rv32im-lb-align-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S
- test: rv32im-lbu-align-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S
- test: rv32im-lh-align-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S
- test: rv32im-lhu-align-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S
- test: rv32im-lui-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S
- test: rv32im-lw-align-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S
- test: rv32im-or-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S
- test: rv32im-ori-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S
- test: rv32im-sb-align-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S
- test: rv32im-sh-align-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S
- test: rv32im-sll-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S
- test: rv32im-slli-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S
- test: rv32im-slt-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S
- test: rv32im-slti-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S
- test: rv32im-sltiu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S
- test: rv32im-sltu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S
- test: rv32im-sra-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S
- test: rv32im-srai-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S
- test: rv32im-srl-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S
- test: rv32im-srli-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S
- test: rv32im-sub-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S
- test: rv32im-sw-align-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S
- test: rv32im-xor-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S
- test: rv32im-xori-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S
# M
- test: rv32im-div-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/div-01.S
- test: rv32im-divu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/divu-01.S
- test: rv32im-mul-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mul-01.S
- test: rv32im-mulh-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulh-01.S
- test: rv32im-mulhsu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S
- test: rv32im-mulhu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhu-01.S
- test: rv32im-rem-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/rem-01.S
- test: rv32im-remu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/remu-01.S
- test: rv32im-andn-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/andn-01.S
- test: rv32im-bclr-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bclr-01.S
- test: rv32im-bclri-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bclri-01.S
- test: rv32im-bext-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bext-01.S
- test: rv32im-bexti-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bexti-01.S
- test: rv32im-binv-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/binv-01.S
- test: rv32im-binvi-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/binvi-01.S
- test: rv32im-bset-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bset-01.S
- test: rv32im-bseti-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/bseti-01.S
- test: rv32im-clmul-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/clmul-01.S
- test: rv32im-clmulh-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/clmulh-01.S
- test: rv32im-clmulr-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/clmulr-01.S
- test: rv32im-clz-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/clz-01.S
- test: rv32im-cpop-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/cpop-01.S
- test: rv32im-ctz-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/ctz-01.S
- test: rv32im-max-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/max-01.S
- test: rv32im-maxu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/maxu-01.S
- test: rv32im-min-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/min-01.S
- test: rv32im-minu-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/minu-01.S
- test: rv32im-orcb_32-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/orcb_32-01.S
- test: rv32im-orn-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/orn-01.S
- test: rv32im-rev8_32-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/rev8_32-01.S
- test: rv32im-rol-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/rol-01.S
- test: rv32im-ror-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/ror-01.S
- test: rv32im-rori-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/rori-01.S
- test: rv32im-sext.b-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sext.b-01.S
- test: rv32im-sext.h-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sext.h-01.S
- test: rv32im-sh1add-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sh1add-01.S
- test: rv32im-sh2add-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sh2add-01.S
- test: rv32im-sh3add-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/sh3add-01.S
- test: rv32im-xnor-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/xnor-01.S
- test: rv32im-zext.h_32-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/zext.h_32-01.S

954
verif/tests/testlist_riscv-compliance-cv32a6_embedded.yaml
View file

@ -1,954 +0,0 @@
# Copyright Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ================================================================================
# Regression test list format
# --------------------------------------------------------------------------------
# testlist : Assembly test list
# test : Assembly test name
# description : Description of this test
# gen_opts : Instruction generator options
# iterations : Number of iterations of this test
# no_iss : Enable/disable ISS simulator (Optional)
# gen_test : Test name used by the instruction generator
# asm_tests : Path to directed, hand-coded assembly test file or directory
# rtl_test : RTL simulation test name
# cmp_opts : Compile options passed to the instruction generator
# sim_opts : Simulation options passed to the instruction generator
# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
# compare_opts : Options for the RTL & ISS trace comparison
# gcc_opts : gcc compile options
# --------------------------------------------------------------------------------
#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml
common_test_config: &common_test_config
path_var: TESTS_PATH
gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/"
testlist:
- test: rv64im-REMUW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/REMUW.S
- test: rv64im-MULW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/MULW.S
- test: rv64i-SRAW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAW.S
- test: rv64i-ADDW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDW.S
- test: rv64i-ADDIW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDIW.S
- test: rv64i-SLLW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLW.S
- test: rv64i-SUBW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SUBW.S
- test: rv64i-SRLW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLW.S
- test: rv64i-SLLIW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLIW.S
- test: rv64i-SRLIW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLIW.S
- test: rv64i-SRAIW
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAIW.S
- test: rv32uc-rvc
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uc/src/rvc.S
- test: rv32Zifencei-I-FENCE.I-01 # FAILED on spike
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S
- test: rv32im-MULHSU
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHSU.S
- test: rv32im-DIVU
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIVU.S
- test: rv32im-REMU
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REMU.S
- test: rv32im-MUL
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MUL.S
- test: rv32im-DIV
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIV.S
- test: rv32im-MULH
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULH.S
- test: rv32im-MULHU
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHU.S
- test: rv32im-REM
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REM.S
- test: rv32ui-jal
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jal.S
- test: rv32ui-bge
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bge.S
- test: rv32ui-blt
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/blt.S
- test: rv32ui-bgeu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bgeu.S
- test: rv32ui-sw
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sw.S
- test: rv32ui-lbu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lbu.S
- test: rv32ui-sb
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sb.S
- test: rv32ui-sw
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slti.S
- test: rv32ui-sra
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sra.S
- test: rv32ui-srl
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srl.S
- test: rv32ui-sh
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sh.S
- test: rv32ui-lw
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lw.S
- test: rv32ui-andi
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/andi.S
- test: rv32ui-srli
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srli.S
- test: rv32ui-slli
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slli.S
- test: rv32ui-beq
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/beq.S
- test: rv32ui-sll
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sll.S
- test: rv32ui-addi
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/addi.S
- test: rv32ui-lh
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lh.S
- test: rv32ui-and
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/and.S
- test: rv32ui-xori
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xori.S
- test: rv32ui-sub
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sub.S
- test: rv32ui-slt
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slt.S
- test: rv32ui-lb
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lb.S
- test: rv32ui-or
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/or.S
- test: rv32ui-lui
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lui.S
- test: rv32ui-ori
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/ori.S
- test: rv32ui-bltu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bltu.S
- test: rv32ui-fence_i
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/fence_i.S
- test: rv32ui-auipc
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/auipc.S
- test: rv32ui-srai
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srai.S
- test: rv32ui-jalr
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jalr.S
- test: rv32ui-xor
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xor.S
- test: rv32ui-simple
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/simple.S
- test: rv32ui-lhu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lhu.S
- test: rv32ui-bne
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bne.S
- test: rv32ui-add
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/add.S
- test: rv32ui-sltiu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltiu.S
- test: rv32ui-sltu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltu.S
- test: rv32mi-sbreak
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/sbreak.S
- test: rv32mi-breakpoint
iterations: 0 # csrr a0, tdata1 => 0x20000000 (spike), 0x00000000 (cva6)
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/breakpoint.S
- test: rv32mi-scall
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/scall.S
- test: rv32mi-ma_addr
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_addr.S
- test: rv32mi-mcsr
iterations: 0 # expected as different marchid
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/mcsr.S
- test: rv32mi-ma_fetch
iterations: 0 # expected as different misa
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_fetch.S
- test: rv32mi-shamt
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/shamt.S
- test: rv32mi-illegal
iterations: 0 # cva6 does not record illegal instructions in log file
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/illegal.S
- test: rv32mi-csr
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/csr.S
- test: rv32i-I-AND-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AND-01.S
- test: rv32i-I-BNE-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BNE-01.S
- test: rv32i-I-IO
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-IO.S
- test: rv32i-I-BLT-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLT-01.S
- test: rv32i-I-SB-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SB-01.S
- test: rv32i-I-MISALIGN_LDST-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S
- test: rv32i-I-ECALL-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S
- test: rv32i-I-LHU-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LHU-01.S
- test: rv32i-I-SRLI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S
- test: rv32i-I-BLTU-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S
- test: rv32i-I-LH-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LH-01.S
- test: rv32i-I-AUIPC-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S
- test: rv32i-I-ORI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ORI-01.S
- test: rv32i-I-SLLI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S
- test: rv32i-I-RF_width-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_width-01.S
- test: rv32i-I-XOR-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XOR-01.S
- test: rv32i-I-DELAY_SLOTS-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-DELAY_SLOTS-01.S
- test: rv32i-I-EBREAK-01 # infinite loop with spike
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S
- test: rv32i-I-SRAI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S
- test: rv32i-I-SLTU-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S
- test: rv32i-I-OR-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-OR-01.S
- test: rv32i-I-MISALIGN_JMP-01 # infinite loop with spike
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S
- test: rv32i-I-JALR-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JALR-01.S
- test: rv32i-I-XORI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XORI-01.S
- test: rv32i-I-ADDI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S
- test: rv32i-I-BGE-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGE-01.S
- test: rv32i-I-ANDI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S
- test: rv32i-I-SH-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SH-01.S
- test: rv32i-I-SLT-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLT-01.S
- test: rv32i-I-SLTIU-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S
- test: rv32i-I-SLL-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLL-01.S
- test: rv32i-I-SRL-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRL-01.S
- test: rv32i-I-LUI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LUI-01.S
- test: rv32i-I-SUB-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SUB-01.S
- test: rv32i-I-LB-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LB-01.S
- test: rv32i-I-LW-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LW-01.S
- test: rv32i-I-SW-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SW-01.S
- test: rv32i-I-SLTI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S
- test: rv32i-I-SRA-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRA-01.S
- test: rv32i-I-RF_size-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_size-01.S
- test: rv32i-I-BEQ-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S
- test: rv32i-I-BGEU-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S
- test: rv32i-I-JAL-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JAL-01.S
- test: rv32i-I-LBU-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LBU-01.S
- test: rv32i-I-ENDIANESS-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ENDIANESS-01.S
- test: rv32i-I-RF_x0-01 # assembly error
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_x0-01.S
- test: rv32i-I-NOP-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-NOP-01.S
- test: rv32i-I-ADD-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S
- test: rv32si-sbreak
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/sbreak.S
- test: rv32si-scall
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/scall.S
- test: rv32si-ma_fetch
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/ma_fetch.S
- test: rv32si-wfi
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/wfi.S
- test: rv32si-dirty
iterations: 0 # exception on spike
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/dirty.S
- test: rv32si-csr
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/csr.S
- test: rv32imc-C-LW
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LW.S
- test: rv32imc-C-LWSP
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LWSP.S
- test: rv32imc-C-ADD
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADD.S
- test: rv32imc-C-JAL # assembly error
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JAL.S
- test: rv32imc-C-SRAI
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRAI.S
- test: rv32imc-C-JALR
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JALR.S
- test: rv32imc-C-XOR
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-XOR.S
- test: rv32imc-C-SUB
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SUB.S
- test: rv32imc-C-ADDI
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI.S
- test: rv32imc-C-BEQZ
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BEQZ.S
- test: rv32imc-C-ADDI16SP
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI16SP.S
- test: rv32imc-C-LI
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LI.S
- test: rv32imc-C-SW
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SW.S
- test: rv32imc-C-OR
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-OR.S
- test: rv32imc-C-ADDI4SPN
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI4SPN.S
- test: rv32imc-C-AND
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-AND.S
- test: rv32imc-C-SRLI
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRLI.S
- test: rv32imc-C-SWSP
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SWSP.S
- test: rv32imc-C-SLLI
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SLLI.S
- test: rv32imc-C-JR
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JR.S
- test: rv32imc-C-BNEZ
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BNEZ.S
- test: rv32imc-C-MV
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-MV.S
- test: rv32imc-C-LUI
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LUI.S
- test: rv32imc-C-J
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-J.S
- test: rv32imc-C-ANDI
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ANDI.S
- test: rv32Zicsr-I-CSRRC-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S
- test: rv32Zicsr-I-CSRRS-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S
- test: rv32Zicsr-I-CSRRSI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S
- test: rv32Zicsr-I-CSRRW-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S
- test: rv32Zicsr-I-CSRRCI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S
- test: rv32Zicsr-I-CSRRWI-01
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S
- test: rv32ua-amoxor_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoxor_w.S
- test: rv32ua-amoadd_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoadd_w.S
- test: rv32ua-amoor_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoor_w.S
- test: rv32ua-amomin_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomin_w.S
- test: rv32ua-amoand_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoand_w.S
- test: rv32ua-amomaxu_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomaxu_w.S
- test: rv32ua-amoswap_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoswap_w.S
- test: rv32ua-amominu_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amominu_w.S
- test: rv32ua-amomax_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomax_w.S
- test: rv32uf-fclass
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fclass.S
- test: rv32uf-ldst
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/ldst.S
- test: rv32uf-fmadd
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmadd.S
- test: rv32uf-recoding
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/recoding.S
- test: rv32uf-fcvt
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt.S
- test: rv32uf-fcmp
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcmp.S
- test: rv32uf-fcvt_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt_w.S
- test: rv32uf-fadd
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fadd.S
- test: rv32uf-fmin
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmin.S
- test: rv32uf-move
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/move.S
- test: rv32uf-fdiv
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fdiv.S
- test: rv32ud-fclass
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fclass.S
- test: rv32ud-ldst
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/ldst.S
- test: rv32ud-fmadd
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmadd.S
- test: rv32ud-recoding
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/recoding.S
- test: rv32ud-fcvt
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcvt.S
- test: rv32ud-fcmp
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcmp.S
- test: rv32ud-fadd
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fadd.S
- test: rv32ud-fmin
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmin.S
- test: rv32ud-fdiv
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fdiv.S

75
verif/tests/testlist_riscv-csr-access-test-cv32a6_embedded.yaml
View file

@ -1,75 +0,0 @@
## // Copyright 2023 Thales
## // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#
# ================================================================================
# Regression test list format
# --------------------------------------------------------------------------------
# testlist : Assembly test list
# test : Assembly test name
# description : Description of this test
# gen_opts : Instruction generator options
# iterations : Number of iterations of this test
# no_iss : Enable/disable ISS simulator (Optional)
# gen_test : Test name used by the instruction generator
# asm_tests : Path to directed, hand-coded assembly test file or directory
# rtl_test : RTL simulation test name
# cmp_opts : Compile options passed to the instruction generator
# sim_opts : Simulation options passed to the instruction generator
# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
# compare_opts : Options for the RTL & ISS trace comparison
# gcc_opts : gcc compile options
# --------------------------------------------------------------------------------
common_test_config: &common_test_config
path_var: TESTS_PATH
gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/"
# Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first.
# It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation.
testlist:
- test: M_RW_CSR
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S
- test: S_RW_CSR
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S
- test: M_RO_CSR
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S
- test: M_MCYCLE_CSR
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_mcycle_csr_test_0.S
- test: M_MCYCLEH_CSR
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_mcycleh_csr_test_0.S
- test: M_MINSTRET_CSR
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_minstret_csr_test_0.S
- test: M_MINSTRETH_CSR
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_minstreth_csr_test_0.S
- test: U_CYCLE_CSR
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S
- test: U_INSTRET_CSR
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_instret_csr_test_0.S

513
verif/tests/testlist_riscv-tests-cv32a6_embedded-p.yaml
View file

@ -1,513 +0,0 @@
# Copyright Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ================================================================================
# Regression test list format
# --------------------------------------------------------------------------------
# testlist : Assembly test list
# test : Assembly test name
# description : Description of this test
# gen_opts : Instruction generator options
# iterations : Number of iterations of this test
# no_iss : Enable/disable ISS simulator (Optional)
# gen_test : Test name used by the instruction generator
# asm_tests : Path to directed, hand-coded assembly test file or directory
# rtl_test : RTL simulation test name
# cmp_opts : Compile options passed to the instruction generator
# sim_opts : Simulation options passed to the instruction generator
# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
# compare_opts : Options for the RTL & ISS trace comparison
# gcc_opts : gcc compile options
# --------------------------------------------------------------------------------
#- import: <riscv_dv_root>/target/rv32imc/testlist.yaml
common_test_config: &common_test_config
path_var: TESTS_PATH
gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/"
testlist:
# ISA tests
- test: rv32ui-p-add
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S
- test: rv32ui-p-addi
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/addi.S
- test: rv32ui-p-and
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/and.S
- test: rv32ui-p-andi
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/andi.S
- test: rv32ui-p-auipc
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/auipc.S
- test: rv32ui-p-beq
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/beq.S
- test: rv32ui-p-bge
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/bge.S
- test: rv32ui-p-bgeu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/bgeu.S
- test: rv32ui-p-blt
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/blt.S
- test: rv32ui-p-bltu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/bltu.S
- test: rv32ui-p-bne
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/bne.S
- test: rv32ui-p-simple
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/simple.S
- test: rv32ui-p-fence_i
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/fence_i.S
- test: rv32ui-p-jal
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/jal.S
- test: rv32ui-p-jalr
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/jalr.S
- test: rv32ui-p-lb
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/lb.S
- test: rv32ui-p-lbu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/lbu.S
- test: rv32ui-p-lh
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/lh.S
- test: rv32ui-p-lhu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/lhu.S
- test: rv32ui-p-lw
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/lw.S
- test: rv32ui-p-lui
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/lui.S
- test: rv32ui-p-or
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/or.S
- test: rv32ui-p-ori
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/ori.S
- test: rv32ui-p-sb
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/sb.S
- test: rv32ui-p-sh
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/sh.S
- test: rv32ui-p-sw
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/sw.S
- test: rv32ui-p-sll
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/sll.S
- test: rv32ui-p-slli
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/slli.S
- test: rv32ui-p-slt
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/slt.S
- test: rv32ui-p-slti
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/slti.S
- test: rv32ui-p-sltiu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltiu.S
- test: rv32ui-p-sltu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltu.S
- test: rv32ui-p-sra
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/sra.S
- test: rv32ui-p-srai
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/srai.S
- test: rv32ui-p-srl
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/srl.S
- test: rv32ui-p-srli
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/srli.S
- test: rv32ui-p-sub
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/sub.S
- test: rv32ui-p-xor
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/xor.S
- test: rv32ui-p-xori
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ui/xori.S
- test: rv32mi-p-breakpoint
iterations: 0 # csrr a0, tdata1 => 0x20000000 (spike), 0x00000000 (cva6)
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/breakpoint.S
- test: rv32mi-p-csr
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/csr.S
- test: rv32mi-p-mcsr
iterations: 0 # expected as different marchid
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/mcsr.S
- test: rv32mi-p-illegal
iterations: 0 # cva6 does not record illegal instructions in log file
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/illegal.S
- test: rv32mi-p-ma_addr
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/ma_addr.S
- test: rv32mi-p-ma_fetch
iterations: 0 # expected as different misa
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/ma_fetch.S
- test: rv32mi-p-sbreak
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/sbreak.S
- test: rv32mi-p-scall
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/scall.S
- test: rv32mi-p-shamt
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32mi/shamt.S
- test: rv32si-p-csr
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32si/csr.S
- test: rv32si-p-ma_fetch
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32si/ma_fetch.S
- test: rv32si-p-scall
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32si/scall.S
- test: rv32si-p-wfi
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32si/wfi.S
- test: rv32si-p-sbreak
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32si/sbreak.S
- test: rv32si-p-dirty
iterations: 0 # to be explained
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32si/dirty.S
- test: rv32uc-p-rvc
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uc/rvc.S
# FPU tests
- test: rv32uf-p-fadd
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/fadd.S
- test: rv32uf-p-fclass
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/fclass.S
- test: rv32uf-p-fcmp
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcmp.S
- test: rv32uf-p-fcvt
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt.S
- test: rv32uf-p-fcvt_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt_w.S
- test: rv32uf-p-fdiv
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/fdiv.S
- test: rv32uf-p-fmadd
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmadd.S
- test: rv32uf-p-fmin
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmin.S
- test: rv32uf-p-ldst
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/ldst.S
- test: rv32uf-p-move
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/move.S
- test: rv32uf-p-recoding
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32uf/recoding.S
- test: rv32ud-p-fadd
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/fadd.S
- test: rv32ud-p-fclass
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/fclass.S
- test: rv32ud-p-fcmp
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcmp.S
- test: rv32ud-p-fcvt
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt.S
- test: rv32ud-p-fcvt_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt_w.S
- test: rv32ud-p-fdiv
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/fdiv.S
- test: rv32ud-p-fmadd
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmadd.S
- test: rv32ud-p-fmin
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmin.S
- test: rv32ud-p-ldst
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/ldst.S
- test: rv32ud-p-recoding
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ud/recoding.S
# MUL/DIV tests
- test: rv32um-p-div
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32um/div.S
- test: rv32um-p-divu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32um/divu.S
- test: rv32um-p-mul
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32um/mul.S
- test: rv32um-p-mulh
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32um/mulh.S
- test: rv32um-p-mulhsu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhsu.S
- test: rv32um-p-mulhu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhu.S
- test: rv32um-p-rem
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32um/rem.S
- test: rv32um-p-remu
iterations: 1
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32um/remu.S
# AMO tests
- test: rv32ua-p-amoadd_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoadd_w.S
- test: rv32ua-p-amoand_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoand_w.S
- test: rv32ua-p-amomax_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomax_w.S
- test: rv32ua-p-amomaxu_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomaxu_w.S
- test: rv32ua-p-amomin_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomin_w.S
- test: rv32ua-v-amominu_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amominu_w.S
- test: rv32ua-p-amoor_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoor_w.S
- test: rv32ua-p-amoxor_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoxor_w.S
- test: rv32ua-p-amoswap_w
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoswap_w.S
- test: rv32ua-p-lrsc
iterations: 0
<<: *common_test_config
asm_tests: <path_var>/riscv-tests/isa/rv32ua/lrsc.S