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Implement response side

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This commit is contained in:
Florian Zaruba 2017-05-29 16:25:27 +02:00
parent b7303e41d2
commit cb848654ff
2 changed files with 23 additions and 3 deletions
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24
tb/agents/dcache_if/dcache_if_driver.svh
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@ -33,6 +33,11 @@ class dcache_if_driver extends uvm_driver #(dcache_if_seq_item);
task run_phase(uvm_phase phase);
dcache_if_seq_item cmd;
logic [11:0] address_index [$];
logic [43:0] address_tag [$];
logic [55:0] address_out;
semaphore lock = new(1);
// --------------
// Slave Port
@ -64,7 +69,24 @@ class dcache_if_driver extends uvm_driver #(dcache_if_seq_item);
fork
// replay interface
mem_read: begin
// we've got a new request
if (m_vif.pck.data_gnt && m_vif.mck.data_req) begin
// push the low portion of the address a.k.a. the index
address_index.push_back(m_vif.mck.address_index);
lock.get(1);
// wait a couple of cycles, but at least one
@(m_vif.mck);
// in this cycle the tag is ready
address_tag.push_back(m_vif.mck.address_tag);
// randomize rvalid here
repeat ($urandom_range(0,2)) @(m_vif.mck);
m_vif.mck.data_rvalid <= 1'b1;
// compose the address
address_out = {address_tag.pop_front(), address_index.pop_front()};
// put back the lock
lock.put(1);
end else
m_vif.mck.data_rvalid <= 1'b0;
end
mem_write: begin

2
tb/agents/mem_if/mem_if_driver.svh
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@ -48,9 +48,7 @@ class mem_if_driver extends uvm_driver #(mem_if_seq_item);
logic [63:0] address [$];
logic [63:0] addr;
logic slave_data_gnt;
semaphore lock = new(1);
slave_data_gnt = 1'b1;
// we serve all requests from the memory file we store in our configuration object
// read memory file