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Fix race condition in dcache misshandler

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Michael Schaffner 2019-03-05 11:25:20 +01:00 • committed by Florian Zaruba
parent 0ffef2ae1a
commit cc0583d144
1 changed files with 9 additions and 2 deletions
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11
src/cache_subsystem/serpent_dcache_ctrl.sv
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@ -54,7 +54,7 @@ module serpent_dcache_ctrl #(
);
// controller FSM
typedef enum logic[2:0] {IDLE, READ, MISS_REQ, MISS_WAIT, KILL_MISS, REPLAY_REQ, REPLAY_READ} state_t;
typedef enum logic[2:0] {IDLE, READ, MISS_REQ, MISS_WAIT, KILL_MISS, KILL_MISS_ACK, REPLAY_REQ, REPLAY_READ} state_t;
state_t state_d, state_q;
logic [DCACHE_TAG_WIDTH-1:0] address_tag_d, address_tag_q;
@ -167,7 +167,7 @@ module serpent_dcache_ctrl #(
if(miss_ack_i) begin
state_d = KILL_MISS;
end else begin
state_d = IDLE;
state_d = KILL_MISS_ACK;
end
end else if(miss_replay_i) begin
state_d = REPLAY_REQ;
@ -203,6 +203,13 @@ module serpent_dcache_ctrl #(
end
end
//////////////////////////////////
KILL_MISS_ACK: begin
miss_req_o = 1'b1;
if(miss_ack_i) begin
state_d = KILL_MISS;
end
end
//////////////////////////////////
// killed miss,
// wait until miss unit responds and
// go back to idle