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hpdcache: update HPDcache to support parametrization (#2059)
This commit is contained in:
Cesar Fuguet
GitHub
parent
4c58b50045
commit
cd241cb387
7 changed files with 172 additions and 233 deletions
7
Makefile
7
Makefile
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@ -110,12 +110,6 @@ endif
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HPDCACHE_DIR ?= $(CVA6_REPO_DIR)/core/cache_subsystem/hpdcache
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export HPDCACHE_DIR
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# Target HPDcache configuration package.
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# The HPDCACHE_TARGET_CFG variable contains the path (relative or absolute)
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# to your target configuration package
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HPDCACHE_TARGET_CFG ?= ${CVA6_REPO_DIR}/core/include/cva6_hpdcache_default_config_pkg.sv
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export HPDCACHE_TARGET_CFG
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# Sources
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# Package files -> compile first
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ariane_pkg := \
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@ -692,7 +686,6 @@ check-torture:
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src_flist = $(shell \
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CVA6_REPO_DIR=$(CVA6_REPO_DIR) \
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TARGET_CFG=$(TARGET_CFG) \
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HPDCACHE_TARGET_CFG=$(HPDCACHE_TARGET_CFG) \
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HPDCACHE_DIR=$(HPDCACHE_DIR) \
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python3 util/flist_flattener.py core/Flist.cva6)
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fpga_filter := $(addprefix $(root-dir), corev_apu/bootrom/bootrom.sv)
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@ -159,7 +159,6 @@ ${CVA6_REPO_DIR}/core/cache_subsystem/cache_ctrl.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache_axi_wrapper.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/std_cache_subsystem.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/std_nbdcache.sv
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${HPDCACHE_TARGET_CFG}
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-F ${HPDCACHE_DIR}/rtl/hpdcache.Flist
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${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv
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${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv
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@ -10,15 +10,19 @@
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// Date: February, 2023
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// Description: Interface adapter for the CVA6 core
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module cva6_hpdcache_if_adapter
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import hpdcache_pkg::*;
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// Parameters
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// {{{
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter type dcache_req_i_t = logic,
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parameter type dcache_req_o_t = logic,
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parameter bit is_load_port = 1'b1
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter hpdcache_pkg::hpdcache_cfg_t hpdcacheCfg = '0,
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parameter type hpdcache_tag_t = logic,
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parameter type hpdcache_req_offset_t = logic,
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parameter type hpdcache_req_sid_t = logic,
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parameter type hpdcache_req_t = logic,
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parameter type hpdcache_rsp_t = logic,
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parameter type dcache_req_i_t = logic,
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parameter type dcache_req_o_t = logic,
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parameter bit is_load_port = 1'b1
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)
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// }}}
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@ -30,7 +34,7 @@ module cva6_hpdcache_if_adapter
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input logic rst_ni,
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// Port ID
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input hpdcache_pkg::hpdcache_req_sid_t hpdcache_req_sid_i,
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input hpdcache_req_sid_t hpdcache_req_sid_i,
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// Request/response ports from/to the CVA6 core
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input dcache_req_i_t cva6_req_i,
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@ -41,14 +45,14 @@ module cva6_hpdcache_if_adapter
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// Request port to the L1 Dcache
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output logic hpdcache_req_valid_o,
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input logic hpdcache_req_ready_i,
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output hpdcache_pkg::hpdcache_req_t hpdcache_req_o,
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output hpdcache_req_t hpdcache_req_o,
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output logic hpdcache_req_abort_o,
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output hpdcache_pkg::hpdcache_tag_t hpdcache_req_tag_o,
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output hpdcache_tag_t hpdcache_req_tag_o,
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output hpdcache_pkg::hpdcache_pma_t hpdcache_req_pma_o,
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// Response port from the L1 Dcache
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input logic hpdcache_rsp_valid_i,
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input hpdcache_pkg::hpdcache_rsp_t hpdcache_rsp_i
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input logic hpdcache_rsp_valid_i,
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input hpdcache_rsp_t hpdcache_rsp_i
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);
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// }}}
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@ -102,35 +106,35 @@ module cva6_hpdcache_if_adapter
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// {{{
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else begin : store_amo_gen
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// STORE/AMO request
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hpdcache_req_addr_t amo_addr;
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hpdcache_req_offset_t amo_addr_offset;
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hpdcache_tag_t amo_tag;
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logic [63:0] amo_addr;
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hpdcache_req_offset_t amo_addr_offset;
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hpdcache_tag_t amo_tag;
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logic amo_is_word, amo_is_word_hi;
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logic [63:0] amo_data;
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logic [ 7:0] amo_data_be;
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hpdcache_req_op_t amo_op;
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logic [31:0] amo_resp_word;
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logic amo_pending_q;
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logic [63:0] amo_data;
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logic [ 7:0] amo_data_be;
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hpdcache_pkg::hpdcache_req_op_t amo_op;
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logic [31:0] amo_resp_word;
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logic amo_pending_q;
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// AMO logic
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// {{{
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always_comb begin : amo_op_comb
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amo_addr = cva6_amo_req_i.operand_a;
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amo_addr_offset = amo_addr[0+:HPDCACHE_REQ_OFFSET_WIDTH];
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amo_tag = amo_addr[HPDCACHE_REQ_OFFSET_WIDTH+:HPDCACHE_TAG_WIDTH];
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amo_addr_offset = amo_addr[0+:hpdcacheCfg.reqOffsetWidth];
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amo_tag = amo_addr[hpdcacheCfg.reqOffsetWidth+:hpdcacheCfg.tagWidth];
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unique case (cva6_amo_req_i.amo_op)
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ariane_pkg::AMO_LR: amo_op = HPDCACHE_REQ_AMO_LR;
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ariane_pkg::AMO_SC: amo_op = HPDCACHE_REQ_AMO_SC;
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ariane_pkg::AMO_SWAP: amo_op = HPDCACHE_REQ_AMO_SWAP;
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ariane_pkg::AMO_ADD: amo_op = HPDCACHE_REQ_AMO_ADD;
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ariane_pkg::AMO_AND: amo_op = HPDCACHE_REQ_AMO_AND;
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ariane_pkg::AMO_OR: amo_op = HPDCACHE_REQ_AMO_OR;
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ariane_pkg::AMO_XOR: amo_op = HPDCACHE_REQ_AMO_XOR;
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ariane_pkg::AMO_MAX: amo_op = HPDCACHE_REQ_AMO_MAX;
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ariane_pkg::AMO_MAXU: amo_op = HPDCACHE_REQ_AMO_MAXU;
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ariane_pkg::AMO_MIN: amo_op = HPDCACHE_REQ_AMO_MIN;
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ariane_pkg::AMO_MINU: amo_op = HPDCACHE_REQ_AMO_MINU;
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default: amo_op = HPDCACHE_REQ_LOAD;
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ariane_pkg::AMO_LR: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_LR;
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ariane_pkg::AMO_SC: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_SC;
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ariane_pkg::AMO_SWAP: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_SWAP;
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ariane_pkg::AMO_ADD: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_ADD;
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ariane_pkg::AMO_AND: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_AND;
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ariane_pkg::AMO_OR: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_OR;
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ariane_pkg::AMO_XOR: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_XOR;
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ariane_pkg::AMO_MAX: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_MAX;
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ariane_pkg::AMO_MAXU: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_MAXU;
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ariane_pkg::AMO_MIN: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_MIN;
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ariane_pkg::AMO_MINU: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_MINU;
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default: amo_op = hpdcache_pkg::HPDCACHE_REQ_LOAD;
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endcase
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end
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// }}}
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@ -129,6 +129,14 @@ module cva6_hpdcache_subsystem
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);
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// }}}
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function int unsigned __minu(int unsigned x, int unsigned y);
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return x < y ? x : y;
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endfunction
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function int unsigned __maxu(int unsigned x, int unsigned y);
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return y < x ? x : y;
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endfunction
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// I$ instantiation
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// {{{
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logic icache_miss_valid, icache_miss_ready;
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@ -181,31 +189,78 @@ module cva6_hpdcache_subsystem
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// NumPorts + 1: Hardware Memory Prefetcher (hwpf)
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localparam int HPDCACHE_NREQUESTERS = NumPorts + 2;
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typedef logic [CVA6Cfg.PLEN-1:0] hpdcache_mem_addr_t;
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typedef logic [CVA6Cfg.MEM_TID_WIDTH-1:0] hpdcache_mem_id_t;
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typedef logic [CVA6Cfg.AxiDataWidth-1:0] hpdcache_mem_data_t;
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typedef logic [CVA6Cfg.AxiDataWidth/8-1:0] hpdcache_mem_be_t;
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localparam hpdcache_pkg::hpdcache_user_cfg_t hpdcacheUserCfg = '{
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nRequesters: HPDCACHE_NREQUESTERS,
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paWidth: CVA6Cfg.PLEN,
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wordWidth: CVA6Cfg.XLEN,
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sets: CVA6Cfg.DCACHE_NUM_WORDS,
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ways: CVA6Cfg.DCACHE_SET_ASSOC,
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clWords: CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.XLEN,
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reqWords: 1,
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reqTransIdWidth: CVA6Cfg.DcacheIdWidth,
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reqSrcIdWidth: 3, // Up to 8 requesters
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victimSel: hpdcache_pkg::HPDCACHE_VICTIM_RANDOM,
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dataWaysPerRamWord: __minu(CVA6Cfg.DCACHE_SET_ASSOC, 128 / CVA6Cfg.XLEN),
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dataSetsPerRam: CVA6Cfg.DCACHE_NUM_WORDS,
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dataRamByteEnable: 1'b1,
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accessWords: __maxu(CVA6Cfg.DCACHE_LINE_WIDTH / (2 * CVA6Cfg.XLEN), 1),
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mshrSets: CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2,
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mshrWays: CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2,
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mshrWaysPerRamWord: CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2,
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mshrSetsPerRam: CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2,
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mshrRamByteEnable: 1'b1,
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mshrUseRegbank: (CVA6Cfg.NrLoadBufEntries < 16),
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refillCoreRspFeedthrough: 1'b1,
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refillFifoDepth: 2,
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wbufDirEntries: CVA6Cfg.WtDcacheWbufDepth,
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wbufDataEntries: CVA6Cfg.WtDcacheWbufDepth,
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wbufWords: 1,
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wbufTimecntWidth: 3,
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wbufSendFeedThrough: 1'b0,
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rtabEntries: 4,
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memAddrWidth: CVA6Cfg.AxiAddrWidth,
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memIdWidth: CVA6Cfg.MEM_TID_WIDTH,
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memDataWidth: CVA6Cfg.AxiDataWidth
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};
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localparam hpdcache_pkg::hpdcache_cfg_t hpdcacheCfg = hpdcache_pkg::hpdcacheBuildConfig(
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hpdcacheUserCfg
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);
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`HPDCACHE_TYPEDEF_MEM_ATTR_T(hpdcache_mem_addr_t, hpdcache_mem_id_t, hpdcache_mem_data_t,
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hpdcache_mem_be_t, hpdcacheCfg);
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`HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t);
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`HPDCACHE_TYPEDEF_MEM_RESP_R_T(hpdcache_mem_resp_r_t, hpdcache_mem_id_t, hpdcache_mem_data_t);
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`HPDCACHE_TYPEDEF_MEM_REQ_W_T(hpdcache_mem_req_w_t, hpdcache_mem_data_t, hpdcache_mem_be_t);
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`HPDCACHE_TYPEDEF_MEM_RESP_W_T(hpdcache_mem_resp_w_t, hpdcache_mem_id_t);
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`HPDCACHE_TYPEDEF_REQ_ATTR_T(hpdcache_req_offset_t, hpdcache_data_word_t, hpdcache_data_be_t,
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hpdcache_req_data_t, hpdcache_req_be_t, hpdcache_req_sid_t,
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hpdcache_req_tid_t, hpdcache_tag_t, hpdcacheCfg);
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`HPDCACHE_TYPEDEF_REQ_T(hpdcache_req_t, hpdcache_req_offset_t, hpdcache_req_data_t,
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hpdcache_req_be_t, hpdcache_req_sid_t, hpdcache_req_tid_t,
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hpdcache_tag_t);
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`HPDCACHE_TYPEDEF_RSP_T(hpdcache_rsp_t, hpdcache_req_data_t, hpdcache_req_sid_t,
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hpdcache_req_tid_t);
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typedef logic [hpdcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t;
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typedef logic [63:0] hwpf_stride_param_t;
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logic dcache_req_valid[HPDCACHE_NREQUESTERS-1:0];
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logic dcache_req_ready[HPDCACHE_NREQUESTERS-1:0];
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hpdcache_pkg::hpdcache_req_t dcache_req [HPDCACHE_NREQUESTERS-1:0];
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hpdcache_req_t dcache_req [HPDCACHE_NREQUESTERS-1:0];
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logic dcache_req_abort[HPDCACHE_NREQUESTERS-1:0];
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hpdcache_pkg::hpdcache_tag_t dcache_req_tag [HPDCACHE_NREQUESTERS-1:0];
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hpdcache_tag_t dcache_req_tag [HPDCACHE_NREQUESTERS-1:0];
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hpdcache_pkg::hpdcache_pma_t dcache_req_pma [HPDCACHE_NREQUESTERS-1:0];
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logic dcache_rsp_valid[HPDCACHE_NREQUESTERS-1:0];
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hpdcache_pkg::hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS-1:0];
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hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS-1:0];
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logic dcache_read_miss, dcache_write_miss;
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logic [ 2:0] snoop_valid;
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logic [ 2:0] snoop_abort;
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hpdcache_pkg::hpdcache_req_offset_t [ 2:0] snoop_addr_offset;
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hpdcache_pkg::hpdcache_tag_t [ 2:0] snoop_addr_tag;
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hpdcache_req_offset_t [ 2:0] snoop_addr_offset;
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hpdcache_tag_t [ 2:0] snoop_addr_tag;
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logic [ 2:0] snoop_phys_indexed;
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logic dcache_cmo_req_is_prefetch;
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@ -256,19 +311,25 @@ module cva6_hpdcache_subsystem
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generate
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dcache_req_i_t dcache_req_ports[HPDCACHE_NREQUESTERS-1:0];
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for (genvar r = 0; r < (NumPorts - 1); r++) begin : cva6_hpdcache_load_if_adapter_gen
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for (genvar r = 0; r < (NumPorts - 1); r++) begin : gen_cva6_hpdcache_load_if_adapter
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assign dcache_req_ports[r] = dcache_req_ports_i[r];
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cva6_hpdcache_if_adapter #(
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.CVA6Cfg (CVA6Cfg),
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.dcache_req_i_t(dcache_req_i_t),
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.dcache_req_o_t(dcache_req_o_t),
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.is_load_port (1'b1)
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.CVA6Cfg (CVA6Cfg),
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.hpdcacheCfg (hpdcacheCfg),
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.hpdcache_tag_t (hpdcache_tag_t),
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.hpdcache_req_offset_t(hpdcache_req_offset_t),
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.hpdcache_req_sid_t (hpdcache_req_sid_t),
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.hpdcache_req_t (hpdcache_req_t),
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.hpdcache_rsp_t (hpdcache_rsp_t),
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.dcache_req_i_t (dcache_req_i_t),
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.dcache_req_o_t (dcache_req_o_t),
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.is_load_port (1'b1)
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) i_cva6_hpdcache_load_if_adapter (
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.clk_i,
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.rst_ni,
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.hpdcache_req_sid_i(hpdcache_pkg::hpdcache_req_sid_t'(r)),
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.hpdcache_req_sid_i(hpdcache_req_sid_t'(r)),
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.cva6_req_i (dcache_req_ports[r]),
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.cva6_req_o (dcache_req_ports_o[r]),
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@ -288,15 +349,21 @@ module cva6_hpdcache_subsystem
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end
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cva6_hpdcache_if_adapter #(
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.CVA6Cfg (CVA6Cfg),
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.dcache_req_i_t(dcache_req_i_t),
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.dcache_req_o_t(dcache_req_o_t),
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.is_load_port (1'b0)
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.CVA6Cfg (CVA6Cfg),
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.hpdcacheCfg (hpdcacheCfg),
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.hpdcache_tag_t (hpdcache_tag_t),
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.hpdcache_req_offset_t(hpdcache_req_offset_t),
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.hpdcache_req_sid_t (hpdcache_req_sid_t),
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.hpdcache_req_t (hpdcache_req_t),
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.hpdcache_rsp_t (hpdcache_rsp_t),
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.dcache_req_i_t (dcache_req_i_t),
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.dcache_req_o_t (dcache_req_o_t),
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.is_load_port (1'b0)
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) i_cva6_hpdcache_store_if_adapter (
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.clk_i,
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.rst_ni,
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.hpdcache_req_sid_i(hpdcache_pkg::hpdcache_req_sid_t'(NumPorts - 1)),
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.hpdcache_req_sid_i(hpdcache_req_sid_t'(NumPorts - 1)),
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.cva6_req_i (dcache_req_ports_i[NumPorts-1]),
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.cva6_req_o (dcache_req_ports_o[NumPorts-1]),
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@ -322,7 +389,7 @@ module cva6_hpdcache_subsystem
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.clk_i,
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.rst_ni,
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.dcache_req_sid_i(hpdcache_pkg::hpdcache_req_sid_t'(NumPorts)),
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.dcache_req_sid_i(hpdcache_req_sid_t'(NumPorts)),
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.cva6_cmo_req_i (dcache_cmo_req_i),
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.cva6_cmo_resp_o(dcache_cmo_resp_o),
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@ -381,15 +448,24 @@ module cva6_hpdcache_subsystem
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`endif
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|
||||
generate
|
||||
for (genvar h = 0; h < NrHwPrefetchers; h++) begin : hwpf_throttle_gen
|
||||
for (genvar h = 0; h < NrHwPrefetchers; h++) begin : gen_hwpf_throttle
|
||||
assign hwpf_throttle_in[h] = hwpf_stride_pkg::hwpf_stride_throttle_t'(hwpf_throttle_i[h]),
|
||||
hwpf_throttle_o[h] = hwpf_stride_pkg::hwpf_stride_param_t'(hwpf_throttle_out[h]);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
hwpf_stride_wrapper #(
|
||||
.NUM_HW_PREFETCH(NrHwPrefetchers),
|
||||
.NUM_SNOOP_PORTS(3)
|
||||
.hpdcacheCfg (hpdcacheCfg),
|
||||
.NUM_HW_PREFETCH (NrHwPrefetchers),
|
||||
.NUM_SNOOP_PORTS (3),
|
||||
.hpdcache_tag_t (hpdcache_tag_t),
|
||||
.hpdcache_req_offset_t(hpdcache_req_offset_t),
|
||||
.hpdcache_req_data_t (hpdcache_req_data_t),
|
||||
.hpdcache_req_be_t (hpdcache_req_be_t),
|
||||
.hpdcache_req_sid_t (hpdcache_req_sid_t),
|
||||
.hpdcache_req_tid_t (hpdcache_req_tid_t),
|
||||
.hpdcache_req_t (hpdcache_req_t),
|
||||
.hpdcache_rsp_t (hpdcache_rsp_t)
|
||||
) i_hwpf_stride_wrapper (
|
||||
.clk_i,
|
||||
.rst_ni,
|
||||
|
|
@ -411,7 +487,7 @@ module cva6_hpdcache_subsystem
|
|||
.snoop_addr_tag_i (snoop_addr_tag),
|
||||
.snoop_phys_indexed_i(snoop_phys_indexed),
|
||||
|
||||
.hpdcache_req_sid_i(hpdcache_pkg::hpdcache_req_sid_t'(NumPorts + 1)),
|
||||
.hpdcache_req_sid_i(hpdcache_req_sid_t'(NumPorts + 1)),
|
||||
|
||||
.hpdcache_req_valid_o(dcache_req_valid[NumPorts+1]),
|
||||
.hpdcache_req_ready_i(dcache_req_ready[NumPorts+1]),
|
||||
|
|
@ -424,10 +500,26 @@ module cva6_hpdcache_subsystem
|
|||
);
|
||||
|
||||
hpdcache #(
|
||||
.NREQUESTERS (HPDCACHE_NREQUESTERS),
|
||||
.HPDcacheMemAddrWidth(CVA6Cfg.PLEN),
|
||||
.HPDcacheMemIdWidth (CVA6Cfg.MEM_TID_WIDTH),
|
||||
.HPDcacheMemDataWidth(CVA6Cfg.AxiDataWidth)
|
||||
.hpdcacheCfg (hpdcacheCfg),
|
||||
.wbuf_timecnt_t (hpdcache_wbuf_timecnt_t),
|
||||
.hpdcache_tag_t (hpdcache_tag_t),
|
||||
.hpdcache_data_word_t (hpdcache_data_word_t),
|
||||
.hpdcache_data_be_t (hpdcache_data_be_t),
|
||||
.hpdcache_req_offset_t(hpdcache_req_offset_t),
|
||||
.hpdcache_req_data_t (hpdcache_req_data_t),
|
||||
.hpdcache_req_be_t (hpdcache_req_be_t),
|
||||
.hpdcache_req_sid_t (hpdcache_req_sid_t),
|
||||
.hpdcache_req_tid_t (hpdcache_req_tid_t),
|
||||
.hpdcache_req_t (hpdcache_req_t),
|
||||
.hpdcache_rsp_t (hpdcache_rsp_t),
|
||||
.hpdcache_mem_addr_t (hpdcache_mem_addr_t),
|
||||
.hpdcache_mem_id_t (hpdcache_mem_id_t),
|
||||
.hpdcache_mem_data_t (hpdcache_mem_data_t),
|
||||
.hpdcache_mem_be_t (hpdcache_mem_be_t),
|
||||
.hpdcache_mem_req_t (hpdcache_mem_req_t),
|
||||
.hpdcache_mem_req_w_t (hpdcache_mem_req_w_t),
|
||||
.hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t),
|
||||
.hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t)
|
||||
) i_hpdcache (
|
||||
.clk_i,
|
||||
.rst_ni,
|
||||
|
|
@ -499,7 +591,7 @@ module cva6_hpdcache_subsystem
|
|||
.wbuf_empty_o(wbuffer_empty_o),
|
||||
|
||||
.cfg_enable_i (dcache_enable_i),
|
||||
.cfg_wbuf_threshold_i (4'd2),
|
||||
.cfg_wbuf_threshold_i (3'd2),
|
||||
.cfg_wbuf_reset_timecnt_on_write_i (1'b1),
|
||||
.cfg_wbuf_sequential_waw_i (1'b0),
|
||||
.cfg_wbuf_inhibit_write_coalescing_i(1'b0),
|
||||
|
|
@ -521,6 +613,7 @@ module cva6_hpdcache_subsystem
|
|||
// {{{
|
||||
cva6_hpdcache_subsystem_axi_arbiter #(
|
||||
.CVA6Cfg (CVA6Cfg),
|
||||
.hpdcache_mem_id_t (hpdcache_mem_id_t),
|
||||
.hpdcache_mem_req_t (hpdcache_mem_req_t),
|
||||
.hpdcache_mem_req_w_t (hpdcache_mem_req_w_t),
|
||||
.hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t),
|
||||
|
|
@ -601,9 +694,16 @@ module cva6_hpdcache_subsystem
|
|||
// Assertions
|
||||
// {{{
|
||||
// pragma translate_off
|
||||
initial
|
||||
assert (hpdcache_pkg::HPDCACHE_REQ_SRC_ID_WIDTH >= $clog2(HPDCACHE_NREQUESTERS))
|
||||
initial begin : initial_assertions
|
||||
assert (hpdcacheCfg.u.reqSrcIdWidth >= $clog2(HPDCACHE_NREQUESTERS))
|
||||
else $fatal(1, "HPDCACHE_REQ_SRC_ID_WIDTH is not wide enough");
|
||||
assert (CVA6Cfg.MEM_TID_WIDTH <= CVA6Cfg.AxiIdWidth)
|
||||
else $fatal(1, "MEM_TID_WIDTH shall be less or equal to the AxiIdWidth");
|
||||
assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(hpdcacheCfg.u.mshrSets * hpdcacheCfg.u.mshrWays) + 1))
|
||||
else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ and I$ miss requests ");
|
||||
assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(hpdcacheCfg.u.wbufDirEntries) + 1))
|
||||
else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ write requests ");
|
||||
end
|
||||
|
||||
a_invalid_instruction_fetch :
|
||||
assert property (
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ module cva6_hpdcache_subsystem_axi_arbiter
|
|||
// {{{
|
||||
#(
|
||||
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
|
||||
parameter type hpdcache_mem_id_t = logic,
|
||||
parameter type hpdcache_mem_req_t = logic,
|
||||
parameter type hpdcache_mem_req_w_t = logic,
|
||||
parameter type hpdcache_mem_resp_r_t = logic,
|
||||
|
|
@ -34,9 +35,7 @@ module cva6_hpdcache_subsystem_axi_arbiter
|
|||
parameter type axi_b_chan_t = logic,
|
||||
parameter type axi_r_chan_t = logic,
|
||||
parameter type axi_req_t = logic,
|
||||
parameter type axi_rsp_t = logic,
|
||||
|
||||
localparam type hpdcache_mem_id_t = logic [CVA6Cfg.MEM_TID_WIDTH-1:0]
|
||||
parameter type axi_rsp_t = logic
|
||||
)
|
||||
// }}}
|
||||
|
||||
|
|
@ -548,18 +547,6 @@ module cva6_hpdcache_subsystem_axi_arbiter
|
|||
initial
|
||||
assert (CVA6Cfg.MEM_TID_WIDTH <= AxiIdWidth)
|
||||
else $fatal("MEM_TID_WIDTH shall be less or equal to AxiIdWidth");
|
||||
initial
|
||||
assert (CVA6Cfg.MEM_TID_WIDTH >= (hpdcache_pkg::HPDCACHE_MSHR_SET_WIDTH + hpdcache_pkg::HPDCACHE_MSHR_WAY_WIDTH + 1))
|
||||
else
|
||||
$fatal(
|
||||
"MEM_TID_WIDTH shall be wide enough to identify all pending HPDcache misses and Icache misses"
|
||||
);
|
||||
initial
|
||||
assert (CVA6Cfg.MEM_TID_WIDTH >= (hpdcache_pkg::HPDCACHE_WBUF_DIR_PTR_WIDTH + 1))
|
||||
else
|
||||
$fatal(
|
||||
"MEM_TID_WIDTH shall be wide enough to identify all pending HPDcache cacheable writes and uncacheable writes"
|
||||
);
|
||||
initial
|
||||
assert (CVA6Cfg.AxiDataWidth <= CVA6Cfg.ICACHE_LINE_WIDTH)
|
||||
else $fatal("AxiDataWidth shall be less or equal to the width of a Icache line");
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit c9956896659489c23dd6d85ce692ab940c74a7e2
|
||||
Subproject commit 57c82d3d2f3c8dcf604b4841d6d7269a682d6462
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies
|
||||
// Alternatives (CEA)
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License, Version 2.1 (the “License”);
|
||||
// you may not use this file except in compliance with the License.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
// You may obtain a copy of the License at https://solderpad.org/licenses/
|
||||
//
|
||||
// Authors: Cesar Fuguet
|
||||
// Date: February, 2023
|
||||
// Description:
|
||||
// Default package with parameters for the HPDcache in a CVA6 platform.
|
||||
// Users can copy this file, rename it, and adapt the configuration values as
|
||||
// needed.
|
||||
|
||||
package hpdcache_params_pkg;
|
||||
// Imports from the CVA6 configuration package
|
||||
// {{{
|
||||
import cva6_config_pkg::CVA6ConfigXlen;
|
||||
import cva6_config_pkg::CVA6ConfigDcacheByteSize;
|
||||
import cva6_config_pkg::CVA6ConfigDcacheSetAssoc;
|
||||
import cva6_config_pkg::CVA6ConfigDcacheLineWidth;
|
||||
import cva6_config_pkg::CVA6ConfigDcacheIdWidth;
|
||||
import cva6_config_pkg::CVA6ConfigWtDcacheWbufDepth;
|
||||
import cva6_config_pkg::CVA6ConfigNrLoadBufEntries;
|
||||
// }}}
|
||||
|
||||
// Definition of constants and functions used only in this file
|
||||
// {{{
|
||||
localparam int unsigned __BYTES_PER_WAY = CVA6ConfigDcacheByteSize / CVA6ConfigDcacheSetAssoc;
|
||||
localparam int unsigned __BYTES_PER_CACHELINE = CVA6ConfigDcacheLineWidth / 8;
|
||||
localparam int unsigned __MAX_RAM_WORD_BITS = 128;
|
||||
|
||||
function int unsigned __minu(int unsigned x, int unsigned y);
|
||||
return x < y ? x : y;
|
||||
endfunction
|
||||
|
||||
function int unsigned __maxu(int unsigned x, int unsigned y);
|
||||
return y < x ? x : y;
|
||||
endfunction
|
||||
// }}}
|
||||
|
||||
// Definition of global constants for the HPDcache data and directory
|
||||
// {{{
|
||||
// HPDcache physical address width (in bits)
|
||||
localparam int unsigned PARAM_PA_WIDTH = riscv::PLEN;
|
||||
|
||||
// HPDcache number of sets
|
||||
localparam int unsigned PARAM_SETS = __BYTES_PER_WAY / __BYTES_PER_CACHELINE;
|
||||
|
||||
// HPDcache number of ways
|
||||
localparam int unsigned PARAM_WAYS = CVA6ConfigDcacheSetAssoc;
|
||||
|
||||
// HPDcache word width (bits)
|
||||
localparam int unsigned PARAM_WORD_WIDTH = CVA6ConfigXlen;
|
||||
|
||||
// HPDcache cache-line width (bits)
|
||||
localparam int unsigned PARAM_CL_WORDS = CVA6ConfigDcacheLineWidth / PARAM_WORD_WIDTH;
|
||||
|
||||
// HPDcache number of words in the request data channels (request and response)
|
||||
localparam int unsigned PARAM_REQ_WORDS = 1;
|
||||
|
||||
// HPDcache request transaction ID width (bits)
|
||||
localparam int unsigned PARAM_REQ_TRANS_ID_WIDTH = CVA6ConfigDcacheIdWidth;
|
||||
|
||||
// HPDcache request source ID width (bits)
|
||||
localparam int unsigned PARAM_REQ_SRC_ID_WIDTH = 3;
|
||||
|
||||
// HPDcache victim selection policy
|
||||
// 0: (Pseudo) RANDOM
|
||||
// 1: (Pseudo) LRU
|
||||
localparam int unsigned PARAM_VICTIM_SEL = 0;
|
||||
// }}}
|
||||
|
||||
// Definition of constants and types for HPDcache data memory
|
||||
// {{{
|
||||
localparam int unsigned PARAM_DATA_WAYS_PER_RAM_WORD = __minu(
|
||||
__MAX_RAM_WORD_BITS / PARAM_WORD_WIDTH, PARAM_WAYS
|
||||
);
|
||||
|
||||
localparam int unsigned PARAM_DATA_SETS_PER_RAM = PARAM_SETS;
|
||||
|
||||
// HPDcache DATA RAM macros whether implements:
|
||||
// - Write byte enable (1'b1)
|
||||
// - Write bit mask (1'b0)
|
||||
localparam bit PARAM_DATA_RAM_WBYTEENABLE = 1'b1;
|
||||
|
||||
// Define the number of memory contiguous words that can be accessed
|
||||
// simultaneously from the cache.
|
||||
// - This limits the maximum width for the data channel from requesters
|
||||
// - This impacts the refill latency (more ACCESS_WORDS -> less REFILL LATENCY)
|
||||
localparam int unsigned PARAM_ACCESS_WORDS = PARAM_CL_WORDS / 2;
|
||||
// }}}
|
||||
|
||||
// Definition of constants and types for the Miss Status Holding Register (MSHR)
|
||||
// {{{
|
||||
// HPDcache MSHR number of sets
|
||||
localparam int unsigned PARAM_MSHR_SETS = 1;
|
||||
|
||||
// HPDcache MSHR number of ways
|
||||
localparam int unsigned PARAM_MSHR_WAYS = CVA6ConfigNrLoadBufEntries;
|
||||
|
||||
// HPDcache MSHR number of ways in the same SRAM word
|
||||
localparam int unsigned PARAM_MSHR_WAYS_PER_RAM_WORD = (PARAM_MSHR_WAYS > 1) ? 2 : 1;
|
||||
|
||||
// HPDcache MSHR number of sets in the same SRAM
|
||||
localparam int unsigned PARAM_MSHR_SETS_PER_RAM = PARAM_MSHR_SETS;
|
||||
|
||||
// HPDcache MSHR RAM whether implements:
|
||||
// - Write byte enable (1'b1)
|
||||
// - Write bit mask (1'b0)
|
||||
localparam bit PARAM_MSHR_RAM_WBYTEENABLE = 1'b1;
|
||||
|
||||
// HPDcache MSHR whether uses FFs or SRAM
|
||||
localparam bit PARAM_MSHR_USE_REGBANK = (PARAM_MSHR_SETS * PARAM_MSHR_WAYS) <= 16;
|
||||
|
||||
// HPDcache feedthrough FIFOs from the refill handler to the core
|
||||
localparam bit PARAM_REFILL_CORE_RSP_FEEDTHROUGH = 1'b1;
|
||||
|
||||
// HPDcache depth of the refill FIFO
|
||||
localparam int PARAM_REFILL_FIFO_DEPTH = 32'd2;
|
||||
// }}}
|
||||
|
||||
// Definition of constants and types for the Write Buffer (WBUF)
|
||||
// {{{
|
||||
// HPDcache Write-Buffer number of entries in the directory
|
||||
localparam int unsigned PARAM_WBUF_DIR_ENTRIES = CVA6ConfigWtDcacheWbufDepth;
|
||||
|
||||
// HPDcache Write-Buffer number of entries in the data buffer
|
||||
localparam int unsigned PARAM_WBUF_DATA_ENTRIES = CVA6ConfigWtDcacheWbufDepth;
|
||||
|
||||
// HPDcache Write-Buffer number of words per entry
|
||||
localparam int unsigned PARAM_WBUF_WORDS = PARAM_REQ_WORDS;
|
||||
|
||||
// HPDcache Write-Buffer threshold counter width (in bits)
|
||||
localparam int unsigned PARAM_WBUF_TIMECNT_WIDTH = 3;
|
||||
localparam bit PARAM_WBUF_SEND_FEEDTHROUGH = 1'b0;
|
||||
// }}}
|
||||
|
||||
// Definition of constants and types for the Replay Table (RTAB)
|
||||
// {{{
|
||||
localparam int PARAM_RTAB_ENTRIES = 4;
|
||||
// }}}
|
||||
endpackage
|
||||
Loading…
Add table
Add a link
Reference in a new issue