mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 12:17:19 -04:00
Connect CSRs info from RVFI_CSR in the testbench & update simulation target (#1879)
This commit is contained in:
Jalali
GitHub
parent
5dceb0d57a
commit
ce0ab81630
9 changed files with 215 additions and 58 deletions
2
verif/env/uvme/uvme_cva6_cfg.sv
vendored
2
verif/env/uvme/uvme_cva6_cfg.sv
vendored
|
|
@ -167,7 +167,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
|
|||
clknrst_cfg.enabled == 1;
|
||||
isacov_cfg.enabled == 1;
|
||||
rvfi_cfg.enabled == 1;
|
||||
rvfi_cfg.csr_enabled == 0;
|
||||
rvfi_cfg.csr_enabled == 1;
|
||||
}
|
||||
|
||||
isacov_cfg.seq_instr_group_x2_enabled == 1;
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ source ./verif/sim/setup-env.sh
|
|||
export cov=1 #enable the Code Coverage
|
||||
|
||||
if ! [ -n "$DV_TARGET" ]; then
|
||||
DV_TARGET=cv32a6_embedded
|
||||
DV_TARGET=cv32a65x
|
||||
fi
|
||||
|
||||
if ! [ -n "$DV_SIMULATORS" ]; then
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ source ./verif/regress/install-spike.sh
|
|||
source ./verif/sim/setup-env.sh
|
||||
|
||||
if ! [ -n "$DV_TARGET" ]; then
|
||||
DV_TARGET=cv32a6_embedded
|
||||
DV_TARGET=cv32a65x
|
||||
fi
|
||||
|
||||
if ! [ -n "$DV_SIMULATORS" ]; then
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ source ./verif/regress/install-spike.sh
|
|||
source ./verif/sim/setup-env.sh
|
||||
|
||||
if ! [ -n "$DV_TARGET" ]; then
|
||||
DV_TARGET=cv32a6_embedded
|
||||
DV_TARGET=cv32a65x
|
||||
fi
|
||||
|
||||
if ! [ -n "$DV_SIMULATORS" ]; then
|
||||
|
|
|
|||
|
|
@ -11,3 +11,4 @@
|
|||
-tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.instr_tracer_i
|
||||
-tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.tracer_if
|
||||
-tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.genblk6.i_cva6_rvfi_combi
|
||||
-tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.i_cva6_rvfi_probes
|
||||
|
|
|
|||
|
|
@ -464,7 +464,7 @@ def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, outp
|
|||
base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv)
|
||||
cmd = get_iss_cmd(base_cmd, elf, target, log)
|
||||
logging.info("[%0s] Running ISS simulation: %s" % (iss, cmd))
|
||||
run_cmd(cmd, 300, debug_cmd = debug_cmd)
|
||||
run_cmd(cmd, 500, debug_cmd = debug_cmd)
|
||||
logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf))
|
||||
if len(iss_list) == 2:
|
||||
compare_iss_log(iss_list, log_list, report)
|
||||
|
|
|
|||
|
|
@ -19,5 +19,34 @@
|
|||
`ifndef __UVMT_CVA6_MACROS_SV__
|
||||
`define __UVMT_CVA6_MACROS_SV__
|
||||
|
||||
// Assign for RVFI CSR interface
|
||||
`define RVFI_CSR_ASSIGN(csr_name) \
|
||||
uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name``_if [RVFI_NRET-1:0](); \
|
||||
for (genvar i = 0; i < RVFI_NRET; i++) begin \
|
||||
assign rvfi_csr_``csr_name``_if[i].clk = clknrst_if.clk; \
|
||||
assign rvfi_csr_``csr_name``_if[i].reset_n = clknrst_if.reset_n; \
|
||||
assign rvfi_csr_``csr_name``_if[i].rvfi_csr_rmask = rvfi_if.rvfi_csr_o.``csr_name``.rmask; \
|
||||
assign rvfi_csr_``csr_name``_if[i].rvfi_csr_wmask = rvfi_if.rvfi_csr_o.``csr_name``.wmask; \
|
||||
assign rvfi_csr_``csr_name``_if[i].rvfi_csr_rdata = rvfi_if.rvfi_csr_o.``csr_name``.rdata; \
|
||||
assign rvfi_csr_``csr_name``_if[i].rvfi_csr_wdata = rvfi_if.rvfi_csr_o.``csr_name``.wdata; \
|
||||
end \
|
||||
|
||||
`define RVFI_CSR_SUFFIX_ASSIGN(csr_name, idx) \
|
||||
uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name````idx``_if [RVFI_NRET-1:0](); \
|
||||
for (genvar i = 0; i < RVFI_NRET; i++) begin \
|
||||
assign rvfi_csr_``csr_name````idx``_if[i].clk = clknrst_if.clk; \
|
||||
assign rvfi_csr_``csr_name````idx``_if[i].reset_n = clknrst_if.reset_n; \
|
||||
assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_rmask = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rmask; \
|
||||
assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_wmask = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wmask; \
|
||||
assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_rdata = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rdata; \
|
||||
assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_wdata = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wdata; \
|
||||
end \
|
||||
|
||||
// Create uvm_config_db::set call for a CSR interface
|
||||
`define RVFI_CSR_UVM_CONFIG_DB_SET(csr_name, idx) \
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if)::set(.cntxt(null), \
|
||||
.inst_name("*"), \
|
||||
.field_name({"csr_", `"csr_name`", "_vif", $sformatf("%0d", ``idx``)}), \
|
||||
.value(rvfi_csr_``csr_name``_if[``idx``])); \
|
||||
|
||||
`endif // __UVMT_CVA6_MACROS_SV__
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ module uvmt_cva6_tb;
|
|||
uvme_cva6_pkg::XLEN
|
||||
) rvfi_instr_if [RVFI_NRET-1:0] ();
|
||||
|
||||
uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_if [RVFI_NRET-1:0]();
|
||||
uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_if [RVFI_NRET-1:0]();
|
||||
|
||||
uvmt_default_inputs_intf default_inputs_vif();
|
||||
|
||||
|
|
@ -109,6 +109,7 @@ module uvmt_cva6_tb;
|
|||
.CVA6Cfg ( CVA6Cfg )
|
||||
) rvfi_if(
|
||||
.rvfi_o(),
|
||||
.rvfi_csr_o(),
|
||||
.tb_exit_o()
|
||||
); // Status information generated by the Virtual Peripherals in the DUT WRAPPER memory.
|
||||
|
||||
|
|
@ -132,7 +133,7 @@ module uvmt_cva6_tb;
|
|||
.core_cntrl_if(core_cntrl_if),
|
||||
.tb_exit_o(rvfi_if.tb_exit_o),
|
||||
.rvfi_o(rvfi_if.rvfi_o),
|
||||
.rvfi_csr_o()
|
||||
.rvfi_csr_o(rvfi_if.rvfi_csr_o)
|
||||
);
|
||||
|
||||
for (genvar i = 0; i < RVFI_NRET; i++) begin
|
||||
|
|
@ -162,6 +163,77 @@ module uvmt_cva6_tb;
|
|||
assign rvfi_instr_if[i].rvfi_mem_wmask = rvfi_if.rvfi_o[i].mem_wmask;
|
||||
end
|
||||
|
||||
`RVFI_CSR_ASSIGN(fflags)
|
||||
`RVFI_CSR_ASSIGN(frm)
|
||||
`RVFI_CSR_ASSIGN(fcsr)
|
||||
`RVFI_CSR_ASSIGN(ftran)
|
||||
`RVFI_CSR_ASSIGN(dcsr)
|
||||
`RVFI_CSR_ASSIGN(dpc)
|
||||
`RVFI_CSR_ASSIGN(dscratch0)
|
||||
`RVFI_CSR_ASSIGN(dscratch1)
|
||||
`RVFI_CSR_ASSIGN(sstatus)
|
||||
`RVFI_CSR_ASSIGN(sie)
|
||||
`RVFI_CSR_ASSIGN(sip)
|
||||
`RVFI_CSR_ASSIGN(stvec)
|
||||
`RVFI_CSR_ASSIGN(scounteren)
|
||||
`RVFI_CSR_ASSIGN(sscratch)
|
||||
`RVFI_CSR_ASSIGN(sepc)
|
||||
`RVFI_CSR_ASSIGN(scause)
|
||||
`RVFI_CSR_ASSIGN(stval)
|
||||
`RVFI_CSR_ASSIGN(satp)
|
||||
`RVFI_CSR_ASSIGN(mstatus)
|
||||
`RVFI_CSR_ASSIGN(mstatush)
|
||||
`RVFI_CSR_ASSIGN(misa)
|
||||
`RVFI_CSR_ASSIGN(medeleg)
|
||||
`RVFI_CSR_ASSIGN(mideleg)
|
||||
`RVFI_CSR_ASSIGN(mie)
|
||||
`RVFI_CSR_ASSIGN(mtvec)
|
||||
`RVFI_CSR_ASSIGN(mcounteren)
|
||||
`RVFI_CSR_ASSIGN(mscratch)
|
||||
`RVFI_CSR_ASSIGN(mepc)
|
||||
`RVFI_CSR_ASSIGN(mcause)
|
||||
`RVFI_CSR_ASSIGN(mtval)
|
||||
`RVFI_CSR_ASSIGN(mip)
|
||||
`RVFI_CSR_ASSIGN(menvcfg)
|
||||
`RVFI_CSR_ASSIGN(menvcfgh)
|
||||
`RVFI_CSR_ASSIGN(mvendorid)
|
||||
`RVFI_CSR_ASSIGN(marchid)
|
||||
`RVFI_CSR_ASSIGN(mhartid)
|
||||
`RVFI_CSR_ASSIGN(mcountinhibit)
|
||||
`RVFI_CSR_ASSIGN(mcycle)
|
||||
`RVFI_CSR_ASSIGN(mcycleh)
|
||||
`RVFI_CSR_ASSIGN(minstret)
|
||||
`RVFI_CSR_ASSIGN(minstreth)
|
||||
`RVFI_CSR_ASSIGN(cycle)
|
||||
`RVFI_CSR_ASSIGN(cycleh)
|
||||
`RVFI_CSR_ASSIGN(instret)
|
||||
`RVFI_CSR_ASSIGN(instreth)
|
||||
`RVFI_CSR_ASSIGN(dcache)
|
||||
`RVFI_CSR_ASSIGN(icache)
|
||||
`RVFI_CSR_ASSIGN(acc_cons)
|
||||
|
||||
`RVFI_CSR_ASSIGN(pmpcfg0)
|
||||
`RVFI_CSR_ASSIGN(pmpcfg1)
|
||||
`RVFI_CSR_ASSIGN(pmpcfg2)
|
||||
`RVFI_CSR_ASSIGN(pmpcfg3)
|
||||
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 0)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 1)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 2)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 3)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 4)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 5)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 6)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 7)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 8)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 9)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 10)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 11)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 12)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 13)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 14)
|
||||
`RVFI_CSR_SUFFIX_ASSIGN(pmpaddr, 15)
|
||||
|
||||
assign default_inputs_vif.hart_id = 64'h0000_0000_0000_0000;
|
||||
assign default_inputs_vif.irq = 2'b00;
|
||||
assign default_inputs_vif.ipi = 1'b0;
|
||||
|
|
@ -173,62 +245,116 @@ module uvmt_cva6_tb;
|
|||
initial begin
|
||||
uvm_config_db#(virtual uvma_rvfi_instr_if )::set(null,"*", $sformatf("instr_vif%0d", i), rvfi_instr_if[i]);
|
||||
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_marchid_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcountinhibit_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mstatus_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ustatus_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mstatush_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_misa_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mtvec_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utvec_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mtval_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utval_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mvendorid_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mscratch_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mepc_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uepc_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcause_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ucause_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mip_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uip_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mie_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uie_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhartid_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mimpid_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_minstret_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_minstreth_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcontext_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcycle_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcycleh_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_dcsr_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_dpc_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_dscratch0_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_dscratch1_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uscratch_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_scontext_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tselect_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata1_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata2_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata3_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tinfo_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tcontrol_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
// set CSRs interface
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(fflags, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(frm, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(fcsr, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(ftran, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(dcsr, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(dpc, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(dscratch0, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(dscratch1, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(sstatus, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(sie, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(sip, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(stvec, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(scounteren, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(sscratch, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(sepc, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(scause, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(stval, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(satp, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mstatus, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mstatush, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(marchid, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(misa, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(medeleg, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mideleg, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mie, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mtvec, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mcounteren, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mscratch, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mepc, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mcause, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mtval, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mip, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(menvcfg, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(menvcfgh, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(marchid, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mhartid, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mcountinhibit, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mcycle, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(mcycleh, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(minstret, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(minstreth, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(cycle, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(cycleh, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(instret, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(instreth, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(dcache, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(icache, i)
|
||||
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg0, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg1, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg2, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpcfg3, i)
|
||||
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr0, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr1, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr2, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr3, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr4, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr5, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr6, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr7, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr8, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr9, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr10, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr11, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr12, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr13, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr14, i)
|
||||
`RVFI_CSR_UVM_CONFIG_DB_SET(pmpaddr15, i)
|
||||
|
||||
//TO-DO - Not yet supported
|
||||
for (int j = 3; j < 32; j++) begin
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent%0d_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0d_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0dh_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent%0d_vif%0d", j, i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0d_vif%0d", j, i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0dh_vif%0d", j, i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_hpmcounter%0d_vif%0d", j, i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_hpmcounter%0dh_vif%0d", j, i), rvfi_csr_if[i]);
|
||||
end
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mconfigptr_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_cycle_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_cycleh_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_instret_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_instreth_vif%0d", i), .value(rvfi_csr_if[i]));
|
||||
for (int j = 0; j < 16; j++) begin
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpcfg%0d_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
for (int j = 4; j < 16; j++) begin
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpcfg%0d_vif%0d", j, i), rvfi_csr_if[i]);
|
||||
end
|
||||
for (int j = 0; j < 64; j++) begin
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpaddr%0d_vif%0d", j, i), .value(rvfi_csr_if[i]));
|
||||
for (int j = 16; j < 64; j++) begin
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpaddr%0d_vif%0d", j, i), rvfi_csr_if[i]);
|
||||
end
|
||||
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mvendorid_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_marchid_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ustatus_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utvec_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utval_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uepc_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ucause_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uip_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uie_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mimpid_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcontext_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uscratch_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_scontext_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tselect_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata1_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata2_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata3_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tinfo_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tcontrol_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mconfigptr_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_time_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_timeh_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_sedeleg_vif%0d", i), rvfi_csr_if[i]);
|
||||
uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_sideleg_vif%0d", i), rvfi_csr_if[i]);
|
||||
end
|
||||
end
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ interface uvmt_rvfi_if #(
|
|||
parameter type rvfi_instr_t = logic
|
||||
) (
|
||||
output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o,
|
||||
output ariane_pkg::rvfi_csr_t rvfi_csr_o,
|
||||
output logic[31:0] tb_exit_o
|
||||
);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue