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Fix some vector length issues in clind and dm, implement haltsum regs in dm_csrs
This commit is contained in:
Michael Schaffner
parent
6b99b47270
commit
d0e657aaab
3 changed files with 58 additions and 32 deletions
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@ -21,7 +21,7 @@ module clint #(
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parameter int unsigned AXI_DATA_WIDTH = 64,
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parameter int unsigned AXI_ID_WIDTH = 10,
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parameter int unsigned NR_CORES = 1 // Number of cores therefore also the number of timecmp registers and timer interrupts
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)(
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic testmode_i,
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@ -35,6 +35,9 @@ module clint #(
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localparam logic [15:0] MSIP_BASE = 16'h0;
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localparam logic [15:0] MTIMECMP_BASE = 16'h4000;
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localparam logic [15:0] MTIME_BASE = 16'hbff8;
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localparam AddrSelWidth = (NR_CORES == 1) ? 1 : $clog2(NR_CORES);
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// signals from AXI 4 Lite
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logic [AXI_ADDR_WIDTH-1:0] address;
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logic en;
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@ -87,11 +90,11 @@ module clint #(
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if (en && we) begin
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case (register_address) inside
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[MSIP_BASE:MSIP_BASE+8*NR_CORES]: begin
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msip_n[$unsigned(address[NR_CORES-1+3:3])] = wdata[0];
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msip_n[$unsigned(address[AddrSelWidth-1+3:3])] = wdata[0];
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end
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[MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin
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mtimecmp_n[$unsigned(address[NR_CORES-1+3:3])] = wdata;
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mtimecmp_n[$unsigned(address[AddrSelWidth-1+3:3])] = wdata;
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end
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MTIME_BASE: begin
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@ -109,11 +112,11 @@ module clint #(
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if (en && !we) begin
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case (register_address) inside
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[MSIP_BASE:MSIP_BASE+8*NR_CORES]: begin
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rdata = msip_q[$unsigned(address[NR_CORES-1+3:3])];
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rdata = msip_q[$unsigned(address[AddrSelWidth-1+3:3])];
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end
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[MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin
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rdata = mtimecmp_q[$unsigned(address[NR_CORES-1+3:3])];
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rdata = mtimecmp_q[$unsigned(address[AddrSelWidth-1+3:3])];
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end
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MTIME_BASE: begin
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@ -17,7 +17,7 @@
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module dm_csrs #(
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parameter int NrHarts = -1
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)(
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic testmode_i,
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@ -89,20 +89,43 @@ module dm_csrs #(
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localparam dm::dm_csr_t ProgBufEnd = dm::dm_csr_t'((dm::ProgBuf0 + {4'b0, dm::ProgBufSize}));
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logic [31:0] haltsum0, haltsum1, haltsum2, haltsum3;
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// TODO(zarubaf) Need an elegant way to calculate haltsums
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// remove assertions below when implemented...
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assign haltsum0 = '0;
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assign haltsum1 = '0;
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assign haltsum2 = '0;
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assign haltsum3 = '0;
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for (genvar i = 0; i < 32; i++) begin
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// assign haltsum0[i] = halted_i[i];
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// TODO(zarubaf) Implement correct haltsum logic
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// assign haltsum0[i] = halted_i[hartsel[19:5]];
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// assign haltsum1[i] = (NrHarts > 32) ? &halted_i[hartsel[19:10] +: 32] : 1'b0;
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// assign haltsum2[i] = (NrHarts > 1024) ? &halted_i[hartsel[19:15] +: 1024] : 1'b0;
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// assign haltsum3[i] = (NrHarts > 32768) ? &halted_i[hartsel[19:19] +: 32768] : 1'b0;
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logic [NrHarts/2**5 :0][31:0] halted_reshaped0;
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logic [NrHarts/2**10:0][31:0] halted_reshaped1;
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logic [NrHarts/2**15:0][31:0] halted_reshaped2;
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logic [(NrHarts/2**10+1)*32-1:0] halted_flat1;
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logic [(NrHarts/2**15+1)*32-1:0] halted_flat2;
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logic [32-1:0] halted_flat3;
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// haltsum0
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assign halted_reshaped0 = halted_i;
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assign haltsum0 = halted_reshaped0[hartsel_o[19:5]];
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// haltsum1
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always_comb begin : p_reduction1
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halted_flat1 = '0;
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for (int k=0; k<NrHarts/2**5; k++) begin
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halted_flat1[k] = &halted_reshaped0[k];
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end
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halted_reshaped1 = halted_flat1;
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haltsum1 = halted_reshaped1[hartsel_o[19:10]];
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end
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// haltsum2
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always_comb begin : p_reduction2
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halted_flat2 = '0;
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for (int k=0; k<NrHarts/2**10; k++) begin
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halted_flat2[k] = &halted_reshaped1[k];
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end
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halted_reshaped2 = halted_flat2;
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haltsum2 = halted_reshaped2[hartsel_o[19:15]];
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end
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// haltsum3
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always_comb begin : p_reduction3
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halted_flat3 = '0;
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for (int k=0; k<NrHarts/2**15; k++) begin
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halted_flat3[k] = &halted_reshaped2[k];
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end
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haltsum3 = halted_flat3;
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end
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dm::dmstatus_t dmstatus;
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dm::dmcontrol_t dmcontrol_d, dmcontrol_q;
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@ -120,7 +143,7 @@ module dm_csrs #(
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// because first data address starts at 0x04
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logic [({3'b0, dm::DataCount} + dm::Data0 - 1):(dm::Data0)][31:0] data_d, data_q;
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logic [NrHarts-1:0] selected_hart;
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logic [HartSelLen-1:0] selected_hart;
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// a successful response returns zero
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assign dmi_resp_o.resp = dm::DTM_SUCCESS;
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@ -149,25 +172,25 @@ module dm_csrs #(
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// we do not support halt-on-reset sequence
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dmstatus.hasresethaltreq = 1'b0;
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// TODO(zarubaf) things need to change here if we implement the array mask
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dmstatus.allhavereset = havereset_q[hartsel_o[HartSelLen-1:0]];
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dmstatus.anyhavereset = havereset_q[hartsel_o[HartSelLen-1:0]];
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dmstatus.allhavereset = havereset_q[selected_hart];
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dmstatus.anyhavereset = havereset_q[selected_hart];
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dmstatus.allresumeack = resumeack_i[hartsel_o[HartSelLen-1:0]];
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dmstatus.anyresumeack = resumeack_i[hartsel_o[HartSelLen-1:0]];
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dmstatus.allresumeack = resumeack_i[selected_hart];
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dmstatus.anyresumeack = resumeack_i[selected_hart];
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dmstatus.allunavail = unavailable_i[hartsel_o[HartSelLen-1:0]];
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dmstatus.anyunavail = unavailable_i[hartsel_o[HartSelLen-1:0]];
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dmstatus.allunavail = unavailable_i[selected_hart];
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dmstatus.anyunavail = unavailable_i[selected_hart];
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// as soon as we are out of the legal Hart region tell the debugger
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// that there are only non-existent harts
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dmstatus.allnonexistent = (hartsel_o > NrHarts[19:0] - 1) ? 1'b1 : 1'b0;
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dmstatus.anynonexistent = (hartsel_o > NrHarts[19:0] - 1) ? 1'b1 : 1'b0;
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dmstatus.allhalted = halted_i[hartsel_o[HartSelLen-1:0]];
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dmstatus.anyhalted = halted_i[hartsel_o[HartSelLen-1:0]];
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dmstatus.allhalted = halted_i[selected_hart];
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dmstatus.anyhalted = halted_i[selected_hart];
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dmstatus.allrunning = ~halted_i[hartsel_o[HartSelLen-1:0]];
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dmstatus.anyrunning = ~halted_i[hartsel_o[HartSelLen-1:0]];
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dmstatus.allrunning = ~halted_i[selected_hart];
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dmstatus.anyrunning = ~halted_i[selected_hart];
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// abstractcs
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abstractcs = '0;
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@ -436,7 +459,7 @@ module dm_csrs #(
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// output multiplexer
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always_comb begin
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selected_hart = hartsel_o[NrHarts-1:0];
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selected_hart = hartsel_o[HartSelLen-1:0];
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// default assignment
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haltreq_o = '0;
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resumereq_o = '0;
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@ -23,7 +23,7 @@ module dm_top #(
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parameter int AxiAddrWidth = -1,
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parameter int AxiDataWidth = -1,
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parameter int AxiUserWidth = -1
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)(
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) (
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input logic clk_i, // clock
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input logic rst_ni, // asynchronous reset active low, connect PoR here, not the system reset
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input logic testmode_i,
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